JP3108366B2 - Analog signal level shift circuit and signal waveform generator using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shift circuit for an analog signal having an offset voltage adjusting function, and BPSK, QPSK, and the like using the level shift circuit.
The present invention relates to a signal waveform generator used for digital communication using a modulation method such as QAM.

[0002]

2. Description of the Related Art Generally, a transmitter for digital communication includes a modulator for generating a baseband signal and a quadrature modulator for performing analog quadrature modulation on the generated baseband signal and outputting a quadrature modulated signal. Have.

[0003] The modulation section has a signal waveform generator for generating a waveform of a baseband signal. The signal waveform generation device stores a roll-off shaped sine wave or cosine wave waveform data and outputs a waveform data at a given address, and converts the waveform data output from the ROM into an analog signal. The D / A converter includes a low-pass filter that reduces a quantization noise in an analog signal output from the D / A converter and outputs a baseband signal.

[0004] Since the modulator and the quadrature modulator are constituted by semiconductor integrated circuits using different processes, the signal potentials for maximizing the performance such as signal / noise ratio and modulation accuracy may be different. In particular, since the components from the D / A converter to the quadrature modulator of the signal waveform generator are constituted by analog circuits, the DC level potential of the signal, that is, the signal ground potential is one of the factors that determine the performance of the device.

For this reason, the signal waveform generator usually has a function of level-shifting (potential conversion) the baseband signal, and furthermore, the signal ground potential of the baseband signal is adjusted to the signal ground optimum for the performance of the quadrature modulator. It has a function of adjusting the offset voltage applied to the baseband signal in order to match the potential.

FIG. 10 shows a D / A of a conventional signal waveform generator.
FIG. 3 is a circuit diagram illustrating a configuration of a 10-bit current cell matrix type D / A converter as an example of a D / A converter used in a conversion unit.

The current cell matrix type D / D shown in FIG.
The A converter includes a plurality of unit current cells, a row decoder, a column decoder, and a load resistor Rdac, selects a unit current cell according to an input code, and supplies a current flowing from the selected unit current cell to the load resistor Rdac. The supply determines the potential of the analog signal Vdac. Each unit current cell outputs a certain current when both the row decode signal and the column decode signal are “H”. The input code is a 10-bit digital signal that represents the waveform of a baseband signal and instructs adjustment of an offset voltage.

[0008] current cell matrix type D / A converter in the unit current cell of the current value I0 / 2 ⁷ is in an array (2
⁷ -1) lined, the current value ^{I0 / 2 8, I0 / 2} 9,
Unit current cells of I0 / 2 ¹⁰ are arranged one by one, respectively. Here, I0 is the value of the full scale current when the output currents of all the unit current cells flow through the load resistance Rdac. Upper 7 bits of the input code is the current value I0 / 2 ⁷
Are converted by the selected number of unit current cells, and the lower 3 bits are D / A converted by selecting whether or not to select the unit current cell weighted with the current amount.
Bit D / A conversion is realized.

FIG. 10 shows a current cell matrix type D / A converter as an example of the D / A converter. In addition to this, the output current of the constant current source is controlled by the requirements of conversion speed and conversion accuracy. There is an example using a current source type D / A converter that determines the output voltage by supplying it to a load resistor (Procedin
gs of the IEEE 1994 Custom Integrated Circuits Con
ference, p16.6.1-16.6.4).

[0010]

However, the conventional signal waveform generator has the following problems.

In a conventional signal waveform generator, a D / A converter has a function of adjusting an offset voltage applied to a baseband signal. When a current cell matrix type D / A converter as shown in FIG. 10 is used in a signal waveform generator, a part of the unit current cells constituting the current cell matrix type D / A converter is used to generate an offset voltage. Used for

FIG. 11 shows an analog signal V generated by the current cell matrix type D / A converter shown in FIG.
It is a figure which shows dac and has shown the case where the signal waveform of amplitude Va is produced | generated. In FIG. 11, SA is a signal having a center potential of Vct, SB is a signal obtained by applying the maximum offset voltage Vofmx to the signal SA, and SC is a signal obtained by applying the minimum offset voltage −Vofmx to the signal SA. Here, it is assumed that the amplitude Va of the signal is equal to the maximum value Vofmx of the offset voltage, and the maximum value of the analog signal Vdac is one third of the power supply potential VDD.

In the case shown in FIG. 11, half of the unit current cells constituting the current cell matrix type D / A converter are used for generating the offset voltage.

However, it can be said that the unit current cell for generating the offset voltage is not involved in the generation of the baseband signal waveform which is an original function of the current cell matrix type D / A converter. Therefore, the current cell matrix type D / A
The power consumption of the whole converter will be greatly increased as compared with the case of simply generating the waveform of the baseband signal. Further, since the required number of unit current cells is increased, the circuit area of the current cell matrix type D / A converter is increased, which causes a problem that the circuit area of the signal waveform generator is increased.

In particular, when the signal waveform generator is used in portable equipment such as a portable telephone or a portable information terminal, the portable equipment is often used continuously for a long time, so that the power consumption is small. In order to reduce the cost, it is an essential condition of the signal waveform generator that the circuit area is small.

In view of the above problems, the present invention provides a level shift circuit for an analog signal having an offset voltage adjusting function. By using the level shift circuit, a signal having low power consumption and a small circuit area is provided. It is an object to provide a waveform generator.

[0017]

Means for Solving the Problems In order to solve the above-mentioned problems, a solution taken by the invention of claim 1 is a level shift circuit for shifting the level of an input analog signal, a first circuit for generating a reference potential. And a second reference potential generating means for generating a reference potential, wherein at least one of the first and second reference potential generating means generates a reference potential according to a given offset voltage adjustment signal. An analog signal having a function of changing a reference potential generated by the first reference potential generating means and a reference potential generated by the second reference potential generating means as a level shift voltage; This level shift voltage is added to a signal in an analog manner, thereby turning off the level shift voltage to be added in an analog manner to the input analog signal. Since changes with Tsu G Voltage adjustment signal, the level shift circuit will have a function to adjust the offset voltage. By using this level shift circuit in the signal waveform generator, the D / A converter does not need to have an offset voltage adjusting function, so that the power consumption of the signal waveform generator can be reduced and the circuit area can be reduced. be able to.

According to a second aspect of the present invention, there is provided a solution to the first aspect of the present invention, wherein an analog signal inputted to a level shift circuit is used as a level shift circuit for level shifting an inputted analog signal. A first signal level shifter for analog-adding a level shift voltage determined according to a bias potential signal applied to a signal potential and outputting the same as an output signal of the level shift circuit; and a first signal level shifter for generating and outputting a first reference potential A first reference potential generating means, a second reference potential generating means for generating and outputting a second reference potential, and having the same level shift characteristics as the first signal level shifter. A second signal level shifter for analog-adding a level shift voltage determined according to a given bias potential signal to a reference potential and outputting the added signal; An output potential of the level shifter is input to a non-inverting input terminal and the first reference potential is input to an inverting input terminal, and a bias potential is set so that an output potential of the second signal level shifter becomes equal to the first reference potential. An operational amplifier for generating a signal and outputting the signal to the first and second signal level shifters, wherein the first reference potential generation means receives an offset voltage adjustment signal as input, and The level shift voltage has a function of changing the first reference potential, and the level shift voltage that is added to the potential of the analog signal input to the level shift circuit in an analog manner changes according to the offset voltage adjustment signal. And the second reference potential.

According to the second aspect of the present invention, a level shift voltage is added to the input analog signal by the first signal level shifter in accordance with the bias potential signal.
Further, the second signal level shifter raises the second reference potential according to the bias potential signal. At this time, the bias potential signal is fed back by the operational amplifier so that the output potential of the second signal level shifter becomes equal to the first reference potential. Since the first signal level shifter and the second signal level shifter have the same level shift characteristics, the level shift voltages analog-added by the first signal level shifter are the first reference potential and the second reference potential. Becomes equal to the potential difference. Here, the first
Can be adjusted by the first reference potential generating means in accordance with the offset voltage adjustment signal, so that the level shift circuit has a function of adjusting the offset voltage.

According to a third aspect of the present invention, the first reference potential generating means in the level shift circuit of the second aspect has a plurality of resistors connected in series between power supply lines for supplying two different potentials. In this case, one of the connection points of the plurality of resistors is selected according to the input offset voltage adjustment signal, and the potential at the connection point is output as the first reference potential.

According to the third aspect of the present invention, the first reference potential generating means selects one of the potentials at the connection points of the plurality of resistors in accordance with the input offset voltage adjustment signal. Generated by Since the first reference potential generating means is constituted by a simple circuit,
A level shift circuit having an offset voltage adjusting function can be easily realized.

According to the invention of claim 4, the second reference potential in the level shift circuit of claim 2 or 3 is equal to the center potential of the analog signal output from the D / A converter. Thereby, the adjustment of the offset voltage becomes more stable.

Further, a solution taken by the invention of claim 5 embodies the invention of claim 1 and is provided as a level shift circuit for level-shifting an input analog signal. A level shift voltage determined according to a given bias potential signal is added to the potential of the analog signal, and a first signal level shifter that outputs the output signal of the level shift circuit and a first reference potential are generated. A first reference potential generating means for generating and outputting a second reference potential; a second reference potential generating means for generating and outputting a second reference potential; and having the same level shift characteristics as the first signal level shifter, A second signal level shifter that analog-adds a level shift voltage determined according to a given bias potential signal to the second reference potential and outputs the resultant signal; The output potential of the second signal level shifter is input to a non-inverting input terminal and the first reference potential is input to an inverting input terminal, so that the output potential of the second signal level shifter becomes equal to the first reference potential. And an operational amplifier for generating such a bias potential signal and outputting the bias potential signal to the first and second signal level shifters. The second reference potential generating means receives an offset voltage adjustment signal as input, and A level shift voltage that has a function of changing the second reference potential in accordance with the adjustment signal, wherein a level shift voltage that is analog-added to the potential of the analog signal input to the level shift circuit includes the first reference potential and the offset voltage It is assumed that the difference is a potential difference from the second reference potential that changes according to the adjustment signal.

According to the fifth aspect of the present invention, a level shift voltage determined according to the bias potential signal by the first signal level shifter is added to the input analog signal in an analog manner. Further, the second signal level shifter raises the second reference potential according to the bias potential signal. At this time, the bias potential signal is fed back by the operational amplifier so that the output potential of the second signal level shifter becomes equal to the first reference potential. Since the first signal level shifter and the second signal level shifter have the same level shift characteristic, the level shift voltage analog-added by the first signal level shifter is equal to the first signal level shifter.
And the potential difference between the second reference potential and the reference potential.

Here, since the second reference potential can be adjusted by the second reference potential generating means in accordance with the offset voltage adjustment signal, the level shift circuit has a function of adjusting the offset voltage.

According to a sixth aspect of the present invention, the second reference potential generating means in the level shift circuit of the fourth aspect has a plurality of resistors connected in series between power supply lines for supplying two different potentials. In this case, one of the connection points of the plurality of resistors is selected according to the input offset voltage adjustment signal, and the potential at the connection point is output as the second reference potential.

According to the sixth aspect of the present invention, one of the potentials at the connection points of the plurality of resistors is selected as the second reference potential by the second reference potential generating means in accordance with the input offset voltage adjustment signal. Generated by Since the second reference potential generating means is constituted by a simple circuit,
A level shift circuit having an offset voltage adjusting function can be easily realized.

According to a seventh aspect of the present invention, the first and second signal level shifters in the level shift circuit according to the second or fifth aspect each include a first MOSFET whose source is connected to a power supply, and a first MOSFET. A second MOSFET whose source is connected to the drain of the first MOSFET and whose drain is grounded.
The gate of the SFET is used as an input terminal and the first M
While the drain of the OSFET is used as an output terminal, the first
Of the MOSFET is used as a bias potential signal input terminal.

According to the seventh aspect of the present invention, since the first and second signal level shifters are constituted by MOSFETs, they can be manufactured by an inexpensive CMOS process, which is effective for cost reduction.

[0030]

[0031]

A solution taken by the invention according to claim 8 is that a signal
Stores the code indicating the signal amplitude value as a waveform generator
Memory that outputs the code of the specified address
Means, and inputting a code output from the storage means.
Then, this code is converted to an analog signal and output.
A converter and an analog output from the D / A converter
Input signal and remove high frequency component of this analog signal
And a low-pass filter that outputs the result of the D / A conversion.
The conversion unit converts the code output from the storage unit into a D / A code.
D / which generates and outputs an analog signal by
A converter and analog output from the D / A converter
Level shift the signal and adjust the offset voltage
Level shift circuit, and the low-pass filter
It is assumed that the signal output from the terminal is an output signal. Soshi
The level shift circuit analog-adds the level shift voltage determined according to the applied bias potential signal to the potential of the analog signal output from the D / A converter, and outputs the result as an output signal of the level shift circuit. First
Signal level shifter, first reference potential generation means for generating and outputting a first reference potential, second reference potential generation means for generating and outputting a second reference potential, and the first signal A second signal level shifter which has the same level shift characteristic as the level shifter, analog-adds a level shift voltage determined according to a given bias potential signal to the second reference potential, and outputs the second reference potential; 2 and the first reference potential is input to an inverting input terminal and the output potential of the second signal level shifter is equal to the first reference potential. An operational amplifier for generating a bias voltage signal and outputting the bias voltage signal to the first and second signal level shifters, wherein the first reference potential generation means receives an offset voltage adjustment signal. And a function of changing the first reference potential in accordance with the offset voltage adjustment signal. The level shift voltage that is added to the analog signal output from the D / A converter in an analog manner is the offset voltage adjustment signal. It is assumed that the difference is a potential difference between the first reference potential and the second reference potential that changes according to a signal.

[0033] Further , a solution taken by the invention of claim 9 is as follows.
Is a code that indicates the amplitude value of the signal as a signal waveform generator.
Output the code of the specified address
And a code output from the storage means.
Convert this code to an analog signal and output
A D / A converter, and an A / D converter output from the D / A converter.
The analog signal is input and the high frequency component of this analog signal
And a low-pass filter that removes and outputs
The / A converter converts the code output from the storage means into a D
/ A conversion to generate and output analog signal
D / A converter, and an A / D converter output from the D / A converter.
Level shift of the analog signal and offset voltage
And a level shift circuit for adjustment.
The signal output from the filter is an output signal.
The level shift circuit analog-adds a level shift voltage determined according to the applied bias potential signal to the potential of the analog signal output from the D / A converter, and outputs the result as an output signal of the level shift circuit. A first signal level shifter, a first reference potential generating means for generating and outputting a first reference potential, a second reference potential generating means for generating and outputting a second reference potential, 1
A second signal level shifter which has the same level shift characteristics as the signal level shifter described above, and analog-adds a level shift voltage determined according to a given bias potential signal to the second reference potential, and outputs the second reference potential. Inputting the output potential of the second signal level shifter to a non-inverting input terminal and inputting the first reference potential to an inverting input terminal;
An operational amplifier for generating a bias potential signal such that an output potential of the second signal level shifter becomes equal to the first reference potential and outputting the bias potential signal to the first and second signal level shifters; The reference potential generation means has a function of receiving the offset voltage adjustment signal as input and changing the second reference potential according to the offset voltage adjustment signal, and performs analog addition to the analog signal output from the D / A converter. The level shift voltage is a potential difference between the first reference potential and a second reference potential that changes according to the offset voltage adjustment signal.

According to the eighth or ninth aspect of the present invention, the D / A conversion
Converter does not have the function to adjust the offset voltage
Adjust the offset voltage using a level shift circuit.
Can be Therefore, the output potential of the D / A converter
The range should be only the range of the potential of the generated signal waveform itself.
Therefore, power consumption can be reduced as compared with the conventional
The road area can be reduced.

[0035]

[0036]

FIG. 1 is a block diagram showing a part of a transmitting section for digital communication. In FIG. 1, reference numeral 1 denotes a modulator for generating a baseband signal, and 2 denotes a quadrature modulator that performs analog quadrature modulation on the generated baseband signal and outputs a quadrature modulated signal. In FIG. 1, the modulation unit 1
Has two signal waveform generators 3a and 3b for generating baseband signals I (t) and Q (t). The signal waveform generator 3a has an R
The signal waveform generator 3b includes a ROM 52b as storage means, a D / A converter 53b, and a low-pass filter 54b. The OM 52a includes a D / A converter 53a and a low-pass filter 54a.

In the modulation section 1, the logic circuit section 51 performs serial / parallel conversion of the input binary transmission data and further performs differential encoding. The ROM 52a stores roll-off shaped sine wave waveform data.
And outputs the waveform data at the address indicated by the data input from. The D / A converter 53a converts the waveform data output from the ROM 52a into an analog signal. ROM 52
The function of a roll-off filter having a raised cosine characteristic or the like is realized by a and the D / A converter 53a.

The ROM 52b stores roll-off shaped cosine wave waveform data.
And outputs the waveform data at the address indicated by the data input from. The D / A converter 53b converts the waveform data output from the ROM 52b into an analog signal. ROM 52
The function of a roll-off filter having a raised cosine characteristic or the like is realized by b and the D / A converter 53b.

The low-pass filter 54a includes a D / A converter 5
It reduces quantization noise in the analog signal output from 3a and outputs a baseband signal I (t) having a signal amplitude Va and a frequency ωb. Also, the low-pass filter 54b
Reduces the quantization noise in the analog signal output from the D / A converter 53b, and reduces the signal amplitude Va and the frequency to ωb
Output the baseband signal Q (t).

In the quadrature modulator, the baseband signal I
(T) and Q (t) are the carrier (c
osωct, −sinωct) and analog addition, and as a result, the quadrature modulated signal S
(T) is output.

In the transmission section of the digital communication shown in FIG. 1, the modulation section 1 is constituted by a semiconductor integrated circuit using a CMOS process in order to reduce the cost by improving the degree of integration. Further, the quadrature modulator 2 is configured by a semiconductor integrated circuit using a bipolar process or GaAs because the carrier frequency ωc increases from several hundred MHz to several GHz. Since the modulator 1 and the quadrature modulator 2 are constituted by semiconductor integrated circuits using different processes, the signal potential at which the performance such as the signal-to-noise ratio and the modulation accuracy is best may be different. In particular, the D / A converters 53a and 53
Since the components from 3b to the quadrature modulator 2 are composed of analog circuits, the DC level potential of the signal, that is, the signal ground potential is one of the factors that determine the device performance.

For this reason, normally, in order to adjust the signal ground potential of the baseband signal to the signal ground potential optimal for the performance of the quadrature modulator 2, the modulator 1 adjusts the offset voltage applied to the baseband signal. Has functions. The modulation unit 1 has the offset voltage adjustment function because the modulation unit 1 is configured by a semiconductor integrated circuit using a CMOS process, the integration degree is high, and the modulation unit 1 has an offset voltage adjustment function. This is because the cost can be reduced.

In this embodiment, the D / A converter is provided with an analog signal level shift circuit having an offset voltage adjusting function, so that the power consumption of the signal waveform generator is reduced and the circuit area is reduced. .

(First Embodiment) FIG. 2 shows a first embodiment of the present invention.
FIG. 4 is a configuration diagram of a D / A conversion unit of the signal waveform generator according to the embodiment. 2, 10 is a level shift circuit,
Reference numeral 11 denotes a 9-bit current cell matrix type D / A converter. The level shift circuit 10 includes a first signal level shifter 12, a signal ground potential determination circuit 13 as first reference potential generation means, a signal center potential reference circuit 14 as second reference potential generation means, and a second signal level shifter. 15 and an operational amplifier 16.

Current cell matrix type D / A converter 11
Is a 9-bit digital signal output from the ROM and represents the waveform of the baseband signal. The signal Vls is input to a low-pass filter.

Current cell matrix type D / A converter 11
Comprises a plurality of unit current cells, a row decoder, a column decoder, and a load resistor Rdac, selects a unit current cell according to a 9-bit input code representing a signal waveform,
The current flowing from the selected unit current cell is determined by the load resistance Rda
c to determine the potential of the analog signal Vdac.

Each unit current cell has a configuration as shown in FIG. 3, and both the row decode signal and the column decode signal are "H".
At this time, a certain current is output. The output current value can be set by adjusting the gate width of the constant current transistor Trcs. Also, a bias voltage externally input to the current cell matrix type D / A converter 11 is supplied to each unit current cell.

Current cell matrix type D / A converter 11
The (2 ⁶ -1) of unit current cells 11a of the current value I0 / 2 ⁷ has been arranged in an array, further the current value I
0/2 ⁸ unit current cell 11b of the current value I0 / 2 ⁹ unit current cells 11c of unit current cells of a current value I0 / 2 ¹⁰ 1
1d are arranged one by one. Here, the current value I0 is the same value as the value of the full-scale current in the 10-bit current cell matrix type D / A converter shown in FIG. The upper 6 bits of the input code are the current value I0 /
D by the number of unit current cells 11a of 2 ⁷ is selected
/ A conversion, and the lower 3 bits are D / A converted depending on whether or not to select the unit current cells 11b, 11c, 11d whose current values are weighted. In addition, 9-bit D / A conversion is realized.

The current cell matrix type D / D shown in FIG.
The smaller number of unit current cells compared to the A converter
This is because it is not necessary to provide the / A converter with a function of adjusting the offset voltage.

The first signal level shifter 12 is a PMOS
This is a source follower circuit composed of 12a and 12b, which analog-adds a level shift voltage to the analog signal Vdac output from the current cell matrix type D / A converter 11 to output a level-shifted signal Vls. The analog signal Vdac is applied to the gate of the PMOS 12a, while the output potential Vbls of the operational amplifier 16 is applied to the gate of the PMOS 12b, and the signal Vls is output from the source of the PMOS 12a (the drain of the PMOS 12b). As will be described later, an offset voltage is applied to this signal Vls. In the PMOS 12a, a substrate and a source are connected to each other in order to prevent a threshold change due to a substrate bias effect.

Here, the source follower circuit will be described. FIG. 4 is a circuit diagram for explaining the operation of the source follower circuit. In FIG. 4, reference numeral 81 denotes a PMOS having a source connected to a power supply and a gate to which a bias potential Vb is applied; and 82, a source connected to a drain of the PMOS 81 and a grounded drain, and a gate connected to the input potential Vin. The applied PMOS. PMOS
The voltage Vou from the drain of 81 (the source of the PMOS 82)
t is output. In addition, the PMOS 82 is connected so that the substrate and the source have the same potential in order to prevent threshold fluctuation due to the substrate bias effect.

The drain current I1 flowing through the PMOS 81 and the drain current I2 flowing through the PMOS 82 are equal, and the following relational expression holds. I1 = I2∴β1 (VDD−Vb−Vtp) ² = β2 (Vout−V
in-Vtp) ² where β1 = (μp · Cox / 2) × (W1 / L1) β2 = (μp · Cox / 2) × (W2 / L2) Vtp: threshold voltage of PMOS μp: PMOS Mobility Cox: gate capacitance of PMOS W1 / L1: ratio of gate width and gate length of PMOS 81 W2 / L2: ratio of gate width and gate length of PMOS 82 When this is solved, the input voltage Vin and the output voltage Vout
Is obtained. Vout = Vin + (β1 / β2) ^1/2 · (VDD−Vb)
+ ｛1- (β1 / β2) ^1/2 ｝ Vtp

This equation shows that the source follower circuit shown in FIG. 4 outputs a voltage Vout obtained by adding the voltage determined by the bias potential Vb to the input voltage Vin in an analog manner. Therefore, the output voltage Vout changes linearly with respect to the input voltage Vin. Here, in order to simplify the following description, a function F (Vin, Vb) satisfying Vout = F (Vin, Vb) is defined.

The signal ground potential determining circuit 13 is composed of a plurality of resistors 13a and a selector circuit 13b connected in series between the power supply and the ground.
Determines the signal ground potential Vsg as the first reference potential by selecting the potential at one connection point of the plurality of resistors 13a. A feature of this embodiment is that the signal ground potential determination circuit 13 has a function of adjusting the offset voltage applied to the signal Vls.

The signal center potential reference circuit 14 is composed of resistors R1 and R2 connected in series between the power supply and the ground, and uses the potential at the connection point of the two resistors as a signal center potential as a second reference potential. Output as Vm. The resistance value of the resistors R1 and R2 is such that the potential Vm is the current cell matrix type D
It is set to be equal to the center potential Vct of the analog signal Vdac output from the / A converter 11.

The second signal level shifter 15 has the same configuration as the first signal level shifter 12, or the element size ratio between the PMOS 15a and the PMOS 15b is the same as the element size ratio between the PMOS 12a and the PMOS 12b forming the first signal level shifter 12. It is configured to be equal. P
While the signal center potential Vm output from the signal center potential reference circuit 14 is applied to the gate of the MOS 15a, PM
The bias potential signal Vbls output from the operational amplifier 16 is applied to the gate of the OS 15b, and the potential Vrpl is output from the source of the PMOS 15a (the drain of the PMOS 15b). The PMOS 15a has a substrate and a source connected to each other in order to prevent a threshold change due to a substrate bias effect.

The operational amplifier 16 receives the output potential Vrpl of the second signal level shifter 15 at the non-inverting input terminal and the signal ground potential Vsg at the inverting input terminal, and outputs a bias potential signal Vbls. Usually, the operational amplifier 16 has a voltage gain of 1000 times or more. Therefore, the operational amplifier 16 sets the bias potential signal Vbls based on the principle of virtual short so that the output potential Vrpl of the second signal level shifter 15 becomes equal to the signal ground potential Vsg. Potential Vrp
When l deviates from the signal ground potential Vsg, the bias potential signal Vbls becomes the potential Vrp
l changes to a value such that it becomes equal to the signal ground potential Vsg.

The operation of the signal waveform generator shown in FIG. 2 will be described in more detail with reference to FIG.

FIG. 5A shows a current cell matrix type D
3 shows a signal waveform of an analog signal Vdac output from the / A converter 11.

Current cell matrix type D / A converter 11
The potential of the analog signal Vdac output from the above becomes a value in the range of the following equation, where Va is the amplitude of the baseband signal and Vct is the center potential of the analog signal Vdac. Vct−Va ≦ Vdac ≦ Vct + Va (11) If Vct−Va = VSS = 0, Vct = Va, and VSS ≦ Vdac ≦ 2Va = I0 / 2 × Rdac.

Since I0 is equal to the full scale current of the current cell matrix type D / A converter shown in FIG. 10, the maximum potential of the analog signal Vdac is half of the maximum potential of the analog signal Vdac shown in FIG. In the description of the subject, it is assumed that the maximum potential of the analog signal Vdac generated by the current cell matrix type D / A converter shown in FIG. 10 is one third of the power supply potential VDD. The maximum potential of Vdac is one sixth of the power supply potential VDD.

FIG. 5B shows the signal ground potential Vsg.
And the range of the signal center potential Vm.

The signal ground potential Vsg is equal to the power supply potential V
Adjustment is made in accordance with the offset voltage adjustment signal 17 with reference to a half of the potential of DD. Offset voltage to Vof
Then, Vsg = VDD / 2 + Vof (12), and the maximum value of the absolute value of the offset voltage Vof is Vofmx
Then, | Vof | ≦ Vofmx, so that VDD / 2−Vofmx ≦ Vsg ≦ VDD / 2 + Vofmx. In FIG. 5B, it is assumed that Vofmx = Va.

The signal center potential Vm is the analog signal Vdac
And is represented by the following equation. Vm = (VDD−VSS) × R2 / (R1 + R2) = Vct (13)

FIG. 5C shows the first signal level shifter 1.
2 shows the signal waveform and range of the output signal Vls. Since the first signal level shifter 12 is a source follower circuit, the output signal Vls can be expressed by the following equation. Vls = F (Vdac, Vbls) Since the second signal level shifter 15 is also a source follower circuit having the same characteristics as the first signal level shifter 12, the output potential Vrpl can be expressed by the following equation. Vrpl = F (Vm, Vbls)

The bias potential signal Vbls output from the operational amplifier 16 has a value such that the output potential Vrpl of the second signal level shifter 15 becomes equal to the signal ground potential Vsg. Therefore, Vrpl = F (Vm, Vbls) = Vsg, and the output signal Vls of the first signal level shifter 12 is obtained.
Can be expressed as: Vls = F (Vdac, Vbls) = F (Vdac + Vm-Vm, Vbls) = Vdac + Vsg-Vm (14)

That is, in the first signal level shifter 12, the signal ground potential Vsg and the signal center potential Vm
Is added to the analog signal Vdac output from the current cell matrix type D / A converter 11 to output a signal Vls. From the formulas (11), (12), (13) and (14), Vls = Vdac + VDD / 2 + Vof-Vm VDD / 2 + Vof-Va≤Vls≤VDD / 2 + Vof + Va (15) Comparing Equations (11) and (15), it can be seen that the central potential Vct in the analog signal Vdac has been linearly level-shifted to the potential (VDD / 2 + Vof) in the signal Vls.

Therefore, the minimum value of the signal Vls {Vls} mi
n and the maximum value {Vls} max are given by equations (11) and (15).
The following equation is obtained. ｛Vls｝ min = VDD / 2 + ｛Vof｝ min-Va = VDD / 2−Vofmx-Va (16) ｛Vls｝ max = VDD / 2 + ｛Vof｝ max + Va = VDD / 2 + Vofmx + Va (17)

Of the signal waveforms shown in FIG. 5C, the waveform shown by the solid line is the waveform of Vls based on VDD / 2, and the waveform shown by the dashed line is the maximum value Vofmx of the offset voltage Vof. It is a waveform of Vls when the minimum value -Vofmx is applied.

FIG. 6 is a circuit diagram showing a configuration of a D / A converter of a signal waveform generator using the current cell matrix type D / A converter shown in FIG. 10 as a comparative example. The figure does not show an offset voltage adjusting function.

In FIG. 6, reference numeral 61 denotes the same 10-bit current cell matrix type D / A converter as shown in FIG. 10, 62 denotes a first signal level shifter constituted by PMOSs 62a and 62b, and 63 denotes a power supply. A signal ground potential determining circuit 64 composed of two resistors connected in series between the ground; 64 a signal center potential reference circuit;
Is a second signal level shifter composed of PMOSs 65a and 65b, and 66 is an operational amplifier. Compared to FIG. 2, the first signal level shifter 62 is the first signal level shifter 12, the signal center potential reference circuit 64 is the signal center potential reference circuit 14, and the second signal level shifter 65 is the second signal level shifter 65.
The signal level shifter 15 and the operational amplifier 66 have the same configuration as the operational amplifier 16, respectively.

FIG. 7 is a diagram showing the level shift of the analog signal Vdac in the comparative example shown in FIG.
(A) shows the signal waveform and the potential range of the analog signal Vdac, (b) shows the signal ground potential Vsg and the signal center potential Vm, and (c) shows the signal waveform and the potential range of the level-shifted baseband signal Vls. .

Current cell matrix type D / A converter 61
The input code input to not only represents the baseband signal waveform, but also has a role of adjusting the offset voltage. Therefore, the analog signal Vdac is obtained by adding the offset voltage Vof to the baseband signal.
Assuming that the amplitude of the baseband signal is Va, the maximum value of the absolute value of the offset voltage Vof is Vofmx, and the center potential of the output potential Vdac is Vct, Vct + Vof−Va ≦ Vdac ≦ Vct + Vof + Va (51), and | Vof | ≦ Vofmx Vct−Vofmx−Va ≦ Vdac ≦ Vct + Vofmx + Va (52) If Vct−Vofmx−Va = VSS = 0, V
ct = Vofmx + Va, and VSS ≦ Vdac ≦ 2Va + 2Vofmx = I0 · Rdac Note that VSS is a ground potential.

Among the waveforms of the analog signal Vdac shown in FIG. 7A, the waveform shown by the solid line is a waveform based on the center potential Vct, and the waveform shown by the dashed line is the maximum value Vofmx of the offset voltage Vof. And a minimum value -Vofmx when applied. In FIG. 7, it is assumed that Vofmx = Va and the maximum value of Vdac is one third of VDD.

Here, it is assumed that the signal ground potential Vsg is set to one half of the power supply potential VDD as shown in FIG. 7B. That is, Vsg = VDD / 2 (53) Further, it is assumed that the signal center potential Vm is equal to the center potential Vct of the analog signal Vdac and is expressed by the following equation. Vm = (VDD−VSS) × R2 / (R1 + R2) = Vct (54)

Assuming that a voltage equal to the potential difference between the signal ground potential Vsg and the signal center potential Vm is applied to the analog signal Vdac and the baseband signal Vls is output, Vls = Vdac + Vsg-Vm (55) ), (53), (54) and (55), Vls = Vdac + VDD / 2−Vct VDD / 2 + Vof−Va ≦ Vls ≦ VDD / 2 + Vof + Va (56) Comparing Equations (51) and (56), it can be seen that the central potential Vct has been linearly level-shifted to the potential VDD / 2.

Therefore, the minimum value ｛Vls｝ min and the maximum value ｛Vls｝ max of the baseband signal Vls are calculated by the following equation (52).
From (56), the following equation is obtained. ｛Vls｝ min = VDD / 2 + ｛Vof｝ min-Va = VDD / 2−Vofmx-Va (57) ｛Vls｝ max = VDD / 2 + ｛Vof｝ max + Va = VDD / 2 + Vofmx + Va (58)

The baseband signal Vls shown in FIG.
Are the waveforms indicated by the solid line with respect to VDD / 2, and the waveforms indicated by the dashed line are the waveforms when the maximum value Vofmx and the minimum value -Vofmx of the offset voltage Vof are applied. .

Equations (15), (16) and (17) correspond to Equations (56), (57) and (58) in the comparative example. Therefore, D of the signal waveform generator shown in FIG.
The / A converter has the same offset voltage adjustment function as the D / A converter of the signal waveform generator shown in FIG. Moreover, as is apparent from the figure, the number of unit current cells of the D / A converter is reduced by almost half. Therefore, the power consumption of the signal waveform generator is reduced and the circuit area is reduced.

As described above, according to the present embodiment, the signal ground potential determining circuit has the function of adjusting the output potential in accordance with the offset voltage adjustment signal, so that the offset voltage applied to the baseband signal can be reduced. It can be adjusted by the decision circuit. Therefore, the number of unit current cells constituting the current cell matrix type D / A converter can be reduced,
A signal waveform generator with low power consumption and small circuit area can be realized.

(Second Embodiment) FIG. 8 shows a second embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating a configuration of a signal waveform generator according to the embodiment. 8, reference numeral 11 denotes a 9-bit current cell matrix type D / A converter, reference numeral 12 denotes a first signal level shifter, reference numeral 15 denotes a second signal level shifter, and reference numeral 16 denotes an operational amplifier. It is the same as what you did. Reference numeral 23 denotes a signal ground potential determination circuit as first reference potential generation means, and reference numeral 24 denotes a signal center potential reference circuit as second reference potential generation means. First signal level shifter 12, signal ground potential determination circuit 2
3. The level shift circuit 20 includes the signal center potential reference circuit 24, the second signal level shifter 15, and the operational amplifier 16.

The signal ground potential determining circuit 23 is composed of two resistors connected in series between the power supply and the ground, and the potential at the connection point between the two resistors is defined as a signal ground potential Vsg as a first reference potential. Output.

The signal center potential reference circuit 24 includes a plurality of resistors 24 a connected in series between a power supply and a ground, and a selector circuit 2.
4b, the selector circuit 24b selects the potential of one connection point of the plurality of resistors 24a in accordance with the input offset voltage adjustment signal 27, thereby determining the signal center potential Vm as the second reference potential. I do.

The feature of this embodiment is that the signal center potential reference circuit 24 has a function of adjusting the offset voltage applied to the signal Vls.

The operation of the signal waveform generator shown in FIG. 8 will be described in more detail with reference to FIG.

FIG. 9A shows a current cell matrix type D
3 shows a signal waveform of an analog signal Vdac output from the / A converter 11. As in the first embodiment, the analog signal Vdac is as follows: Vct−Va ≦ Vdac ≦ Vct + Va (21) ２VSS ≦ Vdac ≦ 2Va = I0 / 2 × Rdac

FIG. 9B shows the signal ground potential Vsg.
And the range of the signal center potential Vm.

The signal ground potential Vsg is equal to the power supply potential VD
It is a half of the potential of D, and Vsg = VDD / 2 (22).

The signal center potential Vm is the analog signal Vdac
Voltage adjustment signal 2 based on the center potential Vct of
Adjusted according to 7. Assuming that the offset voltage is Vof, Vm = Vct + Vof (23), and the maximum absolute value of the offset voltage Vof is Vofmx
Then, since | Vof | ≦ Vofmx, Vct−Vofmx ≦ Vm ≦ Vct + Vofmx. In FIG. 9B, it is assumed that Vofmx = Va.

FIG. 9C shows the first signal level shifter 1
2 shows the signal waveform and range of the output signal Vls. As in the first embodiment, in the first signal level shifter 12, the signal ground potential Vsg and the signal center potential Vm
The offset voltage equal to the potential difference between the analog signal Vda
The signal Vls is output by analog addition to c. Therefore, as in the equation (14), Vls = Vdac + Vsg-Vm (24) Equations (21), (22), (23) and (24)
Therefore, Vls = Vdac + VDD / 2− (Vct + Vof) = Vdac + VDD / 2−Vct−Vof VDD / 2−Vof−Va ≦ Vls ≦ VDD / 2−Vof + Va (25) Comparing Equations (11) and (25), it can be seen that the central potential Vct in the analog signal Vdac has been linearly level-shifted to the potential (VDD / 2-Vof) in the signal Vls. Thus, the offset voltage applied to the signal Vls is adjusted by the offset voltage Vof applied to the signal center potential Vm. However, the sign of the offset voltage Vof is inverted and added to the analog.

Therefore, the minimum value {Vls} mi of signal Vls
The value of n and the maximum value {Vls} min are as follows from Expressions (21) and (25). ｛Vls｝ min = VDD / 2 + ｛-Vof｝ min-Va = VDD / 2-Vofmx-Va (26) ｛Vls｝ max = VDD / 2 + ｛-Vof｝ max + Va = VDD / 2 + Vofmx + Va (27)

Among the signal waveforms shown in FIG. 9C, the waveform shown by the solid line is the signal Vls based on VDD / 2.
And the waveform indicated by the alternate long and short dash line is the waveform of the signal Vls when the maximum value Vofmx and the minimum value −Vofmx of the offset voltage Vof are applied.

Equations (26) and (27) correspond to Equations (57) and (58) in the comparative example. Therefore, the D / A converter of the signal waveform generator shown in FIG. 8 has the same offset voltage adjustment function as the D / A converter of the signal waveform generator shown in FIG. Moreover, as is apparent from the figure, the number of unit current cells of the D / A converter is reduced by almost half. Therefore, the power consumption of the signal waveform generator is reduced and the circuit area is reduced.

As described above, according to the present embodiment, since the signal center potential reference circuit has the function of adjusting the output potential according to the offset voltage adjustment signal, the offset voltage applied to the baseband signal can be reduced by the signal center potential. It can be adjusted by the reference circuit. Therefore, the number of unit current cells constituting the current cell matrix type D / A converter can be reduced, and a signal waveform generation circuit with low power consumption and small circuit area can be realized.

In the embodiment of the present invention, the amplitude Va of the baseband signal and the maximum value Vof of the absolute value of the offset voltage are set.
Although mx is assumed to be equal, the present invention is not limited to this condition, and similar effects can be obtained even if Va and Vofmx are different.

The use of the level shift circuits 10 and 20 shown in the first and second embodiments is not limited to the signal waveform generator, but may be used as an analog signal level shift circuit having an offset voltage adjusting function. It can be used for other applications.

[0097]

As described above, according to the present invention, even if the D / A converter does not have the function of adjusting the offset voltage, the offset voltage can be adjusted by the level shift circuit. Therefore, the range of the output potential of the D / A converter may be only the range of the potential of the signal waveform itself to be generated, so that a signal waveform generating device consuming less power and having a smaller circuit area can be realized. Moreover, it can be realized easily and inexpensively.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a main part of a transmission unit of digital communication.

FIG. 2 is a circuit diagram illustrating a configuration of a D / A converter of the signal waveform generator according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a unit current cell.

FIG. 4 is a circuit diagram showing a configuration of a source follower circuit.

FIG. 5 is a diagram for explaining the operation of the D / A converter of the signal waveform generator according to the first embodiment of the present invention;
(A) is a diagram showing an analog signal Vdac, (b) is a diagram showing a signal ground potential Vsg and a signal center potential Vm,
(C) is a diagram showing a baseband signal Vls to which an offset voltage has been applied.

FIG. 6 is a circuit diagram showing a configuration of a D / A converter of a signal waveform generator as a comparative example.

7A and 7B are diagrams for explaining the operation of the D / A converter of the signal waveform generator as the comparative example shown in FIG.
FIG. 3 is a diagram showing an analog signal Vdac, FIG. 3B is a diagram showing a signal ground potential Vsg and a signal center potential Vm, and FIG. 3C is a diagram showing a baseband signal Vls to which an offset voltage is applied.

FIG. 8 is a circuit diagram illustrating a configuration of a D / A converter of a signal waveform generator according to a second embodiment of the present invention.

FIG. 9 is a diagram for explaining an operation of a D / A converter of the signal waveform generator according to the second embodiment of the present invention;
(A) is a diagram showing an analog signal Vdac, (b) is a diagram showing a signal ground potential Vsg and a signal center potential Vm,
(C) is a diagram showing a baseband signal Vls to which an offset voltage has been applied.

FIG. 10 shows a 10-bit current cell matrix type D / A.
It is a figure showing the composition of a converter.

11 is a diagram showing a waveform of an output signal of the D / A converter shown in FIG.

[Explanation of symbols]

Vdac Analog signal Vsg Signal ground potential (first reference potential) Vm Signal center potential (second reference potential) Vbls Bias potential signal Vls Baseband signal to which offset voltage is applied 1 Modulation unit 2 Quadrature modulator 3a, 3b signal Waveform generator 10 Level shift circuit 11 Current cell matrix type D / A converter 11a Unit current cell (constant current source) 11b, 11c, 11d Unit current cell Rdac Resistance element 12 First signal level shifter 12a, 12b PMOS 13 Signal ground Potential determination circuit (first reference potential generation means) 13a Multiple resistors 13b Selector circuit 14 Signal center potential reference circuit (second reference potential generation means) 15 Second signal level shifter 15a, 15b PMOS 16 Operational amplifier 17 Offset voltage Adjustment signal 20 Level shift circuit 3 Signal ground potential determination circuit (first reference potential generation means) 24 Signal center potential reference circuit (second reference potential generation means) 24a Multiple resistors 24b Selector circuit 27 Offset voltage adjustment signal 51 Logic circuit section 52a, 52b ROM 53a, 53b DA converters 54a, 54b Low-pass filter 61 Current cell matrix type D / A converter 62 First signal level shifter 62a, 62b PMOS 63 Signal ground potential generation circuit 64 Signal center potential reference circuit 65 Second signal level shifter 66 Operational amplifier 81,82 PMOS

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-17415 (JP, A) JP-A-4-271550 (JP, A) JP-A-2-246567 (JP, A) JP-A 64-64 36153 (JP, A) JP-A-56-102120 (JP, A) JP-A-7-162466 (JP, A) JP-A-4-277908 (JP, A) JP-A-2-273400 (JP, A) JP-A-7-245534 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 27/00-27/38 H03M 1/66 H03M 1/74

Claims (9)

(57) [Claims] 1. A level shift circuit for level-shifting an input analog signal, comprising: first reference potential generation means for generating a reference potential; and second reference potential generation means for generating a reference potential. At least one of the first and second reference potential generation means has a function of changing a reference potential according to a given offset voltage adjustment signal, and is generated by the first reference potential generation means. A difference between the reference potential thus generated and the reference potential generated by the second reference potential generating means is set as a level shift voltage, and the level shift voltage is added to the input analog signal in an analog manner. 2. A level shift circuit for level-shifting an input analog signal, wherein a potential of the analog signal input to the level shift circuit is
A first signal level shifter for outputting as an output signal of a level shift circuit by analog-adding a level shift voltage determined according to a given bias potential signal, and a first reference for generating and outputting a first reference potential A potential generating means, a second reference potential generating means for generating and outputting a second reference potential, and having the same level shift characteristic as the first signal level shifter. A second signal level shifter for analog-adding a level shift voltage determined according to a given bias potential signal and outputting the same, and an output potential of the second signal level shifter input to a non-inverting input terminal and the first signal level shifter. A reference potential is input to the inverting input terminal, and a bias potential signal is generated so that the output potential of the second signal level shifter becomes equal to the first reference potential. And an operational amplifier for outputting the first and second signal level shifters to the first and second signal level shifters. The first reference potential generation means receives an offset voltage adjustment signal as an input, and outputs the first reference potential in accordance with the offset voltage adjustment signal. The level shift voltage that is added to the potential of the analog signal input to the level shift circuit in an analog manner is changed by the first reference potential and the first reference potential that change according to the offset voltage adjustment signal. A level shift circuit having a potential difference from a second reference potential. 3. The first reference potential generating means has a plurality of resistors connected in series between power supply lines for supplying two different potentials, and the plurality of resistors are connected in accordance with an offset voltage adjustment signal inputted. 3. The level shift circuit according to claim 2, wherein one of the connection points of the resistors is selected and the potential at the connection point is output as a first reference potential. 4. The level shift circuit according to claim 2, wherein the second reference potential is equal to a center potential of the analog signal input to the level shift circuit. 5. A level shift circuit for level-shifting an input analog signal, wherein the potential of the analog signal input to the level shift circuit is
A first signal level shifter for outputting as an output signal of a level shift circuit by analog-adding a level shift voltage determined according to a given bias potential signal, and a first reference for generating and outputting a first reference potential A potential generating means, a second reference potential generating means for generating and outputting a second reference potential, and having the same level shift characteristic as the first signal level shifter. A second signal level shifter for analog-adding a level shift voltage determined according to a given bias potential signal and outputting the same, and an output potential of the second signal level shifter input to a non-inverting input terminal and the first signal level shifter. A reference potential is input to the inverting input terminal, and a bias potential signal is generated so that the output potential of the second signal level shifter becomes equal to the first reference potential. And an operational amplifier for outputting the signal to the first and second signal level shifters. The second reference potential generating means receives an offset voltage adjustment signal as input, and outputs the second reference potential according to the offset voltage adjustment signal. The level shift voltage that is added to the potential of the analog signal input to the level shift circuit in an analog manner changes according to the first reference potential and the offset voltage adjustment signal. Les which is a potential difference between the second reference potential
Bell shift circuit . 6. The second reference potential generating means includes a plurality of resistors connected in series between power supply lines for supplying two different potentials, and the plurality of resistors are connected in accordance with an input offset voltage adjustment signal. 6. The level shift circuit according to claim 5, wherein one of the connection points of the resistors is selected, and a potential at the selected connection point is output as the second reference potential. 7. The first and second signal level shifters each include a first MOSFET whose source is connected to a power supply, and a first MOSFET whose source is connected to the drain of the first MOSFET and whose drain is grounded. And a gate of the second MOSFET as an input terminal and a drain of the first MOSFET as an output terminal, and a gate of the first MOSFET as a bias potential signal input terminal. The level shift circuit according to claim 2, wherein: 8. A code indicating an amplitude value of a signal is stored.
Storage means for outputting a code at a specified address
And the code output from the storage means as an input,
D / A converter that converts the code into an analog signal and outputs it
And an analog signal output from the D / A conversion unit as an input.
And removes the high-frequency component of this analog signal and outputs it.
A low-pass filter, wherein the D / A converter performs D / A conversion on the code output from the storage unit.
D / A converter that generates and outputs an analog signal according to
And the level of the analog signal output from the D / A converter
Level shift for shifting and adjusting the offset voltage
And a signal output from the low-pass filter as an output signal.
Is intended to, said level shift circuit, the voltage of the analog signal output from D / A converter, a level shift voltage is determined in accordance with a bias potential signal supplied to analog addition, the level shift circuit output A first signal level shifter that outputs as a signal, a first reference potential generation unit that generates and outputs a first reference potential, and a second reference potential generation unit that generates and outputs a second reference potential. A second level shifter which has the same level shift characteristic as the first signal level shifter, and analog-adds a level shift voltage determined according to a given bias potential signal to the second reference potential and outputs the resultant signal; A signal level shifter, and an output potential of the second signal level shifter is input to a non-inverting input terminal, and the first reference potential is input to an inverting input terminal. An operational amplifier for generating a bias potential signal such that the output potential of the second signal level shifter becomes equal to the first reference potential and outputting the bias potential signal to the first and second signal level shifters; The generating means has a function of receiving the offset voltage adjustment signal as input and changing the first reference potential according to the offset voltage adjustment signal. The generating means converts the first reference potential into an analog signal potential output from the D / A converter. level shift voltage added, the signal waveform generator you wherein those wherein the potential difference between the first reference potential and the second reference potential which varies according to the offset voltage adjustment signal. 9. A code indicating a signal amplitude value is stored.
Storage means for outputting a code at a specified address
And the code output from the storage means as an input,
D / A converter that converts the code into an analog signal and outputs it
And an analog signal output from the D / A conversion unit as an input.
And removes the high-frequency component of this analog signal and outputs it.
A low-pass filter, wherein the D / A converter performs D / A conversion on the code output from the storage unit.
D / A converter for generating and outputting an analog signal by a
And the level of the analog signal output from the D / A converter
Level shift for shifting and adjusting the offset voltage
And a signal output from the low-pass filter as an output signal.
Is intended to, said level shift circuit, the voltage of the analog signal output from D / A converter, a level shift voltage is determined in accordance with a bias potential signal supplied to analog addition, the level shift circuit output A first signal level shifter that outputs as a signal, a first reference potential generation unit that generates and outputs a first reference potential, and a second reference potential generation unit that generates and outputs a second reference potential. A second level shifter which has the same level shift characteristic as the first signal level shifter, and analog-adds a level shift voltage determined according to a given bias potential signal to the second reference potential and outputs the resultant signal; A signal level shifter, and an output potential of the second signal level shifter is input to a non-inverting input terminal, and the first reference potential is input to an inverting input terminal. An operational amplifier for generating a bias potential signal such that the output potential of the second signal level shifter becomes equal to the first reference potential and outputting the bias potential signal to the first and second signal level shifters; The generating means has a function of receiving the offset voltage adjustment signal as input and changing the second reference potential according to the offset voltage adjustment signal, and has a function of converting the potential of the analog signal output from the D / A converter into an analog signal. level shift voltage added, the signal waveform generator you, characterized in that a potential difference between the second reference potential which varies according to the offset voltage adjustment signal and said first reference potential.