JP3106671B2 - Error correction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correcting circuit suitable for use in a reproducing system such as a digital VTR such as a so-called digital 8 mm VTR.

[0002]

[Prior art]

In recent years, a digital VTR which digitizes a color video signal and records it on a recording medium such as a magnetic tape.
For example, a D1 format component digital VTR and a D2 format composite digital VTR for broadcasting stations have been put to practical use. These digital VTRs record component signals or composite signals on magnetic tape without compression.

To reduce the amount of tape required for recording and to use a small-sized tape cassette, it has been considered to compress the amount of information of a digital video signal by highly efficient encoding. Transform coding is known as one of the high-efficiency coding methods. Transform coding, particularly two-dimensional coding, divides image data into blocks of, for example, (8 × 8) pixels and performs orthogonal transform for each block. The transform component (referred to as a coefficient) is divided from a DC component into a high-frequency component. Generally, since the DC component is large and the high-frequency component is small, the number of bits is reduced as a whole by allocating an appropriate number of bits to each coefficient. Recently, DCT (Discrete Cosine Transform) has been particularly noted.

[0005]

By the way, since DCT compresses video data and the like in units of blocks, if there is an error in a block, it is processed in units of blocks. When a block having an error is not used, data of the block is not supplied to the IDCT. However, when a block having an error is not used, the block is lost.
It was supplied to CT.

Therefore, when an error occurs in a certain coefficient, if the processing by the IDCT is performed, for example, FIG.
As shown in (1), the originally linear data becomes discontinuous between two broken lines bt, which causes a problem that image quality is deteriorated.

[0007] The present invention has been made in view of the above point, it is possible to minimize the image quality degradation when an error occurs, thereby, when applied to a VTR,
Error correction circuit that can increase the reliability of the digital VTR, reduce the redundancy for error correction, and further increase the recording density, that is, configure a digital VTR for high-quality long-time recording What you want to do.

[0008]

The error correction circuit of the present invention performs a multiply-accumulate process on reproduced video data to obtain a plurality of interpolated value data related to the correlation of the data, as shown in FIGS. Modifying circuits 52, 54 and 60; an edge detecting circuit 56 for detecting edges of video data; and a plurality of interpolated value data from the modifying circuits 52, 54 and 60 based on the detection result from the edge detecting circuit 56 and an error signal. Selection circuits 53, 55, 57, 58, 6 for selectively outputting
1 is provided.

[0009]

According to the present invention described above, the modifying circuits 52, 54 are provided.
A plurality of interpolated value data from the edge detection circuit 5
6 is selectively output based on the detection result and the error signal, so that the image quality degradation at the time of occurrence of an error can be minimized, and when applied to a VTR, the reliability of the VTR can be reduced. , The redundancy for error correction can be reduced, and the recording density can be further increased, that is, a digital VTR for high-quality long-time recording can be configured.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the error correction circuit according to the present invention will be described below in detail with reference to FIG.

First, an example of a VTR to which the error correction circuit of the present embodiment is applied will be described with reference to FIG.

FIG. 2 shows a signal processing section of a recording system and a reproducing system such as an 8 mm VTR. A digital luminance signal is supplied to an input terminal indicated by 1Y, and digital color difference signals CR and CB are supplied to an input terminal indicated by 1C. In this case, the sampling frequency of each signal is 13.5 MHz,
6.75 MHz, and the number of bits per sample is 8 bits. This (4: 2:
The data in the blanking period is removed from the input video signal of 2), and only the information of the effective area is recorded / reproduced. Although not shown, these input signals are obtained by converting the data order from the raster scanning order to the block order by a blocking circuit.

In this example, one field is subdivided into a number of (8 × 4) pixel blocks. FIG. 3 shows an effective area and a block of a luminance signal. For the luminance signal Y,
The effective information of (720 pixels × 304 lines) shown in FIG. 3A is divided into (90 × 76) blocks as shown in FIG. 3B. The color difference signals CR and CB are shown in FIG.
A (45 × 76) block shown in FIG. 4B is formed from valid information of one field of (pixel × 304 line).

The luminance signal and the color difference signal which have been divided into blocks are subjected to DCT conversion by DCT conversion circuits 2Y and 2C, respectively. The coefficient data (for example, one sample, 12 bits) from each of the DCT transform circuits 2Y and 2C is supplied to the shuffling circuits 3Y and 3C, respectively. The shuffling circuits 3Y and 3C include, for example, a field memory and change the arrangement of coefficient data. In addition, the shuffling circuits 3Y and 3C divide the coefficient data of each field into two together with shuffling.

That is, in the shuffling circuits 3Y and 3C, as shown in FIG. 3C, the coefficient data Y 'of the luminance data Y in one field is divided into two with a diagonal line Ya and one with no diagonal line Yb. . Each is (90 × 38)
It is a block. Similarly, as shown in FIG. 4C, one-field coefficient data CR ′ and CB ′ of one field of chrominance data CR and CB are respectively divided into four pieces of (45 × 38) coefficient data CRa, CRb, C
Ba and CBb are formed.

Then, as shown in FIG.
a and the coefficient data CRa and CBa form recording data of 1/4 field, each of which represents Tk = 0 and Tk = 1. Similarly, the coefficient data Yb and the coefficient data CRb and CBb form Tk = Recorded data corresponding to 1/4 field, each represented by 0 and Tk = 1, is formed. The recording data for this フ ィ ー ル ド field is recorded as four tracks. In this example, 2
Double azimuth heads in which two magnetic heads are arranged close to each other are arranged at 180 ° facing intervals, and two tracks are simultaneously formed on the magnet, and one track is formed by four tracks.
The coefficient data relating to the luminance signal and the color difference signal for the field is recorded.

In this case, even if a clog is generated in one magnetic head, the coefficient block of the magnetic head can be allocated even if one magnetic head is clogged by alternately allocating the hatched and non-shaded coefficient data blocks to a plurality of channels. The coefficient blocks located on the upper, lower, left and right sides are reproduced by other magnetic heads, so that the coefficient data can be easily modified. The coefficient data resulting from the shuffling is output in the order of the coefficient data of the AC component in order from the low order to the high order, starting with the coefficient data of the DC component. As an example, the shuffled coefficient data is output from the shuffling circuits 3Y and 3C as a sync block (for example, 32 × 10 × 2 = 640 coefficient data), and the quantization circuit 4
Y, 4C. In the quantization circuits 4Y and 4C, 1
The 2-bit coefficient data is quantized to an n-bit shorter coefficient data.

The outputs of the quantization circuits 4Y and 4C are supplied to variable length coding circuits 5Y and 5C, respectively, and are subjected to, for example, Huffman coding. However, as will be described later, Huffman coding is not performed on DC component coefficients having high importance in the coefficient data. At the outputs of the variable length coding circuits 5Y and 5C, coefficient data of a luminance signal and coefficient data of a color difference signal are alternately mixed. This output data is supplied to buffering circuits 6 and 7, respectively. The buffering circuit 6 keeps the length of the sync block constant, and the buffering circuit 7 keeps the amount of information for each track constant.

As described above, the shuffling circuits 3Y, 3
From C, a predetermined number (640) in sync block units
Is extracted. By the shuffling operation, the variation in the amount of coefficient data of each block in one field is averaged. Therefore, the variable length coding circuit 5
Although the output of Y and 5C has a considerably small variation in length, there is still a difference in length, so that the buffering circuit 6 keeps the length of each sync block constant.

The buffering circuit 7 includes a quantization circuit 4
By controlling the quantization step width in Y and 4C,
The purpose is to make the amount of information per track constant. That is, by increasing the quantization step width,
By reducing the number n of bits of the coefficient data, and conversely, by reducing the quantization step width, the number n of bits of the coefficient data is increased. The buffering circuit 7 is provided with a circuit for estimating the generated data amount of the current field from the data amount of the previous field, and controls the quantization step width in accordance with the estimated generated data amount. In this example, control is performed such that the total sum of the output lengths of the variable length encoding circuits 5Y and 5C is (L × 171) or less in track units.

The output data of the buffering circuit 6 is supplied to a parity generation circuit 8 and undergoes error correction coding processing. As an example, as shown in FIG.
A product code using a Reed-Solomon code is used for each record data of one track in 71). That is, the H parity of the Reed-Solomon code is formed for the coefficient data of each sync block in the horizontal direction, and the V parity of the Reed-Solomon code is formed for the coefficient data and the H parity of the vertical direction. The same error correction encoding is performed on coefficient data of other tracks.

The output of the parity generation circuit 8 is synchronous and I
The sync signal and the ID code are added to the D adding circuit 9 for each sync block. The output of the synchronization and ID addition circuit 9 is supplied to an encoder 10 for channel coding. Channel coding reduces the DC component of the recording data. Although the output data of the channel encoder 10 is not shown, the tape / head system 11 is connected via a recording amplifier.
, And are recorded on a magnetic tape by two tracks.

The shuffling operation will be described with reference to FIG. FIG. 7 shows a shuffling operation on the coefficient data Y ′ of the luminance signal, but the same operation is performed on the color difference signal. FIG. 7A shows coefficient data of the (90 × 38) block shown in FIG. 2C, and the total number of coefficient data is (90 × 38 × 32 = 109,440). Since 640 coefficient data are included in one sync block, 17 sync blocks in one field
It becomes one. With respect to this two-dimensional array, the horizontal position H (=
0 to 89) and its vertical position V (= 0 to 37). As shown in FIG. 7B, a coefficient number C0 is defined for 32 coefficient data in one block.
The coefficient data (C0 = 8) at the upper left corner is of a DC component, and has a higher order in the order of deg-zag scanning, that is, coefficient data of a high-frequency component.

Shuffling is a process in which the track number Tk, sync number SY, and coefficient number Cn are determined according to the following equation. Tk = [(C0 ￥ 16) + H + V] mod.2 SY = [9 × V + 67 × H + 171 × Cn) / 16] mod.171 Cn = [C0 + 8 + 4 × (C0 ￥ 16)] mod.171 where (C0 ￥ 16) means that 0 to 15 of C0 is 0, and 16 to 31 is 1.

According to the above equation, a track number of 0 or 1 is determined, a sync block number of 0 to 170 is determined, and a coefficient number Cn of 0 to 15 is determined. FIG. 7C
This shows a specific example of shuffling.
k = 0, SY = 0, C0 = 8), (Tk = 1, SY =
0, C0 = 8) and (Tk = 0, SY = 0, C0 = 1), respectively. As shown in FIG. 7C, (90
The coefficient data of the (× 38) block is divided into 10 areas of (9 × 38) size, and the coefficient data extracted from the DCT block as shown in each area is included in the same sync block.

The shuffled result is output in order from the lower order to the higher order as shown in FIG. 7D. FIG. 7D
The two data on the left side of are the luminance signal Y and the color difference signal C
3 shows the quantization level for each of the. The next (10 × 2) data are coefficient data of DC components from 10 DCT blocks for each of Y and C. Further, the next (10 × 31 × 2) coefficient data is coefficient data of AC components from 10 DCT blocks for each of Y and C. The DC component data is not subjected to variable length coding (specifically, Huffman coding), and the AC component coefficient data is Huffman coded. The coefficient data of the 31 × 10 AC components are arranged in order from the lower order to the higher order. As a result of this order, as described above, the bits of the coefficient data subjected to the process of keeping the length of the sync block constant are those of the higher-order coefficient data. Since the bits to be controlled by the excess or deficiency are affected by errors of other sync blocks, it is preferable to use higher-order coefficient data having a lower importance than the DC component data.

Reproduction data from the tape head system 11 is supplied to a data reproduction circuit 22 via a composite circuit 21 for channel coding. The reproduced data from the data reproducing circuit 22 is supplied to the inner code decoder 23. Decoder 2
In No. 3, error correction using H parity in the horizontal direction is performed. Then, in the decoder 24 of the next outer code,
Error correction using vertical V parity is performed.
The data on the luminance signal in the error-corrected reproduction data from the decoder 24 is supplied to the variable-length decoder 25Y, and the data on the color difference signal therein is supplied to the decoder 25C. Subsequent to the decoders 25Y and 25C, processing is performed separately for the luminance signal and the color difference signal.
However, these processes are the same.

The variable-length code decoder 25Y and the inverse quantization circuit 26Y are combined, and the quantization level is converted into a representative value by the inverse quantization circuit 26Y. In this case, the decoder 2
From 4, the data indicating the supplied quantization level is used for the inverse quantization circuit 26Y. This representative value is supplied to the deshuffling circuit 27Y, and the data array is returned to the original order, contrary to the shuffling circuit 3Y of the recording system. The output of the deshuffling circuit 27Y is supplied to an error correcting circuit 28Y.

The error correction circuit 28Y corrects an uncorrectable error (indicated by an error flag) by the decoders 23 and 24 with correct coefficient data included in other surrounding DCT blocks. By the shuffling and deshuffling processes, it is possible to prevent all coefficient data of a certain block from being erroneous, and to prevent deterioration in image quality. At the same time, it is possible to reduce the possibility that an error of the coefficient data having the same order as that of the coefficient data to be modified, which is included in another surrounding coefficient block. Therefore,
Error correction ability can be increased. The output data of the error correction circuit 28Y is supplied to the inverse conversion circuit 29Y. The luminance data restored from the coefficient data is output to the output terminal 3.
0Y. The error correction circuit 28Y and an error correction circuit described later are described with reference to FIGS.
And will be described later in detail with reference to

As for the color difference signal, similarly to the above-described luminance signal, the variable length code decoder 25C and the inverse quantization circuit 26 are used.
C, deshuffling circuit 27C, error correction circuit 28
C, an inverse conversion circuit 29C is provided. Output terminal 30
The color difference data restored to C is obtained. Output terminal 30
Since the restored data obtained in Y and 30C are in the order of the blocks, the order of the data is converted in the order of raster scanning by a block decomposition circuit (not shown).

The error correction circuits 28Y and 28Y described above
8C is configured as shown in FIG. 1 in this example.

That is, in FIG. 1, reference numeral 50 denotes an input terminal to which an error flag from the deshuffling circuit 27Y or 27C shown in FIG. 2 is supplied, and reference numeral 51 denotes an input terminal from the deshuffling circuit 27Y or 27C shown in FIG. Is an input terminal to which the deshuffled video data is supplied. The error flags and video data from the deshuffling circuit 27Y or 27C are supplied to the selectors 61, 53, 55, 58, the vertical space concealment circuit 52, the horizontal space concealment circuit 54, and the motion detection circuit via these input terminals 50 and 51. 59 respectively.

The vertical space concealment circuit 52 performs error correction on the video data from the input terminal 51. Similarly, the horizontal space concealment circuit 54 performs error correction on the video data from the input terminal 51. As described in FIG. 2, in the recording system, the video data is DCT
(Discrete cosine transform) processing. In the DCT processing, similarly to the Fourier series expansion, a block of n × m pixels is to be expressed by superimposition of an n × m two-dimensional cosine wave as shown in FIG.

FIG. 2 shows a two-dimensional cosine wave of a plurality of orders represented by DCT. That is,
2B, 2C and 2 from the cosine wave of FIG.
D,..., FIG. 21, FIG. 2J, FIG. 2K,. A block of n × m pixels is expressed by superimposing these two-dimensional cosine waves.

As described with reference to FIG. 11, the loss of a two-dimensional wave due to an error causes significant discontinuities at both ends of the block. To minimize this discontinuity,
Interpolate data lost due to errors. Here, the discontinuity is defined as being represented by the magnitude of the output of the high-pass filter before and after the boundary (the larger the output of the high-pass filter, the more discontinuous).

The horizontal space concealment circuit 5 in FIG.
4 or a specific circuit configuration of the vertical space concealing circuit 52 is shown in FIG. 8 as an error correction circuit.
The equation for calculating the space concealment in 2 is expressed by the following equation 1.
Is shown in the following equation. Further, this operation expression is an expression for calculating the lost DCT processing coefficient euv.

[0037]

(Equation 1)

However, in order to use Equation 1, it is necessary that one error is present in one row in the horizontal direction. Therefore, it is necessary to prevent a plurality of errors from entering one row or one column by shuffling, and to prevent an error from entering an adjacent block. However, as a characteristic of the cosine wave, the even-order wave has the same sign at both ends, and the odd-order wave has different signs at both ends. Therefore, if there are one even-order wave and one odd-order wave, Concealing becomes possible by using it at the boundary between both ends. In principle, this method cannot be used for high frequency components of the original signal. 0 in case of DCT processing of order n
This is effective for coefficients from the next order to the (n / 2-1) th order. As a result, two types of interpolation values can be obtained by independently using the correlation in the horizontal direction and the correlation in the vertical direction.

In the following, the correspondence between the above equation (1) and the error correction circuit (vertical or horizontal space concealment circuit 52 or 54) of FIG. 8 will be described.

In FIG. 8, video data from an input terminal 51 of FIG. 1 is supplied to an IDCT (inverse discrete cosine transform) 70. This video data is subjected to inverse discrete cosine transform by the IDCT 70 and then supplied to the product-sum circuit 71.

First, the horizontal equation in the above equation (1) is given by:
The error correction circuit shown in FIG.
4) will be described. The product-sum circuit 71 calculates Σhg for g, which is the processing result of the IDCT 70, and calculates a value corresponding to each row, using λ as an index. Here, g indicates the result of processing performed by the IDCT 70 including an error, h indicates a coefficient for performing the error calculation processing, and the coefficient h is stored in the coefficient circuit 72. This operation is performed for each row for each of the left and right boundaries of the block. The calculation result is supplied to the product-sum circuit 73 for the left boundary and supplied to the product-sum circuit 75 for the right boundary, and held. Next, the product-sum circuit 73 performs, for example, the remaining calculation of the horizontal expression in Expression 1 with respect to the left boundary. Note that d in the denominator is a transform coefficient for DCT transform. Index i, n of the denominator of this equation
Is independent of the indices j and λ in the numerator, and since this denominator can be calculated in advance for the index i, the product sum coefficient for the left boundary including this is stored in the coefficient circuit 74. . Similarly, the product-sum circuit 75 performs, for example, the remaining calculation of the horizontal expression in Expression 1 with respect to the right boundary. The coefficient circuit 76 stores the product-sum coefficient for the right boundary including the denominator calculated in advance for the index i. Thus, the product-sum circuit 71,
By successively passing through 73 and 75, the horizontal expression in Expression 1 is realized, and a DCT coefficient which is a concealed operation result using the left boundary is output to the output terminal 80.
Is supplied to the fixed contact 55a of the selector 55 of
A DCT coefficient as a result of concealment operation using the right boundary is output to the output terminal 82 and supplied to the fixed contact 55c of the selector 55 in FIG. In the adder circuit 77, the averaging operation of the concealment operation results using the left boundary and the right boundary from both output terminals 80 and 82 is performed, and the DCT coefficient data which becomes the concealed result in consideration of both the boundaries is output to the output terminal. The signal is output to the selector 5 of FIG.
5 fixed contacts 55b.

Next, the vertical expression in the above expression (1) is given by:
8 (vertical space concealment circuit 5)
The correspondence between 2) will be described. The product-sum circuit 71 calculates Σhg for g, which is the processing result of the IDCT 70, and calculates a value corresponding to each row, using λ as an index. Here, g indicates the result of processing performed by the IDCT 70 including an error, h indicates a coefficient for performing the error calculation processing, and the coefficient h is stored in the coefficient circuit 72. This operation is performed for each row for each of the upper and lower boundaries of the block. The calculation result is supplied to the product-sum circuit 73 for the upper boundary and supplied to the product-sum circuit 75 for the lower boundary, and is held. Next, the product-sum circuit 73 performs, for example, the remaining calculation of the vertical expression in the expression (1) with respect to the upper boundary. Note that d in the denominator is a transform coefficient for DCT transform. The coefficient circuit 74 stores, for the index i, the product-sum coefficient for the upper boundary including the denominator calculated in advance. Similarly, the product-sum circuit 75 performs, for example, the remaining calculation of the vertical expression in Expression 1 with respect to the lower boundary. The coefficient circuit 76 stores the product-sum coefficient for the lower boundary including the denominator calculated in advance for the index i. Thus, the product-sum circuits 71, 73, 7
5 successively realizes the vertical expression in the expression (1), and outputs a DCT coefficient which is a concealed operation result using the upper boundary to the output terminal 80. While being supplied to the fixed contact 53a, the output terminal 82 outputs a concealed calculation result using the lower boundary.
The CT coefficient is output and supplied to the fixed contact 53c of the selector 53 in FIG. In the addition circuit 77, both output terminals 8
The averaging operation of the concealment operation results using the upper boundary and the lower boundary from 0 and 82, respectively, is performed, and the DCT coefficient data that becomes the concealed result in consideration of the boundary on both sides is:
The signal is output to the output terminal 81 and supplied to the fixed contact 53b of the selector 53 in FIG.

Referring back to FIG. 1, the edge detection circuit 56 performs a so-called edge detection based on the video data subjected to the inverse discrete cosine transform processing from each IDCT 70 of the vertical and horizontal concealment circuits 52 and 54. The detection result is supplied to selectors 53 and 55 and a selector 58 described later, respectively. Here, the edge indicates the original high-frequency component of the boundary data of the video data.

The motion detection circuit 59 is connected to the input terminal 51.
Video concealment circuit 60 to be described later
The motion detection is performed based on the video data from the output {one-field delay or one-field N-line delay 91 (see FIG. 9)}.

Now, this edge and motion detection is a process for performing an adaptive process, and both must be detected from a state including an error. Therefore, motion detection must be detected from DCT coefficients. In addition, edge detection cannot be performed by performing processing across blocks.

In the motion detection, a DCT coefficient interpolated by a method in a time concealment circuit 60, which will be described later, is determined regardless of the presence or absence of an error in consideration of the interlace.
The absolute value of the difference between the CT coefficient and the coefficient of the block to be concealed when there is no error is obtained, and the maximum value is used as the motion index of the block.

In the edge detection, as shown in FIG. 13, a second derivative is obtained from three points at the end of a certain block, an average is obtained for each side, and the obtained average value is used as an edge index. That is, in this case, |-1 / 4x _m0 + 1 / 2x _m1
-1 / 4x _m2 | get average.

Based on the edge and motion thus obtained, for example, six directions having the highest correlation are determined, and the interpolated value obtained therefrom is adopted.

Further, as shown in FIG. 12, when a block b in which an error e exists is detected and a boundary part p
In the case where the entire video data is composed of a white area p1 and a black area p2 with 3 interposed therebetween, the video data is obtained from a block in six directions adjacent to the block b having the error e currently detected or a block b in the upper, lower, left and right directions. The interpolated values are compared with each other, and a significantly different value is canceled, that is, a correction result is not output to, for example, the selectors 53, 55, and 58.

The selector 53 outputs three outputs from the vertical space concealment circuit 52, that is, an interpolation value (reverse direction) based on the correlation on the block supplied to the fixed contact 53a, and an even number supplied to the fixed contact 53b. The interpolation value (vertical direction) in the case where there is an error in any of the movable contact 5 and the odd number is determined based on the error flag supplied through the input terminal 50 by the selector 53 and the edge detection result.
By 3e, it is selectively supplied to a fixed contact 58a of a selector 58 and an adding circuit 57, respectively, which will be described later.

On the other hand, the selector 55 outputs three outputs from the horizontal space concealment circuit 54, that is, an interpolation value (horizontal direction) based on the left correlation of the block supplied to the fixed contact 55a, and an even number supplied to the fixed contact 55b. The interpolation value (horizontal direction) when there is an error in both the odd and odd numbers, and the interpolation value (horizontal direction) based on the right correlation of the block supplied to the fixed contact 55c are determined by the selector 55 using the input terminal 50.
A movable contact 55e, based on an error flag and an edge detection result supplied through
Are selectively supplied to the fixed contact 58c and the adder circuit 57, respectively.

The adder circuit 57 is connected to each of the selectors 53 and 5
5 is added, and the result of addition is added to the selector 58.
To the fixed contact 58b.

The selector 58 has three outputs: a vertical interpolation value supplied to the fixed contact 58a, a vertical and horizontal addition output from the addition circuit 57 supplied to the fixed contact 58b, and a fixed contact. The horizontal interpolation value supplied to 58c is selectively supplied to the selector 61 based on the error flag and the edge detection result supplied via the input terminal 50.

The time concealment circuit 60 is a circuit for performing interpolation based on, for example, previous field data. When using data from the previous field, the effects of interlacing must be considered. The image data [x _nm ] is interpolated by the image data [x ′ _nm ] of the immediately preceding field.

For example, the image data [x _nm ] can be expressed by the following equations (2) and (3) when the field is odd and when the field is even.

[0056]

(Equation 2)

[0057]

(Equation 3)

Using the equations (2) and (3) and the definition equation of the DCT processing, an equation for obtaining a DCT coefficient to be concealed can be obtained. These equations are shown in Equations 4 and 5 in the case of odd and even.

[0059]

(Equation 4)

[0060]

(Equation 5)

However, the DCT block size N × M, [d
_pm ] is the N-order DCT matrix, y _nm is the DCT coefficient to be obtained, y ′
_nm coefficients of the previous field, Y'u _nm is [y 'block DCT coefficients on the _nm], Y'd _nm is [y' is a DCT coefficient of the block under _nm].

The internal configuration of the time concealment circuit 60 is, for example, as shown in FIG. In this FIG.
Reference numeral 0 denotes an input terminal to which an output signal from the selector 61 shown in FIG.
The output signal from 1 is supplied to a one-field delay (or one-field N-line delay) 91.

The video data delayed by the one-field delay 91 is supplied to an N-line delay 92 and a product-sum circuit 94, respectively. The N-line delay 92 supplies the video data from the one-field delay 91 to the product-sum circuit 93 after further delaying the video data. This product-sum circuit 93 is N
Data obtained by performing a product-sum operation on the delay output data from the line delay 92 is supplied to an adder circuit 95. Sum of products circuit 94
Supplies the sum of the video data from the one-field delay 91 to the adder circuit 95. This adding circuit 95
Supplies the added output obtained by adding the outputs from the product-sum circuits 93 and 94 to the selector 61 shown in FIG.

Returning to FIG. 1, the selector 6
Reference numeral 1 denotes a video data from the input terminal 51, a vertical and horizontal spatial concealment circuit 5 from the selector 58, based on an error flag from the input terminal 50 and an output from the motion detection circuit 59.
2 and 54 and an output from the above-described time concealment circuit 60 are selectively supplied to an IDCT (inverse discrete cosine transform) circuit 29Y or 29C shown in FIG.

As described above, in this example, high-pass filtering is performed on a discontinuous portion (a predetermined range between blocks) and the output thereof is controlled to be "0". Image quality degradation at the time of occurrence can be minimized, so that when applied to a VTR, VT
The reliability of R can be increased, the redundancy for error correction can be reduced, and the recording density can be further increased, that is, a digital VTR for high-quality long-time recording can be configured.

The above embodiment is an example of the present invention.
It goes without saying that various other configurations can be adopted without departing from the spirit of the present invention.

[0067]

According to the present invention described above, a plurality of interpolated value data from the correction circuit are selectively output based on the detection result from the edge detection circuit and the error signal. Image quality degradation can be minimized, and when applied to a VTR, the VTR
This has the advantage that the reliability of the digital VTR can be increased, the redundancy for error correction can be reduced, and the recording density can be increased, that is, a digital VTR for high-quality long-time recording can be configured.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of an error correction circuit according to the present invention.

FIG. 2 is a configuration diagram showing an example of a VTR to which the error correction circuit of the present invention is applied.

FIG. 3 is an explanatory diagram for describing an error correcting circuit according to an embodiment of the present invention;

FIG. 4 is an explanatory diagram for describing an error correcting circuit according to an embodiment of the present invention;

FIG. 5 is an explanatory diagram for explaining an embodiment of an error correction circuit according to the present invention;

FIG. 6 is an explanatory diagram for describing an error correcting circuit according to an embodiment of the present invention;

FIG. 7 is an explanatory diagram for explaining an embodiment of an error correction circuit according to the present invention;

FIG. 8 is a configuration diagram showing a main part of an embodiment of the error correction circuit of the present invention.

FIG. 9 is a configuration diagram showing a main part of an embodiment of the error correction circuit of the present invention.

FIG. 10 is an explanatory diagram of one embodiment of the error correction circuit of the present invention.

FIG. 11 is an explanatory diagram of one embodiment of the error correction circuit of the present invention.

FIG. 12 is an explanatory diagram of one embodiment of the error correction circuit of the present invention.

FIG. 13 is an explanatory diagram of one embodiment of the error correction circuit of the present invention.

[Explanation of symbols]

 52 Vertical space concealment circuit 53, 55, 58, 61 Selector 54 Horizontal space concealment circuit 56 Edge detection circuit 57 Addition circuit 59 Motion detection circuit 60 Time concealment circuit

Claims (1)

(57) [Claims] 1. A modification circuit that performs a sum-of-products process on reproduced video data to obtain a plurality of interpolated value data related to a correlation between the data, an edge detection circuit that detects an edge of the video data, A selection circuit for selectively outputting the plurality of interpolated value data based on a detection result from the edge detection circuit and an error signal.