JP3105110B2 - Arithmetic unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a RISC type arithmetic unit which realizes arithmetic processing of a high-performance electronic computer and is suitable for porting a CISC type program.

[0002]

2. Description of the Related Art Conventional CISC (Complicated Instruc)
In the Option Set Computer type processor, machine language instructions were realized by microprogram control. Here, the machine language instruction is a primitive instruction word provided to a user including an operating system (OS) as an instruction word set of a processor. In a microprogram-controlled processor, as shown in FIG.
One machine language instruction is realized by one or more microprograms.

[0003] In a high-performance processor, machine instructions are pipelined to improve performance. Pipelining refers to several operations for processing machine language instructions, such as instruction fetch, instruction decode, operand address calculation, operand fetch request, microprogram fetch, microprogram decode, operand fetch, arithmetic processing, and result storage. The processing of subsequent instructions is performed in a time-overlapping manner without waiting for the preceding instruction to complete all stages, and is intended to improve performance.

Here, if the microprogram for one machine language instruction is one step, the pipeline flows indefinitely. However, for a machine language instruction whose processing is complicated and processing cannot be completed by a one-step microprogram such as movement of data in the main memory, a microprogram of two or more steps is required. In this case, it is necessary to process a plurality of microprograms by stopping the pipeline to interrupt the flow of machine language instructions, and it is necessary to perform coding in accordance with the operation timing of hardware.

For example, to read data from the main memory, a machine language instruction is described in such a manner as to issue an operand fetch request, execute a nop, and fetch an operand. Thus, microprogram processing can be very inefficient.

In consideration of such a problem, a so-called RI
A computer called a reduced instruction set computer (SC) has been developed. In a RISC-type computer, basically, the hardware is a simple pipeline for processing machine language instructions, and all machine language instructions are hardwired rather than microprogram controlled. Therefore, the function of the machine language instruction is almost 1
Only primitives that can be executed in a cycle.

[0007]

When a conventional program for a CISC-type computer is ported to a RISC-type computer, it is necessary to rewrite the CISC-type instruction with a RISC-type instruction. However, as mentioned above, CISC
Many types of instructions cannot be executed in one cycle. If a large number of RISC-type instructions express a CISC-type instruction,
In some cases, an interrupt occurs during the execution of a RISC-type instruction, and a function equivalent to a CISC-type instruction cannot be appropriately realized. As described above, the conventional RISC type computer does not have high portability of the program for the CISC type computer.

[0008] Instructions for operating the hardware are special in their use, have many restrictions on their use, and depend on the hardware configuration. These instructions are released to the general user by the operating system (O
When included in S), the portability of the OS deteriorates, automatic generation of code (code generation by a compiler) becomes difficult, and a malfunction occurs due to erroneous use by a general user.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a RISC-type arithmetic unit having excellent portability of a program for a CISC-type computer.

Further, the present invention excludes instructions for operating hardware from a machine instruction set in a normal mode.
Another object of the present invention is to provide a highly reliable arithmetic unit that can use such instructions only in the special mode.

[0011]

In order to achieve the above object, an arithmetic unit according to the present invention has an asynchronous mode and an asynchronous mode.
Two operations in firmware mode where interrupts are disabled
System with operation mode, run in normal mode
For normal mode consisting of RISC-type machine instructions to be executed
Storage means for storing the program of
From RISC-type machine instructions to be executed in air mode
Second storing the firmware mode program
Storage means, and machine language instructions of the first and second storage means
Readout means for reading and firmware mode only
Dedicated registers, firmware mode and normal mode
Shared register set shared by
Of the firmware program read from the
Instruction and the dedicated register set and the shared register set
And execute the instructions of the normal mode program.
Execution means for executing using the shared register set.
It is a configuration provided. Further, the arithmetic device according to the present invention includes:
From RISC-type machine language instructions to be executed in normal mode
A normal mode program and the firmware
Instructions and firmware for instructing switching to A mode
Consists of RISC-type machine instructions to be executed in mode
Go to program and normal mode for firmware mode
Storage means for storing a command for instructing return of the
In the normal state, the normal mode stored in the storage means
Instructions of the program for
In response to a command to switch to air mode,
Read the instructions of the program for the firmware mode sequentially
And in response to an instruction to return to normal mode
Reads out the instructions of the normal mode program sequentially
And the instruction read by the reading means.
Execute and switch to the firmware mode
Disables asynchronous interrupts in response to instructions
And responds to the instruction to return to the normal mode.
And means for enabling asynchronous interrupts.
is there.

The present invention also provides a CISI type program.
Among the constituent instructions, multiple microprograms
Controlled, predetermined instructions to be executed
Firmware mode in which asynchronous interrupts are disabled.
Set the firmware and within the firmware mode,
Multiple RISC-type instructions that implement the same function as
By executing the CISC type program,
It is a method of porting to a processor.

[0013]

According to the RISC type arithmetic unit having the above-mentioned structure, the flow is
In the super-privileged mode called the firmware mode ,
(1) Asynchronous interrupts are prohibited, (2) synchronous interrupts can be prohibited if necessary, and (3) a register file dedicated to the firmware mode is arranged.

Due to the features of (1) and (2), the execution of inseparable processing (processing in which an interrupt is not allowed during execution) which has been performed by one conventional CISC-type machine language instruction is performed by a plurality of RISC-type machine instructions. It can be realized by a combination of instructions.

According to the feature (2), in the normal mode, execution of a combination of instructions that cannot be executed as a program error, forced logout processing while ignoring a hardware error trap, and the like can be realized in the super-privileged mode.

The feature (3) eliminates the need for context switching when the firmware operates. Therefore, a program executed in the super-privileged mode can be positioned as one machine language instruction from the normal mode (software in the normal mode).

Further, by introducing the super-privileged mode, it is possible to provide a command for operating hardware as a function for only a specific user using a special mode called the super-privileged mode.

Further, in the method of porting a CISC-type program having the above configuration to a RISC-type processor,
In the SC program, for a predetermined instruction which is controlled by a multi-step microprogram and is to be executed inseparably as an integral part, in the firmware mode,
A plurality of RISCs realizing the same function as the predetermined instruction
Execute the type instruction. According to such a configuration, the RISC
It is possible to prevent a situation in which an interrupt occurs in the middle of the type instruction and the processing is interrupted.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. First, an outline of the arithmetic device according to this embodiment will be described. In the arithmetic unit of this embodiment, the hardware has a simple pipeline configuration for processing machine language instructions, and the machine language instructions are almost only primitives that can be executed in one cycle.

Further, in this embodiment, a super-privileged mode which is a firmware mode is introduced. The firmware mode is set by a firmware call instruction newly introduced in the present embodiment. The firmware mode has the following features as compared with the normal mode in which a machine language instruction of a normal operating system or a user program is executed. (1) Interrupts that occur asynchronously with the execution of instructions, such as input / output (I / O) interrupts, are prohibited. (2) Interrupts that cannot be prohibited in the normal mode, for example, synchronous interrupts such as a program error interrupt and a TLB miss hit interrupt can also be prohibited. (3) In addition to a register file for normal mode (register set), a register file dedicated to firmware mode is provided. Further, if necessary, a work memory dedicated to the firmware mode is provided. (4) A machine language instruction set for controlling hardware highly dependent on hardware, such as directly operating the contents of a cache memory or TLB, can be used.

Due to the features of (1) and (2), the execution of inseparable processing (processing in which an interrupt is not allowed during execution), which has been performed by one conventional CISC-type machine language instruction, is performed by a plurality of RISC-type instructions. It can be realized by a combination of instructions.

According to the feature (2), in the normal mode, execution of a combination of instructions that cannot be executed as a program error, forced logout processing while ignoring a hardware error trap, and the like can be realized.

The feature (3) eliminates the need for context switching when the firmware operates. Therefore, the firmware can be regarded as one machine language instruction from the normal mode (software in the normal mode). On the other hand, in the subroutine in the normal mode, the context needs to be saved / restored when the routine is switched.

Instructions for operating the hardware are special in their use, have many restrictions on their use, and depend on the hardware configuration. If such instructions are included in an operating system (OS) released to general users, portability of the OS will deteriorate, and automatic generation of code (code generation by a compiler) will be difficult. It is not preferable, for example, that a malfunction occurs due to use. For this reason, such instructions should be excluded from the normal mode machine instruction set provided to the general user. According to the feature (4), using a special mode called a firmware mode, an instruction to operate hardware can be provided as a function for a specific user (a user of a level capable of using the firmware mode).

As a method of realizing the firmware mode, for example, a mode switching register is prepared, and when an instruction for setting the firmware mode is detected,
Set the firmware mode in the mode register, disable asynchronous interrupts, set whether to disable synchronous interrupts, and enable the use of a register file exclusively for firmware mode, and use instructions to operate hardware May be made possible.

As a mode switching method, a mode register is controlled by one mode register as shown in FIG. 1 and a mode register is prepared for each stage of the pipeline as shown in FIG. Then, a method of controlling the mode for each stage or the like can be considered.

In the method shown in FIG. 1, it is necessary to flush the pipeline once when switching modes. In the method of FIG. 2, when the instruction for setting the firmware mode is decoded, the firmware mode is set in the mode register of the instruction fetch page and the instruction decode stage, and in the next cycle, the mode register of the instruction execution stage is set. Set the firmware mode to
In the next cycle, the firmware mode is set in the mode register of the result storage stage.

When the instruction for returning to the normal mode is decoded, the normal mode is set in the mode register of the instruction fetch stage and the instruction decode stage, and the normal mode is set in the mode register of the instruction execution stage in the next cycle. Is set, and in the next cycle, the normal mode is set in the mode register of the result storage stage.

Switching between the normal mode and the firmware mode is performed by a branch instruction accompanied by mode switching as shown in FIG. For example, switching from the normal mode to the firmware mode is performed by a firmware call instruction, and return from the firmware mode to the normal mode is performed by a branch instruction to the normal mode.

In such a configuration, when a program for a CISC type computer is ported to a RISC type,
A normal CISC-type instruction is replaced with one or more corresponding RISC-type instructions. On the other hand, for a CISC type instruction executed by a plurality of microprograms and which is to be executed inseparably, a firmware call instruction is provided before a corresponding plurality of R instructions are executed.
The ISC type instruction is coded, and finally, the return instruction to the normal mode is coded.

If coding is performed in this manner, C which has been executed inseparably by a plurality of microprograms
A plurality of RISs with ISC-type instructions with asynchronous interrupts disabled (if necessary, with synchronous interrupts disabled)
It can be executed by a combination of C-type instructions. Therefore, CISC
The function realized by the type instruction can be realized by the RISC type instruction. Moreover, transplantation becomes relatively simple.

Next, the configuration of the arithmetic and control unit according to the first embodiment of the present invention will be specifically described with reference to FIGS. FIGS. 4 and 5 show the configuration of the RISC-type arithmetic and control unit according to the first embodiment of the present invention in combination.

4 and 5, reference numeral 11 denotes a main memory, and reference numeral 12 denotes a processor. The main memory 11 has a normal mode storage area for storing a normal mode program and a firmware mode storage area for storing a firmware mode program.

The processor 12 has a pipeline structure and includes four stages of an instruction fetch stage F, an instruction decode stage D, an instruction execution stage E, and a result storage stage W.

The instruction fetch stage F has an instruction register 101 for latching instructions and operands read from the main memory 11. The instruction decode stage D is an instruction decoder 103 for decoding the instruction held in the instruction register 101, a register file 105 (available in the normal mode and the firmware mode), a firmware mode dedicated register file 107, and a control for holding a decode result. A register 109, a FWM (firmware mode) register 111 set by the instruction decoder 103 when the instruction is a firmware call instruction, and a multiplexer for selecting one of output data of the register file 105 and the firmware mode dedicated register file 107. 113 and 115, multiplexers 113 and 1
AND gate 117 and multiplexer 1 for controlling the control circuit 15
Data register 11 for latching outputs of 13 and 115
9, one of the output of the operand address generation circuit 125, the address register 127, the instruction decoder 103 and the set signal S output from the interrupt control circuit 167, which will be described later,
The multiplexer MPX <b> 1 selects in response to the selection control signal C <b> 1 output from the interrupt control circuit 167 and supplies the selected signal to the FWM register 111.

The instruction execution stage E includes the data register 1
The arithmetic unit 121 performs a numerical operation, a logical operation, and the like on the data held in the arithmetic unit 19 and an arithmetic unit control circuit 123 that controls the arithmetic unit 121 according to the contents of the control register 109.
The instruction execution stage E further includes a TLB (TranslationLoo) for converting a logical address into a physical address at a high speed.
The comparator 131 compares the lower address read from the TLB 129 with the lower bit of the address supplied from the address register 127, the TLB hit register 133 sets the comparison result of the comparator 131, and stores the operand. Cache memory 13
5. Work memory 137 dedicated to firmware mode
A register 141 for latching contents of a read data register 139 for holding read data of the cache memory 135 or the work memory 137 and a control register 109 and outputting a selection control signal C2 of "1" level when the instruction is a load instruction; An operation result register 143 for latching the result of the operation by the operation unit 121;

The result storage stage W is provided with a storage control circuit 145 for storing the operation result held in the operation result register 143 or the output data D of the read data register 139 in a register file when the load instruction is executed. .

Further, the processor 12 includes the main memory 11
The location counter 151 for specifying the instruction address set in the location counter is incremented by +1.
Update circuit 153 for updating, subroutine call, firmware call, branch destination address generation circuit 155 for generating a branch destination address (physical address) when a return to the normal mode occurs, output address of update circuit 153 and branch destination A multiplexer 157 for selecting one of the output addresses of the address generation circuit 155, an output address of the multiplexer 157, and an interrupt control circuit 16 described later.
7 is provided with a multiplexer 159 for selecting one of the 7 output addresses (interrupt vector).

Although the drawing shows that instructions are directly fetched from the main memory without using a cache memory, a cache memory may be used like an operand.

Further, the processor 12 includes an inverter 161 for inverting the data held in the FWM register 111 for interrupt control, an AND gate 163 for masking an asynchronous interrupt signal according to the output of the inverter 161,
165, the interrupt control circuit 167, the instruction decoder 10
3, an OR gate 173 for ORing the output of the enable register 171 with the output of the inverter 161 and an AND gate 17 for ANDing the output of the OR gate 173 and the synchronous interrupt signal.
5 is provided.

Next, the operation of the arithmetic and control unit shown in FIGS. 1. Operation in Normal Mode 1.1 In a normal state, the multiplexer 157 selects the output of the update circuit 153, and the multiplexer 159 selects the output of the multiplexer 157. Therefore, the count value of the location counter 151 sequentially counts up, and the machine language instructions in the normal mode storage area addressed by the location counter 151 are sequentially read,
They are sequentially set in the instruction register 101.

The instruction decoder 103 includes an instruction register 101
Decodes the instruction held in the register file 10
5, one corresponding to the decoding result is selected, and the two data held in the register are read out. In the normal state, data "0" is held in the FWM register 111, the output of the AND gate 117 is also "0", and the multiplexers 113 and 115 select the output data of the register file 105. Multiplexer 113
And 115 are latched in the data register 119.

The decoding result of the instruction decoder 103 is latched in the control register 109. Arithmetic unit control circuit 123
Is calculated based on the contents of the control register 109.
1 and performs operations such as adding two data held in the data register 119 and taking a logical product.

The decoding result of the instruction decoder 103 is also stored in the register 141 via the control register 109. Result storage control unit 1 based on the contents of register 141
Numeral 45 writes the operation result held in the operation result register 143 to the register file 105. In the case of a load instruction, the register 141 supplies the selection control signal C2 of “1” level to the multiplexer MPX2, and the multiplexer MPX2 reads the read data (from the cache memory 135 or the work memory 137) set in the read data register 139. (Read data) D is selected. The result storage control unit 145 includes the multiplexer MPX2
Is written to the register file 105.

Thus, the processing of the instruction fetch, instruction decode, instruction execution, and result storage stages for one instruction is completed. Then, the processing in the above-described four stages is executed in parallel, and pipeline processing is realized.

1.2 In the normal mode, when a subroutine call instruction or the like is fetched and decoded,
The branch destination address generation circuit 155 generates a branch destination address based on an instruction from the instruction decoder 103, the contents of the instruction register 101, data read from the register set 105, and the like. The multiplexer 157 selects this address according to the instruction from the instruction decoder 103,
Further, the multiplexer 159 includes the interrupt control circuit 1
According to the instruction from 67, this address is selected and set in the location counter 151. Therefore, thereafter, the machine language instructions stored after the address of the call destination are sequentially fetched and executed.

1.3 In the case where the decoded instruction is an instruction that needs to generate an operand address, the operand address generation circuit 125 outputs the operand address based on the instruction from the instruction decoder 103 and the instruction from the normal mode register group 105. Generate This operand address is supplied to the TLB 129 via the register 127, and is converted into a physical address.

1.4 When an instruction or the like whose use in the normal mode is prohibited is decoded, the instruction decoder 103 outputs a program error signal (one of synchronous interrupt signals). In the normal mode, the value held in the FWM register 111 is “0”, the output of the inverter 161 is at “1” level, the output of the OR gate 173 is at “1” level, the AND gate 175 is opened, and the program error signal is output. Is supplied to the interrupt control circuit 167. The interrupt control circuit 167 specifies the contents of the interrupt, and the start address (interrupt vector) of the storage area for the program error processing
Is generated and supplied to the multiplexer 159 to set the control signal to “1”. The multiplexer 159 selects this address in response to the control signal, and
Set to 51. Thereafter, the interrupt processing program is sequentially executed.

A firmware mode, which will be described later, may be set according to the type of interrupt, and interrupt processing may be executed in the firmware mode. For example, upon detecting a specific interrupt, the interrupt control unit 167 sets the set signal S and the selection control signal C1 to “1”. As a result, the multiplexer MPX1 outputs 1 and "1" is set in the FWM register 111, the firmware mode is set, and the subsequent processing is executed. Note that all the interrupt processes may be executed in the firmware mode.

Similarly, for other asynchronous interrupts and synchronous interrupts, an interrupt signal is accepted and interrupt processing is executed. 2. Operation in Firmware Mode 2.1 When the instruction decoder 103 decodes the firmware call instruction, it stores "1" in the FWM register 111.
And sends a command to the branch destination address generation circuit 155. The branch destination address generation circuit 155 generates a branch destination address.
It is set in the location counter 151 via 57 and 159. Thereafter, the machine language instructions in the firmware mode are sequentially fetched and executed. Also in the firmware mode, the instructions themselves are the same as the instructions in the normal mode, and the pipeline processing is the same as in the normal mode.

In the firmware mode, the instruction decoder 103 sets the registers in the register file 105 and the firmware mode register file 107 to 1
And reads the stored data. Since “1” is set in the FWM register 111, the AND gate 11
7 is opened, and the multiplexers 113 and 115 select the output data of the selected register set 105 or 107 under the control of the instruction decoder 103.

The output of the inverter 161 becomes "0",
AND gates 163 and 165 are closed, and the asynchronous interrupt signal is masked and inhibited. Further, until an instruction to set “1” in the enable register 171 is executed,
The output of the OR gate 172 becomes "0", the AND gate 175 closes, and the synchronous interrupt signal is also masked and inhibited.

2.2 The instruction decoder 103 sets "1" in the enable register 171 when decoding the instruction for setting the enable register 171. Then, the output of the OR gate 172 becomes "1", the AND gate 175 opens, and the synchronous interrupt signal is accepted.

2.3 The instruction decoder 103 decodes the return instruction to the normal mode, and
11 is set to “0”, and the branch destination address generation circuit 15 is set.
Send a command to 5. The branch destination address generation circuit 155 generates a branch destination address, and outputs the multiplexers 157 and 159.
To the location counter 151 via Therefore, thereafter, the machine instructions following the return destination are sequentially fetched and executed.

3. Next, the case of rewriting the contents of the TLB 129 and the work memory 1 dedicated to the firmware mode
When data is stored in the memory 37, the operation in the firmware mode will be specifically described by taking as an example the case of executing an instruction whose use is prohibited in the normal mode.

3.1 Rewriting the TLB is a process of directly operating hardware, and a small mistake may cause a serious failure. Therefore, in the present embodiment, this type of instruction is hidden in the firmware mode, and this function is provided only to a user who can use the firmware mode. For this reason, in the present embodiment, for example, FIG.
The program for rewriting the TLB is stored in the main memory 1 as shown in FIG.
Save to 1.

In the normal mode, when the firmware call instruction is fetched and decoded, "1" is set in the FWM register 111 via the multiplexer MPX1. The branch destination address generation circuit 155 generates a branch destination address, that is, a head address of a TLB rewriting program. This address is supplied to the location counter 151 via multiplexers 157 and 159.
Is set to Thereafter, the machine language instructions of the TLB rewriting program are sequentially fetched.

Since "1" is set in the FWM register 111, the AND gate 117 is opened, and the register set 107 for the firmware mode can be selected. In this state, the TLB rewrite instruction is fetched,
When decoded, the instruction decoder 103 selects an appropriate register from the normal mode register set 105 and the firmware mode register set 107, controls the switching signal, and outputs the output data of the selected register to the multiplexer 113. 115 is selected.

The arithmetic unit control circuit 123 controls the arithmetic unit 121 based on the decoding result, and
The new data, that is, the address data for rewriting, is calculated by operating the two data set to 9.

The result storage control circuit 145 writes new address data to the register set and
9 is written to the entry to be rewritten. This gives T
The contents of LB 129 are rewritten.

Finally, when the return instruction to the normal mode is decoded, the FW is transmitted via the multiplexer MPX1.
“0” is set in the M register 111, and the branch destination address generation circuit 155 generates a branch destination address, and sets it in the location counter 151 via the multiplexers 157 and 159. Thereafter, the machine instructions in the normal mode are sequentially fetched and executed.

3.2 When executing a store instruction, a load instruction, or the like, a TLB mishit may occur at the stage of address conversion, and a synchronous interrupt may occur. In such a case, if the synchronous interrupt is prohibited, the process is performed on the wrong address.

Therefore, when executing an instruction requiring address conversion such as a store instruction or a load instruction in the firmware mode, for example, as shown in FIG. 7, an instruction for setting "1" in the enable register 171 is issued. Code in advance.

When the store instruction is decoded with "1" set in the enable register 171, the instruction decoder 103 sends an instruction to the operand address generation circuit 125 to generate an operand address. This operand address is set to T via the address register 127.
It is supplied to the LB 129. For example, the address of the TLB entry is addressed by the upper m bits of the generated operand address, and n is read from the entry.
The bit data and the lower n bits of the operand address are compared by the comparator 131, and if they match, a TLB hit occurs. In the case of a TLB hit, its physical address,
For example, the work memory 13 dedicated to the firmware mode
7 is stored.

On the other hand, if the comparison results from the comparator 131 do not match, a TLB miss occurs, and a synchronous interrupt signal is generated. As described above, since “1” is set in the enable register 171, the output of the OR gate 173 becomes “1”, the AND gate 175 opens, and the synchronous interrupt signal is accepted by the interrupt control circuit 167.

The interrupt control circuit 167 generates a jump destination address (the head address of the TLB miss hit interrupt processing) and sets the jump destination address in the location counter 151 via the multiplexer 159. After that, TLB
The instructions of the mishit interrupt processing are sequentially executed, and the contents of the TLB 129 are replaced based on the data stored in the physical address cache memory 135. Then TL
B129 is re-accessed, the logical address is converted to a physical address, and the data is stored at that address location.

3.3 In the normal mode, when an instruction whose use is prohibited is decoded, the instruction decoder 10
3 generates a synchronous interrupt (program error) and cannot execute this instruction. However, if this type of instruction is executed in the firmware mode and in a state in which the synchronous interrupt is disabled (the enable register 171 is reset), the program error signal itself is generated, but the interrupt signal is generated by the AND gate 175. Blocking is also performed in the execution stage E and the result storage stage W. Therefore, even a machine language instruction or a combination of machine language instructions that cannot be executed in the normal mode can be forcibly executed in the firmware mode, and the hardware can be checked.

As described above, according to this embodiment,
By introducing a super-privileged mode called firmware mode, it is easy to port programs for CISC computers, and instructions for directly controlling hardware are hidden in firmware mode and released only to users of a certain level or higher. Furthermore, it is possible to forcibly execute an instruction or a combination of instructions that is not permitted in the normal mode, ignoring a hardware error trap or the like.

(Second Embodiment) Next, an arithmetic and control system according to a second embodiment of the present invention will be described with reference to FIG. The arithmetic and control system according to this embodiment includes an LSI and an SRAM.
And other disk cleat parts.

The arithmetic and control system shown in FIG.
And a processor 212 are connected via a control bus 213, an address bus 214, and a data bus 215.

The processor 212 has a basic operation control circuit 2
21, address conversion control circuit 222, first and second TL
B223, 224, cache control circuit 225, user instruction bus 226, operand data bus 227, firmware ROM 229, work memory 230, operand cache memory 231, instruction cache memory 23
2 is provided.

The basic operation control circuit 221 has a pipeline therein and performs a pipeline process such as fetching, decoding, executing, and storing a result of an instruction, and is realized by, for example, a one-chip LSI. Cache memory 231 and 232
Have independent configurations for operands and instructions, and are composed of discrete SRAMs. Operand cache memory 231 stores operands, and instruction cache memory 232 stores instructions. Each of the operand cache memory 231 and the instruction cache memory 232 is a physical address cache that caches the state of the main storage 211 as it is. Cache memory 23
The control of 1 and 232 is performed by the cache control circuit 225.

An address conversion unit for performing a conversion process from a logical address to a physical address is provided by an address conversion control circuit 22.
2 and the first and second TLBs 223 and 224. The address conversion circuit 222 is formed of a one-chip LSI, and the first and second TLBs 223 and 224 are formed of discrete SRAMs. First and second TLB 22
Nos. 3 and 224 are provided with two sets of large-scale translation tables, and up to two address translations (for example, address translation for parallel execution of load and store instructions or parallel execution of load and branch instructions). ) Can be processed simultaneously under the control of the address conversion control circuit 222.

The arithmetic system of this embodiment also supports the super-privileged mode, that is, the firmware mode, as in the first embodiment. The work memory 230 is a dedicated memory for the firmware mode for storing hardware diagnostic information and system information. Further, for example, even collect diagnostic information when the main memory 211 can not be accessed by a failure or the like of the interface with the power-on or system bus, so that it can set the processor 212 in a stopped state, important farm c Air on processor 212 And the remaining part of the firmware is stored in the main memory 211.

Next, the operation of the arithmetic and control system shown in FIG. 8 will be described. First, in the normal state, the cache control circuit 225 addresses the main memory 211 via the address bus 214. The main memory 211 supplies the machine language instruction at the address position to the basic operation control circuit 221 via the data bus 215. The basic operation control circuit 221 stores the supplied machine language instruction in the instruction cache memory 232 via the user instruction bus 226.

The basic operation control circuit 221 is connected to the data bus 2
15, or instructions stored in the instruction cache memory 232 are sequentially read, decoded, and executed.

For example, if the instruction is a simple operation instruction,
The basic operation control circuit 221 performs the operation, and holds the operation result in an internal register set. When the decoded instruction is a store instruction, the basic operation control circuit 221 outputs a request address (logical) 1 or 2 including an instruction, a logical address, a control signal, and the like to the address conversion control circuit 222.
The address conversion control circuit 222 is provided with the TLB 223 or 22
4 to generate a physical address. The cache control circuit 225 receives the generated logical address and specifies a write position. For example, the write target is the main memory 2
In the case of 11, the cache control circuit 225 stores a control signal such as a write address and a write enable signal in the main memory 21.
Feed to 1. The write data is stored in the basic operation control circuit 22.
1 to the main memory 211 via the data bus 215. The write target is the operand cache memory 23
In the case of 1, the cache control circuit 225 supplies a control signal such as a write address and a write enable signal to the operand cache memory 231. The write data is transferred from the basic operation control circuit 221 to the operand data bus 227.
Is supplied to the operand cache memory 231. When the write target is the work memory 230 (occurs only in the firmware mode), the cache control circuit 225 supplies a control signal such as a write address and a write enable signal to the work memory 230. The write data is supplied from the basic operation control circuit 221 to the work memory 230 via the operand data bus 227.

If the decoded instruction is a load instruction, data is read from the location addressed by the cache control circuit 225. On the other hand, if the decoded instruction is a firmware call instruction, the basic operation control circuit 221
Set firmware mode and disable asynchronous and synchronous interrupts. The basic operation control circuit 221 outputs a request address 1 or 2 including an instruction, a logical address, a control signal, and the like to the address conversion control circuit 222.
The address conversion control circuit 222 generates a branch destination address, that is, a top physical address of an area in which a firmware program to be accessed is stored. The cache control circuit 225 addresses the memory to be accessed (the main memory 211 or the firmware ROM 229) and supplies a read control signal based on the generated physical address. Thereafter, the cache control circuit 225 updates the address and sequentially reads out the machine language instructions in the firmware mode.

For example, when the firmware to be read is stored in the main memory 211, the cache control circuit 225 reads the read address and the read enable signal,
Control signals such as RAS and CAS are supplied to the main memory 211. The instruction in the firmware mode is supplied to the basic operation control circuit 221 via the data bus 215. Also, the firmware to be read is firmware ROM2.
29, the cache control circuit 225
Supplies control signals such as a read address and a read enable signal to the firmware ROM 229. The instruction in the firmware mode is supplied to the basic operation control circuit 221 via the user instruction bus 226.

In this state, the basic operation control circuit 221
Execute the firmware mode instruction. When the decoded instruction is a return instruction to the normal mode, the basic operation control circuit 221 sets the normal mode and enables the asynchronous interrupt and the synchronous interrupt. Further, the basic operation control circuit 221 outputs the request address 1 or 2 to the address conversion control circuit 222, and the address conversion control circuit 222 generates a branch destination physical address. The cache control circuit 225 determines, based on the generated physical address,
Addressing a memory to be accessed and supplying a read control signal and the like. Thereafter, the instructions in the normal mode are sequentially read out and executed under the control of the basic operation control circuit 221.

(Regarding the Firmware Space) In the second embodiment, the firmware (the program for the firmware mode) is stored in the main memory 211 and the firmware ROM.
229. Therefore, one of the programs is selectively read according to the processor status or the address of the instruction in the firmware. Switching the read position of the program to be executed can be regarded as switching the address space. The address space for the firmware is referred to as a firmware space, and an example of the configuration will be described below.

1. FIG. 9 shows the areas constituting the firmware space. Each area in FIG. 9 will be described below.

1.1 Firmware ROM Area (Instruction ROM Area) An area starting from the first address 0 in the firmware space, and is an area in which codes such as initialization of a processor are stored. This area is constituted by a ROM. The ROM is desirably provided on a processor like the firmware ROM 229 in FIG. In a multiprocessor system, it is effective to have a ROM on each processor in order to increase the independence of each processor.

1.2 Firmware Communication Area This is an area mainly used for communication between processors.
C writing only are permitted by air. In the case of a multiprocessor system, writing by a plurality of processors is permitted. In this example, firmware communication region is placed so as to follow the firmware ROM area.

1.3 Firmware Program Area This is an area for storing firmware code of each processor. It can also be used as a local data storage area for firmware of each processor. If the firmware code is common to a plurality of processors, this area may be used as a shared area for a plurality of processors. However, in this case, the local data storage area must be separated from the common part, and each processor must have its own.

In this example, the firmware program area is defined after address 4M in the firmware space. 2. 2.1 Relationship between Mapping of Logical Space and Physical Space 2.1 FIG. 10 shows the relationship of mapping between the logical space and the physical space in a multiprocessor system having n + 1 processors.

The firmware ROM area and the firmware communication area linearly mapped in the firmware space are mapped to the same area (address) in the physical space. That is, the firmware ROM area and the firmware communication area use the same address in the physical space. For example, the address translation mechanism and the cache control circuit 225 of each processor access the firmware ROM area when accessing the area as an instruction address, and access the firmware communication area when accessing the area as an operand address. Perform control.

2.2 The firmware program areas are arranged such that an area in the logical space and an area in the physical space have a one-to-one relationship for each processor. This mapping is performed by the address conversion control circuit 222 in each processor.
And TLB 223, 224. It is also possible to make the definition of the area in the physical space variable, to share one area by a plurality of processors, or to map so as to avoid a faulty area of the main memory.

3. Address conversion in firmware space 3.1 Registers used Address conversion processing is performed under the control of the address conversion control circuit 222. In the firmware space, correspondence information for converting a logical address into a physical address is stored in a register in the address conversion control circuit 222. FIG. 11 shows the names, significant bit widths, meanings, and the like of each register.

3.2 Setting of Size of Firmware ROM Area and Firmware Communication Area The sizes of the firmware ROM area and the firmware communication area are determined by the set value of the register FCSZ. Each region has a boundary of an integral multiple of the region size (the size is 12
If it is 8 Kbytes, it is located at an address which is an integral multiple of 128 Kbytes. This is for simplifying the address translation process.
The sizes of the firmware ROM area and the firmware communication area are either 128 Kbytes or 256 Kbytes. Set value of register FCSZ and firmware R
FIG. 1 shows the relationship between the start address (logical), end address (logical), and size of the OM area and the firmware communication area.
It is shown in FIG.

3.3 Setting of Size of Firmware Program Area As shown in FIG. 13, the firmware program area has its start address, end address, and area according to the set value (not a continuous value) of the register FRSZ. The size is determined and can take six values. Each firmware program area is arranged at a boundary of an integral multiple of the area size (if the size is 128 Kbytes, the address is an integral multiple of 128 Kbytes). This is for simplifying the address translation process.

3.4 Address Conversion Method for Firmware ROM Area and Firmware Communication Area FIG. 14 shows address conversion logic for the firmware ROM area and the firmware communication area. As shown in FIG. 14, when the value held in the register FCSZ is “0”, the first to fourteenth bits of the register FCTP are replaced with the first to fourteenth bits of the logical address in the firmware space, thereby obtaining the physical address. Is obtained. When the value held in the register FCSZ is “1”,
By replacing the first to thirteenth bits of the TP with the first to thirteenth bits of the logical address in the firmware space, a physical address is obtained.

3.5 Address Conversion Method for Firmware Program Area FIG. 15 shows a logic for converting a logical address to a physical address in the firmware program area. As shown in FIG. 15, the physical address is replaced by replacing the bit whose value is “0” among the first to ninth bits of the firmware logical address and the tenth to fourteenth bits of the register FRSZ with the value held in the register FRTP. Is obtained.

4. Protection of Firmware Area in Main Storage 211 To improve the reliability of the system, it is desirable to protect the firmware stored in the main storage 211 from being destroyed by a program runaway or erroneous processing. This protection mechanism checks whether the target address at the time of the writing process to the main memory 211 is an area where firmware is stored, and if it is an area where firmware is stored, generates a trap ( Writing process is prohibited).

For checking access to the firmware area, for example, the following items can be considered. 4.1 Checking Access to Firmware Space (Logical Address) Access to an unmounted area (between the communication area and the program area) in the firmware space and access beyond the last address of the program area are detected. . This is executed by the basic operation control circuit 221 inside the processor based on the logical address.

4.2 Checking Access to Firmware Communication Area and Firmware Program Area The firmware communication area is common to a plurality of processors, but the firmware program area can be individually defined. Therefore, when checking access to these areas inside the processor, each processor needs to know the range of the firmware program area of another processor.

As shown in FIG. 16, when the plurality of processors P and the main memory MEM are connected via the system control unit, the system control unit accesses the firmware communication area and the firmware program area. Can be checked together. However, it is necessary to notify the type of access from each processor to the system control unit. In addition, because the detection timing is delayed, countermeasures for illegal detection (access trap processing)
It is necessary to detect this kind of access quickly within the processor in order to cause the error to occur quickly.

4.3 Checking Access to Firmware Area on Main Memory For a request that refers to the main memory, it is determined whether or not access is permitted according to the area to be accessed.
For example, the classification shown in FIG. 17 can be considered.

As shown in FIG. 17A, for example, in the case of a request to access the main memory for fetching an instruction, and when the jump destination is a normal area, the physical address of the branch destination after address conversion is the firmware. It is determined whether or not the area is an area. If the area is a firmware area of any of the processors, access is prohibited. Further, when the jump destination is a firmware area, it is determined whether or not the physical address of the branch destination after address conversion is the firmware area of the own processor, and access is permitted only in the case of the firmware area of the own processor. You.

As shown in FIG. 17B, in the case of a request to access the main memory for accessing an operand, if the access target area is a normal area, the actual physical address after address conversion is the firmware. It is determined whether or not the area is an area. If the area is a firmware area of any of the processors, access is prohibited. If the access target area is a firmware area, it is determined whether or not the actual physical address after the address conversion is the firmware area of the own processor. Is allowed. If the access target area is the entire area, no check is performed, and access to all areas is permitted.

The access is checked by comparing the type of the request and the target address with the setting information of the firmware area. FIG. 17 shows the relationship between the type of request and the area check in the firmware mode, and all references to the firmware area in the normal mode are prohibited as illegal (error).

4.4 Check of Access from DMA Bus to Main Memory With the configuration shown in FIG. 16, it is also possible for the system control unit to check access from the DMA bus to main memory MEM. This check may be performed by a device that performs DMA.

When the access check is performed by the system control unit, the firmware area setting information of all the processors P is held in the system control unit, and the address requested by the access request from the DMA bus and the firmware area setting information are stored. Are compared, and an area check is performed.

From the viewpoint of reliability, it is desirable to prohibit any access from the DMA bus to the firmware area of the main memory MEM. Therefore, for example, when loading the firmware placed on the main memory MEM at system startup from an external storage device such as a disk, first, the firmware is DMA-transferred to the normal area of the main memory MEM, and then Then, the firmware in the firmware ROM may transfer the firmware transferred to the normal area on the main memory MEM to the firmware area.

The above is an example of the configuration of the firmware space. (Interrupt disabled mode in which only asynchronous interrupts are disabled) In addition to the firmware mode, an interrupt disabled mode in which only asynchronous interrupts are disabled may be considered.
This is a mode released to the user, and executes an instruction sequence usable in the normal mode in a state where external interrupts are disabled. Non-interruptible processing realized by the microprogram in the CISC type processor, for example, inseparable processing such as a queue operation instruction, can be realized using this mode.

For example, as shown in FIG. 18, before executing the indivisible processing (normal mode), an instruction for prohibiting the asynchronous interrupt is executed to set the interrupt prohibition mode. In the interrupt prohibition mode, a plurality of RISC-type instructions for realizing the same function as the CISC-type high-performance instruction are executed, and after the execution is completed, an external interrupt enable instruction is executed to enable the external interrupt.

Not only inseparable, but also interrupt processing required from the operating system to be realized by hardware and processing directly related to hardware, for example, multiprocessor control instructions, input / output instructions, initialization , Interrupt processing, etc. may be processed in the firmware mode. It is also possible to provide both of these modes and select the realization mode according to the content of the processing. In this case, for example, when the decoding unit decodes the firmware call instruction or the external interrupt prohibition instruction, mode data is set in a predetermined register and the mode is switched. Note that the present invention is not limited to the above embodiment, and various modifications are possible.

[0108]

As described above, in the present invention, a super-privileged mode, which is a firmware mode, is introduced into RISC type hardware, and processing conventionally constituted by a microprogram is realized as a normal machine language instruction. It is possible. This makes it easy to port the operating system developed for the CISC type processor to the RISC type processor, and hides the machine language instructions directly related to the hardware in the firmware mode, thereby improving the reliability of the system. And the portability of software such as an operating system is improved.

[Brief description of the drawings]

FIG. 1 shows a first embodiment of a pipeline control method according to the present invention.
The figure which shows an example.

FIG. 2 shows a second embodiment of the pipeline control method according to the present invention.
The figure which shows an example.

FIG. 3 is a flowchart showing a procedure for switching between a normal mode and a firmware mode.

FIG. 4 is a diagram showing a configuration of an arithmetic and control unit according to the first embodiment of the present invention in combination with FIG. 5;

FIG. 5 is a diagram showing a configuration of an arithmetic and control unit according to the first embodiment of the present invention in combination with FIG. 4;

FIG. 6 is a view showing a program storage state when a TLB rewriting program is stored in a firmware storage area.

FIG. 7 is a view showing a program storage state when a store instruction is stored in a firmware storage area.

FIG. 8 is a diagram showing a configuration of an arithmetic and control system according to a second embodiment of the present invention.

FIG. 9 is a diagram showing an area constituting a firmware space.

FIG. 10 is a diagram showing a relationship between mapping between a firmware space and a physical space.

FIG. 11 shows names of registers used to convert a logical address to a physical address in a firmware space;
The figure for demonstrating bit width and the meaning.

FIG. 12 is a diagram showing a relationship between a set value of a register FCSZ and a start address, an end address, and a size of a firmware ROM area and a firmware communication area.

FIG. 13 is a view showing a relationship between a set value of a register FRSZ, a start address, an end address, and an area size of a firmware program area.

FIG. 14 is a diagram showing address conversion logic of a firmware ROM area and a firmware communication area.

FIG. 15 is a diagram showing a logic for converting a logical address of a firmware program area into a physical address.

FIG. 16 is a block diagram showing a configuration in which a plurality of processors P and a plurality of main memories MEM are connected via a system control unit.

FIG. 17 is a diagram showing a relationship between a request and an area check for a request that refers to main storage.

FIG. 18 is a flowchart for explaining an external interrupt inhibition mode.

FIG. 19 is a diagram showing a relationship between a machine language instruction and a microprogram.

[Description of Signs] 11: Main memory, 12: Processor, 101: Instruction register, 103: Instruction decoder, 105: Register file, 107: Register file dedicated to firmware mode, 109: Control register, 111: FWM register,
113, 115: multiplexer, 117: AND gate, 119: data register, 121: arithmetic unit, 123
.. .Operation unit control circuit, 125 .operand address generation circuit, 127 .address register, 129 .TLB (Tran)
slation Lookaside Buffer), 131 ... Comparator, 133
... TLB hit register, 135 ... Physical cache memory, 137 ... Work memory dedicated to firmware mode, 139 ... Read data register, 141 ... Register, 143 ... Operation result register, 145 ... Result storage control circuit, 151 ... Location counter, 153 ... Update circuit, 155 ... Branch destination address generation circuit, 157, 159
... Mux, 161 ... Inverter, 163, 16
5 AND gate, 167 interrupt control circuit, 171
... Enable register, 173 ... OR gate, 175 ...
AND gate, 211: main memory, 212: processor,
213: control bus, 214: address bus, 2
15 Data bus, 221 Basic operation control circuit, 222
... Address conversion control circuits, 223, 224 ... TLB, 2
25: cache control circuit, 226: user instruction bus,
227: Operand data bus, 229: Firmware ROM, 230: Work memory, 230: Operand cache memory, 232: Instruction cache memory.

Claims (3)

(57) [Claims] 1. A system having two operation modes, a normal mode and a firmware mode in which asynchronous interrupts are prohibited, wherein a program for a normal mode including a RISC type machine language instruction to be executed in the normal mode is stored. first storage means and, machine language of the second storage means and said first and second storage means for storing the firmware mode program consisting of a RISC machine instructions to be executed by the firmware mode Reading means for reading instructions; a dedicated register set dedicated to firmware mode; a shared register set shared for firmware mode and normal mode; and the dedicated register for reading the instructions of the firmware program read by the reading means. And the common register set, and execute the normal mode. Execution means for executing instructions of a load program using the shared register set. 2. A system having two operation modes, a normal mode and a firmware mode in which asynchronous interrupts are prohibited, comprising: a program for a normal mode including a RISC-type machine language instruction to be executed in the normal mode; Storage means for storing a command for switching to the firmware mode, a program for the firmware mode including a RISC-type machine language instruction to be executed in the firmware mode, and a command for returning to the normal mode; In the normal state, the instructions of the program for the normal mode stored in the storage means are sequentially read, and the instructions of the program for the firmware mode are sequentially read in response to the instruction to switch to the firmware mode, In response to the instruction to return to normal mode, Reading means for sequentially reading the instructions of the program for the firmware, executing the instructions read by the reading means, and prohibiting the asynchronous interrupt in response to the instruction to switch to the firmware mode. Means for enabling an asynchronous interrupt in response to an instruction to return to the mode. 3. A method for porting a CISC-type program to a RISC-type processor, wherein, among instructions constituting the CISI-type program, predetermined instructions which are controlled by a plurality of microprograms and which are to be integrally executed are described. A firmware mode in which asynchronous interrupts are prohibited, and a plurality of RISC-type instructions for realizing the same function as the predetermined instruction are executed in the firmware mode.
How to port to ISC type processor.