JP3101568B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a metal silicide film.

[0002]

2. Description of the Related Art In recent years, further reduction in design rules has been studied in order to achieve higher integration and higher speed of semiconductor devices. Today, trial production of 256 MDRAM and trial production of a CMOS transistor having a gate length of 0.1 μm have been announced. With the progress of miniaturization of such transistors, reduction of device size according to the scaling law,
It is expected that the operation will be speeded up accordingly.

However, although channel resistance can be reduced simply by miniaturizing the transistor, the parasitic resistance of the source / drain diffusion layer (source / drain region) and the resistance of the contact portion (contact resistance) are reduced. The resistance becomes equal to or larger than the resistance, which is an obstacle in increasing the operation speed. In addition, in order to increase the operation speed, it is necessary to reduce the resistance of the gate wiring (electrode).

Conventionally, a salicide (Self-alined silicide) method has been proposed as a method for simultaneously reducing the parasitic resistance of the source / drain region and the wiring resistance of the gate electrode (T. Yoshida., Et. al.:J. Electrochem
i. Soc., Vol. 137, No. 6, (1990) pp1914-1917). LDD (Lighside) using this salicide method (salicide structure)
A method for manufacturing a p-channel MOS transistor having a (tly doped drain) structure will be described with reference to schematic cross-sectional views of the device shown in FIGS.

Step 1 (see FIG. 7A): LOCOS (Loca
An element isolation region 72 is formed on an n-type single crystal silicon substrate 71 by using a lized oxidation of silicon (lOx) method. Next, a silicon oxide film is formed on the substrate 71 by using a thermal oxidation method. Then, CVD (chemical Vapor Depositio
Using n), a doped polysilicon film doped with boron is formed on the silicon oxide film. Then, the gate insulating film 73 and the gate electrode 74 are formed by patterning the doped polysilicon film and the silicon oxide film into desired shapes.

Step 2 (see FIG. 7B): Using the gate electrode 74 as a mask for ion implantation, boron ions (B ⁺ ) are implanted into the surface of the substrate 71 to form a self-aligned (self-aligned) low-concentration region 75. To form Step 3 (see FIG. 7C): A silicon oxide film is formed on the entire surface of the device formed in the above steps by using the CVD method. Next, the entire surface of the silicon oxide film is etched back, and a sidewall spacer 76 is formed on the side wall of the gate electrode 74. Subsequently, using the gate electrode 74 and the sidewall spacers 76 as an ion implantation mask, boron fluoride ions (BF ₂ ⁺ ) are implanted into the surface of the substrate 71 to form a high-concentration region 77 in a self-aligned manner.

As a result, an LD having a source / drain region 83 composed of a low concentration region 75 and a high concentration region 77 is provided.
The p-channel MOS transistor 84 having the D structure is completed. Step 4 (see FIG. 8A): A natural oxide film formed on the surface of the substrate 71 is removed by performing isotropic etching. Next, using a magnetron sputtering method, a titanium film 78 (thickness: 30 nm) is formed on the entire surface of the device formed in the above steps.

Step 5 (see FIG. 8B): A first heat treatment is performed at a treatment temperature of 600 to 700 ° C. by using a heat treatment method in an electric furnace or an RTA (Rapid Thermal Annealing) method. As a result, the titanium film 78 and the substrate 71, the titanium film 78
And a gate electrode 74, a titanium silicide (TiSi ₂ ) film 79 is formed in a self-aligned manner at a position where the contact is made. At the same time, boron in the low concentration region 75 and the high concentration region 77 is activated.

The processing time when the heat treatment in an electric furnace is used is about 30 minutes, and the processing time when the RTA method is used is about 30 seconds. At this time, the titanium silicide film 79 is not formed where the titanium film 78 and the sidewall spacer 76 are in contact. Next, a mixed solution of aqueous hydrogen peroxide, ammonia and water heated to about 60 ° C. (mixing ratio: H ₂ O ₂ : NH ₄ OH: H ₂ O = 1: 1:
The titanium film 78 that has not been silicided is removed by the wet etching method using 5), and only the titanium silicide film 79 is left.

Subsequently, a heat treatment method in an electric furnace or RTA
The second heat treatment is performed at a processing temperature of 750 to 900 ° C. by using the method. The time of the second heat treatment is the same as that of the first heat treatment. Step 6 (see FIG. 8C): An interlayer insulating film 80 is formed on the entire surface of the device formed in the above step. Next, a contact hole 81 that contacts the titanium silicide film 79 is formed in the interlayer insulating film 80 by anisotropic etching. Subsequently, the contact holes 81 are formed by sputtering.
The inside is filled with a metal material to form a metal wiring 82.

In the MOS transistor 84, since the titanium silicide film 79 is formed, the parasitic resistance of the source / drain region 83 and the wiring resistance of the gate electrode 74 are simultaneously reduced. Note that an n-channel MOS having an LDD structure
When forming a transistor, each region 75, 77 has n
Ion implantation of a type impurity (such as phosphorus or arsenic) may be performed.

[0012]

In the conventional example, in step 5, the non-silicidized titanium film 78 is removed and only the titanium silicide film 79 is left, but hydrogen peroxide, ammonia and water are used. Since the wet etching is performed using the mixed solution of (1) and (2), washing and drying operations are required, and there is a problem that time and labor are required for manufacturing.

Furthermore, the one used as the etching solution contains ammonia which is harmful to the human body, and its handling and processing method is difficult, and the cost required for the processing must be increased in view of safety. The present invention relates to a method for manufacturing a semiconductor device and solves such a problem.

[0014]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein an element formation region and an element isolation region are formed.
Titanium or titanium compound on the surface of a silicon substrate
Contacting the silicon surface by the heat treatment process
A step of silicidizing titanium or a titanium compound;
Unsilicided chips without using a etching mask
Reaction of sulfur hexafluoride and oxygen with tan or titanium compounds
Gas and the flow rate ratio (sulfur hexafluoride / oxygen) is 2
Etching using dry etching technology set to 5
Removing step.

In a second aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, the flow ratio (hexafluoride ion
(Ow / oxygen) is set to 3-4. The method of manufacturing a semiconductor device according to claim 3 is the method according to claim 1 or 2.
In the above, a field effect transistor having a gate electrode and source / drain regions is formed in the element formation region.

FIG. 6 shows the respective etching rates of titanium (Ti), titanium nitride (TiN) and titanium silicide (TiSi) when sulfur hexafluoride and oxygen are used as reactive gases during reactive ion etching. , While changing the amount of oxygen added. As described above, by using sulfur hexafluoride and oxygen as reaction gases, titanium and titanium nitride are etched earlier, and titanium silicide is etched later.

Therefore, without using an etching mask,
Since titanium is quickly removed and titanium silicide is not easily etched, only the silicide portion can be selectively left.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments embodying the present invention will be described with reference to the drawings. 1 to 5 sequentially show the manufacturing process of a p-channel MOS transistor having a salicide structure. Step A (see FIG. 1): An element isolation film 2 is formed on an n-type single crystal silicon substrate 1 by using a LOCOS method. Next, in the same manner as in the conventional example, the gate insulating film 3, the gate electrode 4,
Sidewall spacer 5 and source / drain region 6
Is formed.

Step B (see FIG. 2): A natural oxide film formed on the surface of the substrate 1 is removed by performing isotropic etching.
Next, using a magnetron sputtering method, a titanium film 7 (thickness: 30 n) is formed on the entire surface of the device formed in the above process.
m). Step C (see FIG. 3): heat treatment in an electric furnace or RTA
The first heat treatment is performed at a treatment temperature of 600 to 700 ° C. by using a method. As a result, the titanium film 7 and the substrate 1, the titanium film 7
C49 phase titanium silicide (TiSi ₂ ) film 8 is self-aligned at the position where
Is formed. At the same time, the source / drain region 6
The boron inside is activated.

The processing time when using the heat treatment method in an electric furnace is about 30 minutes, and the processing time when using the RTA method is about 30 seconds. At this time, the titanium silicide film 8 is not formed where the titanium film 7 is in contact with the element isolation film 2 and the sidewall spacer 76. Also, a thin unreacted titanium film 7 remains on the surface of the titanium silicide film 8.

Step D (see FIG. 4): The entire surface of the titanium film 7 is anisotropically etched using a reactive ion etching (RIE). At this time,
Gas used: sulfur hexafluoride (SF ₆ ) + oxygen (O ₂ ) (S
F ₆ : O ₂ = 10: 3), total flow rate of used gas: 130 scc
m, pressure: 200 mtorr, RF power: 30 W, temperature: 70 ° C.

By using a mixed gas of sulfur hexafluoride and oxygen as a reaction gas, the titanium film 7 is easily etched and the titanium silicide film 8 is hardly etched. Therefore, even if an etching mask is not used, the titanium film 7 is removed, and only the titanium silicide film 8 can be left. The flow ratio (SF ₆ / O ₂ ) between sulfur hexafluoride and oxygen is preferably in the range of 2 to 5, and most preferably in the range of 3 to 4. If it is smaller than the desired range, etching may not be performed well. If it is larger than this range, the etching rate of titanium silicide may be equal to that of titanium nitride or titanium, and the selectivity may be lost.

In the step C, when the heat treatment is performed by the RTA method, part or all of the non-silicided titanium film 7 is nitrided because the heat treatment is performed in a nitrogen atmosphere. At the same time, they are etched away. Step E (see FIG. 5): heat treatment in an electric furnace or RTA
The second heat treatment is performed at a treatment temperature of 800 to 900 ° C. by using a method. The time of the second heat treatment is the same as that of the first heat treatment. By this second heat treatment, the titanium silicide film 8 is transformed from the C49 phase to the C54 phase, and the gate electrode 4 on which the titanium silicide film 8 is formed,
The sheet resistance of each of the source / drain regions 6 having the titanium silicide film 8 formed on the surface is reduced to about 5Ω / □.

In the above embodiment, the salicide structure has been described as an example, but it is needless to say that the present invention can be simply applied to the step of silicidizing a metal film. Further, in the above embodiment, the example in which the titanium film is silicided is shown, but a titanium compound such as titanium nitride may be used instead of titanium, and other high melting point metals such as molybdenum, tungsten, and tantalum , Hafnium, zirconium, niobium, vanadium, rhenium, chromium, platinum, iridium, osmium, rhodium and the like, or compounds thereof.

[0025]

According to the present invention, in the process of forming a metal silicide film, a safe dry etching process can be used without requiring cleaning and drying operations as in the prior art. Manufacturing is simple and high throughput can be obtained.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment of the invention.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the embodiment of the present invention;

FIG. 4 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the embodiment embodying the present invention;

FIG. 5 is a cross-sectional view showing a manufacturing step of the semiconductor device in the embodiment embodying the present invention;

FIG. 6 is a diagram showing an etching rate curve of a titanium film, a titanium nitride film, and a titanium silicide film when an oxygen flow rate is changed.

FIG. 7 is a cross-sectional view sequentially showing a manufacturing process of a semiconductor device in a conventional example.

FIG. 8 is a cross-sectional view sequentially showing a manufacturing process of a semiconductor device in a conventional example.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 silicon substrate 2 element isolation film 4 gate electrode 6 source / drain region 7 titanium film (metal film) 8 titanium silicide film

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ identification code FI H01L 29/78 301S (58) Investigated field (Int.Cl. ⁷ , DB name) H01L 21/28-21/288 H01L 21 / 44-21/445 H01L 29/40-29/43 H01L 29/47 H01L 29/872 H01L 21/302 H01L 21/306 H01L 21/3065 H01L 21/461

Claims (3)

(57) [Claims] 1. A forming a titanium or a titanium compound on the surface of a silicon substrate and the element formation region and the element isolation region is formed by heat treatment, titanium or Chi in contact with the silicon surface
No silicidation without using an etching mask
Titanium or titanium compounds react with sulfur hexafluoride and oxygen
And the flow ratio (sulfur hexafluoride / oxygen) is 2
A step of removing the etching by using a dry etching technique set in any one of (1) to (5) . 2. The flow rate ratio (sulfur hexafluoride / oxygen)
2. The method according to claim 1, wherein the number is set to 3 to 4 . The method according to claim 3, wherein said element forming region, a method of manufacturing a semiconductor device according to claim 1 or 2 that was characterized by the field effect transistor is formed having a gate electrode and source and drain regions.