JP3100568B2 - Small area transmission gate cell - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout design technique for configuring an LSI,
Related to cells that are components of layout, especially CM
The present invention relates to a small area transmission gate cell which is related to pass transistor logic using an OS transmission gate and is effective in reducing the LSI chip area.

[0002]

2. Description of the Related Art First, as a conventional cell layout technique, a layout shape of a general CMOS gate cell will be described, and restrictions on cell layout design will be described. FIG. 65 is a layout diagram of a cell of the NAND gate, and FIG. 66 is a circuit diagram of the NAND gate corresponding to FIG. Two P-type MOS transistors 600,
601 and two N-type MOS transistors 602 and 603
And wiring for interconnecting them. Broken line 60
The inside of 4 is called a well, and a diffusion region for forming a P-type MOS transistor can be arranged inside a certain distance from a broken line. Where the diffusion region for forming the P-type MOS transistor can be arranged inside the well 604 depends on the LSI.
Determined by the constraints coming from the manufacturing process. On the other hand, a diffusion region for forming an N-type MOS transistor can be arranged outside a certain distance from the broken line. N-type MOS
The position where the diffusion region for transistor formation can be placed is also LS
I determined by constraints coming from the manufacturing process.

FIG. 67 shows only the diffusion region in the layout diagram of FIG. 65. The diffusion region 605 in the well is for forming a P-type MOS transistor, and the diffusion region 606 outside the well is for forming an N-type MOS transistor. In this example, the diffusion region 605 is arranged so as to occupy almost the entire area where the diffusion region for forming the P-type MOS transistor can be arranged, and occupies almost the entire area where the diffusion area for forming the N-type MOS transistor can be arranged. Is provided with a diffusion region 606.

FIG. 68 additionally shows gate polysilicon wirings 607 and 608 which are located above the diffusion region. MOS transistors 600 to 603 are formed at portions where diffusion regions 605 and 606 and gate polysilicon wirings 607 and 608 overlap. FIG. 69 shows FIG.
1 shows an aluminum first-layer wiring placed on a further upper layer of FIG. The diffusion region contact 609 connects the aluminum first layer wiring and the diffusion region (source or drain of the MOS transistor), and the polysilicon contact 610 is
The aluminum first layer wiring and the gate polysilicon wiring are connected.

In general, when designing the layout of a CMOS logic cell, the cell height (vertical length in FIG. 65) is fixed to a certain value, and the cell size is changed for each CMOS gate having a different function. Sometimes the cell width (Fig. 65
Normally, only the length in the left-right direction is changed. Also, the height of the well 604 and the position of the well 604 with respect to the upper and lower ends of the cell are usually determined. Therefore, even when laying out a cell of a selection switch using a CMOS transmission gate, which is a target of the present invention, it is necessary to design such that the cell height and the well position are the same as those of the CMOS gate to be mixed. .

Next, a conventional technique relating to the pass transistor logic will be described. A pass transistor logic, which is a type of logic circuit used for an LSI, constitutes a logic by using a MOS transistor as a selection switch of an input signal. Particularly, when an N-type MOS transistor is used as a selection switch, it is most widely used. CM doing
It is possible to realize logic of the same function with a smaller number of transistors than the OS logic, and it is attracting attention as a logic circuit which is excellent in chip area, power consumption, and operation speed. The features and examples of the circuit are described on pages 98 to 104 of “Technical White Paper for Low-Power LSI (Nikkei Microdevices, Nikkei BP)” (referred to as Document 1).

On page 104 of Document 1, by combining three types of cells using an N-type MOS transistor as a selection switch for an input signal, the area is 0.55 times that of the conventional CMOS logic and the delay time is 0. A case where the power consumption is reduced by 0.74 times and power consumption by 0.63 times is introduced. In addition, "1997 SYMPOSIUM ON VLSI
CIRCUITS, DIGEST OF TECH
NICAL PAPERS (Japan Society of Applied Physics / IEEE
E-Solid Circuit Subcommittee) (Ref. 2)
The page also introduces an example of using an N-type MOS transistor as an input signal selection switch.
The advantage over logic is shown.

However, when only an N-type MOS transistor is used as a selection switch for an input signal, it is known that the voltage amplitude at the output point of the selection switch is reduced. It has become. This will be described with reference to FIG. 63 while citing a part of the circuit shown in Reference 2.

The selection switch, which is the minimum unit when configuring the pass transistor logic, is composed of two N-type MOS transistors 500 and 501 and an inverter gate 502. When the value of the selection input signal E is low (assuming zero volts), the N-type MOS transistor 500 is in a conductive state,
The N-type MOS transistor 501 is turned off, and the value of the input signal G is guided to the output point 507 of the selection switch.
At this time, when the value of the input signal G is high (assuming that it is equal to the power supply voltage) and is 3 volts, the voltage at the output point 507 of the selection switch does not rise to 3 volts, and the N-type MOS
The value is lower than 3 volts by the threshold voltage of the transistor 500. This voltage value is 2 when the N-type MOS transistor 500 is manufactured by a normal manufacturing method.
Around the bolt. Thus, the output point 5 of the selection switch
07 is significantly lower than the power supply voltage.
Attempting to operate the circuit at a lower power supply voltage causes performance degradation such as a reduction in noise margin and an increase in delay.

Here, a supplementary explanation will be given on the method of configuring the pass transistor logic. In FIG. 63, two N-type MOS transistors 503, 5
04 and the inverter gate 505, and the N-type MOS transistor 503 is connected to the output point 50 of the first-stage selection switch.
7 to form a serial connection of selection switches.
Generally, in pass transistor logic, selection switches are connected in series in multiple stages to form logic. An output buffer inverter gate 506 is normally connected to the output point 508 of the last-stage selection switch to recover the reduction of the voltage amplitude and to enhance the driving capability of the output signal.

By the way, as described above, the pass transistor logic using only the N-type MOS transistor as the input signal selection switch is not suitable for operation at a low power supply voltage because performance problems are likely to occur. However, operating at a low power supply voltage has a remarkable effect on reducing the power consumption of an LSI. Therefore, it is an important issue to make pass transistor logic having various good properties usable at a low power supply voltage. One way to achieve this is to use an N-type MOS as an input signal selection switch.
Instead of using only transistors, a CMO comprising a pair of an N-type MOS transistor and a P-type MOS transistor
There is a method using an S transmission gate.

FIG. 64 shows a circuit functionally equivalent to that of FIG. 63, constructed using CMOS transmission gates. As an input signal selection switch, an N-type MOS transistor 5
00 instead of N-type MOS transistor 511 and P-type M
A CMOS transmission gate composed of an OS transistor 512 is used, and an N-type M transistor is used instead of the N-type MOS transistor 501.
OS transistor 513 and P-type MOS transistor 51
4 and a further inverter gate 515 is used. In FIG. 64, when the value of the selection input signal E is low (zero volt), the N-type M
OS transistor 511 and P-type MOS transistor 51
2 is conductive, N-type MOS transistor 513 and P-type M
The OS transistor 514 is turned off and the input signal G
Is guided to the output point 517 of the selection switch. At this time, if the value of the input signal G is high (equal to the power supply voltage) and is 3 volts, the voltage at the output point 517 of the selection switch rises to just 3 volts. The fact that the voltage has risen to just 3 volts without a voltage drop is due to the function of the P-type MOS transistor 512. As described above, by using the CMOS transmission gate for the selection switch, the voltage amplitude at the output point of the selection switch does not decrease.
For this reason, when operating at a low power supply voltage, reduction in noise margin and deterioration in delay are reduced, and pass transistor logic can be used at a low power supply voltage.

FIG. 70 shows an example in which one stage is taken out of the two-stage series connection of the selection switches shown in FIG. 64 and laid out according to the prior art. FIG. 1 shows a circuit diagram corresponding to FIG. FIG. 1 shows a minimum unit when a pass transistor logic is constituted by one stage of a selection switch, and is itself a two-input one-output selector using a CMOS transmission gate. FIG. 71 shows a diffusion region extracted from FIG. 70. CMO in FIG.
The S inverter gate 20 includes two CMOS transmission gates 21,
Reference numeral 22 is realized in the left half of the cell using diffusion regions 611 and 613. FIG. 72 shows the aluminum first layer wiring and contact in FIG. 70, and FIG. 73 shows the aluminum second layer wiring and via hole in FIG. 70. As described above, the two-input one-output selector using the CMOS transmission gate can be easily realized by the conventional technology.

[0014]

However, FIG.
There is a problem in the pass transistor logic using the CMOS transmission gate as shown in FIG. This is because the number of transistors is increased in the circuit configuration of FIG. 64 as compared with the circuit configuration using only N-type MOS transistors as selection switches as shown in FIG. Is to happen. The increase in the LSI chip area results in an increase in LSI manufacturing cost and a deterioration in power consumption and operation speed. Therefore, in the present invention, CM
By devising the LSI layout design while taking advantage of the circuit configuration characteristics of the two-input one-output selector using the OS transmission gate, the two-input one-input CMOS transmission gate can be used.
The output selector is realized as a small area cell. This suppresses an increase in LSI manufacturing costs and prevents deterioration of power consumption and operation speed. This solves or reduces the problem of increasing the LSI chip area when using a pass transistor logic using a CMOS transmission gate operable at a low power supply voltage. The present invention has been made to achieve this.

[0015]

Means for Solving the Problems A layout design for realizing a small-area cell while taking advantage of a circuit configuration characteristic of a two-input one-output selector using a CMOS transmission gate will be described. I paid attention. that is,
In the pass transistor logic, it is easy to obtain high performance even if a small size MOS transistor is used.
As an example, assuming a manufacturing process of 0.35 micrometers, a signal delay time when the circuit of FIG. 1 is realized using a transistor having a gate width of 4.2 micrometers and a gate width of 1 Signal delay time when the same circuit is realized using a transistor of .4 micrometers (when all load is taken from inverter gate with gate width of 2.8 micrometers and wiring load is considered)
Comparing with the simulation, the signal delay time of the latter is only 8% larger than that of the former, whereas the power consumption of the latter is 56% smaller than the former. This value translates into an energy delay product, which is a performance index of a logic circuit, meaning that it has been improved by 50%, and the pass transistor logic indicates that good performance can be easily obtained using a small transistor. .

Accordingly, a CMOS transmission gate is formed by using small-sized MOS transistors, and an inverter gate for driving the gate input of the CMOS transmission gate is also formed by small MOS transistors. To a smaller area. However, cells serving as components of the LSI are limited in shape, and reducing the size of the MOS transistor does not necessarily reduce the area of the cell. Here, a layout design must be devised. .

Next, means for solving the problem will be described. The means corresponding to claims 1 to 4 is for realizing a cell including a 2-input / 1-output selector using a CMOS transmission gate with a small area.

First, means corresponding to claim 1 will be described. Well 1 for forming P-type MOS transistor
6, the first diffusion region 11 and the second diffusion region 12 are provided, and the second diffusion region 12 is located below the first diffusion region 11 when the well 16 is disposed on the layout drawing. Arrange to come. Next, a third diffusion region 13 and a fourth diffusion region 14 are provided outside the well 16 and below the well 16 on the layout drawing.
In addition, the fourth diffusion region 14 is arranged below the third diffusion region 13 on the layout drawing.

Next, a P-type MOS is formed on the first diffusion region 11.
The transistor 1 is provided, P-type MOS transistors 3 and 5 adjacent to each other are provided on the second diffusion region 12, and N-type MOS transistors 4 and 6 adjacent to each other are provided on the third diffusion region 13. N-type MOS transistor 2 is provided on diffusion region 14. At this time, the structure is such that the four MOS transistors 1, 2, 3, and 6 share one gate polysilicon wiring 15.

Further, a P-type MOS transistor 1 and an N-type M
CMOS inverter gate 2 by OS transistor 2
0, the first CMOS transmission gate 21 is constituted by the P-type MOS transistor 3 and the N-type MOS transistor 4, and the second CMOS transmission gate 22 is constituted by the P-type MOS transistor 5 and the N-type MOS transistor 6. ,
And a CMOS inverter gate 20, a first CMOS transmission gate 21, and a second CMOS transmission gate 22
Construct an input 1 output selector.

A description will be given of how the above-mentioned problem is solved by this means. First, in the pass transistor logic, the area and shape of the diffusion region were changed to reduce the cell area by taking advantage of the characteristic that good performance was easily obtained even when a small transistor was used. FIG. 71 shows only the diffusion region extracted from the layout example of the conventional two-input one-output selector shown in FIG. In FIG. 71, the diffusion regions 612 and 611 juxtaposed in the horizontal direction in the drawing are changed to have a smaller area in the present means and are juxtaposed in the vertical direction in the drawing. That is, the diffusion regions 11 and 12 for P-type MOS transistors are juxtaposed in the vertical direction. The same applies to the diffusion regions 614 and 613 juxtaposed in the horizontal direction in FIG.
The diffusion regions 13 and 14 for type MOS transistors are juxtaposed in the vertical direction. As a result, the same number of transistors can be formed without changing the cell height (vertical length) and making the cell width (left / right length) smaller than in the conventional method. Furthermore, paying attention to the fact that the wiring in the cell requires an area in the layout, and adopting a structure in which four transistors share one gate polysilicon wiring, the gate wiring length is shortened and the aluminum wiring is reduced. Was. Such a structure takes advantage of the circuit characteristics of a two-input one-output selector using a CMOS transmission gate.
In addition to the MOS transistors 1 and 2 constituting the S inverter gate 20, the four M transistors of the P-type MOS transistor 3 in the first CMOS transmission gate 21 and the N-type MOS transistor 6 in the second CMOS transmission gate 22
This utilizes the necessity of mutual gate connection between OS transistors. As described above, the two-input one-output selector using the CMOS transmission gate is realized as a small-area cell, and the problem of an increase in cell area due to an increase in the number of transistors is reduced.

Next, means corresponding to "claim 2" will be described. The means corresponding to "claim 2" is different from the means corresponding to "claim 1" only in the following points. First, the transistor formed on the first diffusion region 11 is limited to only the P-type MOS transistor 1, and the second diffusion region 1
2 are formed on adjacent P-type MOs.
Limited to S transistors 3 and 5, only third diffusion region 1
3 are formed on adjacent N-type transistors.
Limited to only S transistors 4 and 6, fourth diffusion region 1
4 is limited to the N-type MOS transistor 2 only. These six MOS transistors are the minimum required to constitute a two-input one-output selector. Further, a connection for forming the CMOS inverter gate 20 is provided between the MOS transistors 1 and 2, a connection for forming the first CMOS transmission gate 21 is provided between the MOS transistors 3 and 4, and the MOS transistors 5 and 5 are provided. 6, a connection for configuring the second CMOS transmission gate 22 is provided.
The connection between the output of the OS inverter gate 20 and the gate input of the MOS transistors 4 and 5 is provided. By specifying these connections, the CMOS inverter gate 20, the first CMOS transmission gate 21, and the second CMOS transmission gate 21 are connected. All of the connections for configuring a two-input one-output selector using the CMOS transmission gate 22 of FIG.

Next, means corresponding to claim 3 will be described. The means corresponding to "claim 3" is different from the means corresponding to "claim 1" only in the following points. That is, one more P-type MOS transistor 7 is provided on the second diffusion region, one more N-type MOS transistor 8 is provided on the third diffusion region, and the second CMOS transistor 7 The inverter gate 23 is formed, and the output of the second CMOS inverter gate 23 is connected to one input of a two-input one-output selector, so that one input of the two-input one-output selector is inverted. . By this means, one of the inputs of the two-input / one-output selector is inverted to improve the function while solving the above-mentioned problem in the same manner as the means corresponding to "claim 1".

Next, means corresponding to claim 4 will be described. The means corresponding to "claim 4" is different from the means corresponding to "claim 1" only in the following points. That is, one more P-type MOS transistor 9 is provided on the first diffusion region, and one more N-type MOS transistor 10 is provided on the fourth diffusion region. By forming the inverter gate 24 and providing a connection between the output of the two-input one-output selector and the gate input of the CMOS inverter gate for output buffer, a two-input one-output selector with a CMOS inverter gate for output buffer was configured. Things.
According to this means, the function is enhanced by adding a CMOS inverter gate for output buffer to the two-input one-output selector while solving the above-mentioned problem in the same manner as the means corresponding to "claim 1". The output buffer CMOS inverter gate 24
Are arranged in the first diffusion region 11 and the fourth diffusion region 14 having a small number of transistors, the cell area is prevented from increasing with the increase in the number of transistors.

Next, means corresponding to "claim 6" will be described. A total of two or more cells corresponding to any of the small-area transmission gate cells described in "Claims 1 to 4" are prepared, and they are arranged in a line so that there is no gap between adjacent cells. Apply wiring. As a result, a cell having a higher function is configured using a cell corresponding to any of the small area transmission gate cells described in claims 1 to 4 as a constituent element. This means utilizes a feature relating to the configuration of the pass transistor logic. In the design of the pass transistor logic, in addition to treating the two-input one-output selector as the minimum unit of the logic design, a combination of the two-input one-output selector is used. It is often treated as a more sophisticated logical design unit.

Next, means corresponding to claim 7 will be described. A total of one or more cells and one or more CMOS gate cells corresponding to any of the small-area transmission gate cells described in “Claims 1 to 4” are prepared, and they are arranged in a row so that there is no gap between adjacent cells. Wiring required between cells is provided.
As a result, a cell having a higher function can be constituted by adding a CMOS gate cell with a cell corresponding to any of the small area transmission gate cells described in claims 1 to 4 as a constituent element.

[0027]

Embodiments of the present invention will be described below. FIG. 4 shows an embodiment corresponding to "claim 1".
8 to FIG. 4 to 8 are layout drawings of the cell, FIG. 4 shows only the well and the diffusion region, FIG. 5 shows the gate polysilicon wiring in addition to FIG. 4, and FIG. 6 shows the entire layout diagram of the cell. 7 shows only the aluminum first layer wiring in FIG. 6, and FIG. 8 also shows only the aluminum second layer wiring.

First, a description will be given with reference to FIG. P-type MO
A first diffusion region 11 and a second diffusion region 12 are provided inside a well 16 for forming an S transistor. At this time, the second diffusion region 12 is arranged below the first diffusion region 11 when the well 16 is arranged on the layout drawing. Next, a third diffusion region 13 and a fourth diffusion region 14 are provided outside the well 16 and below the well 16 on the layout drawing. At this time, the fourth diffusion region 14 is arranged below the third diffusion region 13 on the layout drawing.

Next, a description will be given with reference to FIG. The P-type MOS transistor 1 is provided on the first diffusion region 11, the P-type MOS transistors 3 and 5 adjacent to each other are provided on the second diffusion region 12, and the N-type MOS transistors MOS transistors 4 and 6 are provided, and N-type MOS transistor 2 is provided on fourth diffusion region 14. At this time, the four MOS transistors 1, 2, 3, 6 are 1
The structure is such that the gate polysilicon wiring 15 is shared.

The two-input / one-output selector shown in FIG. 1 is constituted by the MOS transistors provided as described above. A CMOS inverter gate 20 is constituted by the P-type MOS transistor 1 and the N-type MOS transistor 2,
A first CMOS transmission gate 21 is constituted by the P-type MOS transistor 3 and the N-type MOS transistor 4,
A second CMOS transmission gate 22 is constituted by the S transistor 5 and the N-type MOS transistor 6, and a two-input one-output selector is constituted by the CMOS inverter gate 20, the first CMOS transmission gate 21, and the second CMOS transmission gate 22. I do.

In order to form the two-input one-output selector as described above, it is necessary to connect the MOS transistors to each other. For example, the gate polysilicon wiring shown in FIG. 5 and the aluminum first layer shown in FIG. The interconnection between the MOS transistors can be realized by using the wiring and the aluminum second layer wiring shown in FIG. FIG. 6 shows a layout diagram of the entire cell after aluminum wiring is performed. In the diffusion regions 11, 12, 13, and 14, both left and right ends of the region are drawn in a waveform. In addition to the MOS transistors 1 to 6 shown in FIG. , Expresses that it can be used to create more sophisticated cells.

Next, an embodiment corresponding to "claim 2" will be described with reference to FIGS. 9 to 12 are layout drawings of a cell, FIG. 9 shows a well, a diffusion region, and a gate polysilicon wiring, FIG. 10 shows the entire layout of the cell, and FIG. 11 shows the aluminum first layer wiring in FIG. FIG. 12 also shows only the aluminum second layer wiring.

First, a description will be given with reference to FIG. P-type MO
A first diffusion region 11 and a second diffusion region 12 are provided inside a well 16 for forming an S transistor. At this time, the second diffusion region 12 is arranged below the first diffusion region 11 when the well 16 is arranged on the layout drawing. Next, a third diffusion region 13 and a fourth diffusion region 14 are provided outside the well 16 and below the well 16 on the layout drawing. At this time, the fourth diffusion region 14 is arranged below the third diffusion region 13 on the layout drawing. Next, only one P-type MOS transistor 1 is provided on the first diffusion region 11, and only two P-type MOS transistors 1 are provided on the second diffusion region 12.
Type MOS transistors 3 and 5 and a third diffusion region 1
3, only two adjacent N-type MOS transistors 4, 6 are provided, and only one N-type M
An OS transistor 2 is provided. At this time, four MOS
The transistors 1, 2, 3, and 6 have a structure in which one gate polysilicon wiring 15 is shared.

The two-input / one-output selector shown in FIG. 1 is constituted by the MOS transistors provided as described above. A connection is provided to configure the CMOS inverter gate 20 using the P-type MOS transistor 1 and the N-type MOS transistor 2. For this purpose, a polysilicon wiring 15 can be used for the gate wiring, and an aluminum wiring can be used for the wiring of the source and drain portions. Next, a connection is provided to configure the first CMOS transmission gate 21 with the P-type MOS transistor 3 and the N-type MOS transistor 4.
Aluminum wiring can be used for this. Next, a connection is provided to form the second CMOS transmission gate 22 by the P-type MOS transistor 5 and the N-type MOS transistor 6. Aluminum wiring can also be used for this. Further, a connection is provided for connecting the output of the CMOS inverter gate 20 and the gate inputs of the MOS transistors 4 and 5. This can be realized by using both the gate polysilicon wiring and the aluminum wiring. Thus, a two-input one-output selector including the CMOS inverter gate 20, the first CMOS transmission gate 21, and the second CMOS transmission gate 22 is obtained. FIG. 9 shows a specific example of the gate polysilicon wiring, FIG. 11 shows a specific example of the aluminum first layer wiring, and FIG. 12 shows a specific example of the aluminum second layer wiring. FIG. 10 shows a layout diagram of the whole cell realized by these.

Next, an embodiment corresponding to claim 3 will be described with reference to FIGS. 13 to FIG.
6 is a layout drawing of the cell, FIG. 13 shows a well, a diffusion region, and a gate polysilicon wiring, FIG. 14 shows the entire layout of the cell, FIG. 15 shows only the aluminum first layer wiring in FIG. FIG. 16 also shows only the aluminum second layer wiring.

First, a description will be given with reference to FIG. P type M
A first diffusion region 11 and a second diffusion region 12 are provided inside a well 16 for forming an OS transistor. At this time, the second diffusion region 12 is arranged below the first diffusion region 11 when the well 16 is arranged on the layout drawing. Next, outside the well 16 and below the well 16 on the layout drawing,
A third diffusion region 13 and a fourth diffusion region 14 are provided. At this time, the fourth diffusion region 14 is arranged below the third diffusion region 13 on the layout drawing. Next, one P-type MOS transistor 1 is provided on the first diffusion region 11, and two adjacent P-type MOS transistors 3 and 5 and one P-type MOS transistor are further provided on the second diffusion region 12. A transistor 7 is provided, and two adjacent N-type MOS transistors 4 and 6 are further provided on the third diffusion region 13.
One N-type MOS transistor 8 is provided, and one N-type MOS transistor 2 is provided on the fourth diffusion region 14. At this time, the four MOS transistors 1, 2, 3, 6 are 1
The structure is such that the gate polysilicon wiring 15 is shared.

The MOS transistor provided as described above constitutes a two-input one-output selector in which one of the inputs is an inverted input, as exemplified in FIG. First, a CMOS inverter gate 20 is constituted by a P-type MOS transistor 1 and an N-type MOS transistor 2, and a P-type MOS transistor
A first CMOS transmission gate 21 is formed by the transistor 3 and the N-type MOS transistor 4, and a second CM is formed by the P-type MOS transistor 5 and the N-type MOS transistor 6.
An OS transmission gate 22, and a CMOS inverter gate 20, a first CMOS transmission gate 21, and a second C
The MOS transmission gate 22 forms a two-input one-output selector. Next, the second CMOS inverter gate 23 is constituted by the MOS transistors 7 and 8, and the output of the second CMOS inverter gate 23 is connected to one input of a two-input one-output selector. As described above, a two-input one-output selector in which one of the inputs is an inverted input is configured. However, the CMOS inverter gate is connected to the input C of FIG.
Is also possible.

As described above, in order to form a two-input one-output selector in which one of the inputs is inverted, it is necessary to connect the MOS transistors to each other. For example, the gate polysilicon wiring shown in FIG. The interconnection between the MOS transistors can be realized by using the aluminum first layer wiring shown in FIG. 15 and the aluminum second layer wiring shown in FIG. FIG. 14 shows a layout diagram of the whole cell after wiring. MOS transistors 7 and 8 are shown in FIG.
In the case of arranging in the position shown in FIG.
The connection between the output 3 and the CMOS transmission gate 21 constituting one input of the 2-input / 1-output selector is connected by a diffusion layer, so that it is not necessary to provide an aluminum wiring.

Next, an embodiment corresponding to claim 4 will be described with reference to FIGS. 17 to FIG.
9 is a layout drawing of the cell, FIG. 17 shows a well, a diffusion region, and a gate polysilicon wiring, FIG. 18 shows the whole layout of the cell, FIG. 19 shows only the aluminum first layer wiring in FIG. FIG. 20 also shows only the aluminum second layer wiring.

First, a description will be given with reference to FIG. P type M
A first diffusion region 11 and a second diffusion region 12 are provided inside a well 16 for forming an OS transistor. At this time, the second diffusion region 12 is arranged below the first diffusion region 11 when the well 16 is arranged on the layout drawing. Next, outside the well 16 and below the well 16 on the layout drawing,
A third diffusion region 13 and a fourth diffusion region 14 are provided. At this time, the fourth diffusion region 14 is arranged below the third diffusion region 13 on the layout drawing. Next, the P-type MOS transistor 1 and one more
P-type MOS transistors 9 are provided, two adjacent P-type MOS transistors 3 and 5 are provided on the second diffusion region 12, and two adjacent N-type MOS transistors are provided on the third diffusion region 13. MOS transistors 4 and 6 are provided, and an N-type MOS transistor 2 and one N-type MOS transistor 10 are provided on the fourth diffusion region 14. At this time,
The MOS transistors 1, 2, 3, and 6 have a structure in which one gate polysilicon wiring 15 is shared.

With the MOS transistor provided as described above, the output buffer CMOS as shown in FIG.
A two-input one-output selector with an inverter gate is constructed. First, a CMOS inverter gate 20 is constituted by the P-type MOS transistor 1 and the N-type MOS transistor 2, and a first CMOS transmission gate 21 is constituted by the P-type MOS transistor 3 and the N-type MOS transistor 4.
A second CMOS transmission gate 22 is constituted by the MOS transistor 5 and the N-type MOS transistor 6, and the CM
The OS inverter gate 20, the first CMOS transmission gate 21, and the second CMOS transmission gate 22 constitute a two-input one-output selector. Next, the CMOS inverter gate 2 for output buffer is provided by the MOS transistors 9 and 10.
4 and further, a connection is provided between the output of the two-input one-output selector and the gate input of the CMOS inverter gate 24 for output buffer, thereby forming a two-input one-output selector with a CMOS inverter gate for output buffer.

As described above, in order to form a two-input one-output selector with an output buffering CMOS inverter gate, interconnection between MOS transistors is required. For example, the gate polysilicon wiring shown in FIG. 1
The interconnection between the MOS transistors can be realized by using the aluminum first layer wiring shown in FIG. 9 and the aluminum second layer wiring shown in FIG. FIG. 18 shows a layout diagram of the entire cell after wiring has been performed.

Next, an embodiment corresponding to claim 6 will be described with reference to FIGS. FIG. 21 also shows a layout diagram of a plurality of cells. Each of the cells 40 to 44 is a small-area transmission gate cell corresponding to any one of claims 1 to 4. In the case of FIG. 21, the cell 40 corresponds to “Claim 4”, and the cell 41 to the cell 44
Are small area transmission gate cells corresponding to claim 2, but are examples in which the layout forms of the cells 41 to 44 are slightly different from each other. Next, these cells are arranged in a line so that there is no gap between adjacent cells. At this time, it is desirable to determine the arrangement order of the cells so that a desired logic function can be realized with the shortest possible wiring using these cells. FIG. 22 shows a case where the five cells shown in FIG. 21 are arranged in a line without any gap.
FIG. 24 shows a circuit that can be configured using these cells and can be used as a high-performance logic design unit in the logic design of pass transistor logic. This is a 2-input, 1-output selector arranged in a tree-like fashion and a CM for output buffering.
This is a circuit provided with an OS inverter gate. FIG. 23 shows a layout in which inter-cell wiring is added to the layout in FIG. 22 to realize the circuit in FIG. There are many types of circuits that can be used as high-performance logic design units in the design of pass transistor logic, and almost all of them can be realized by a combination of small-area transmission gate cells according to claims 1 to 4.

Next, an embodiment corresponding to claim 7 will be described with reference to FIGS. FIG. 25 also shows a layout diagram of a plurality of cells. Each of the cells 51 to 53 is a small area transmission gate cell corresponding to any one of claims 1 to 4, and the cell 50 is a CMO.
This is an S gate cell. In the example of FIG. 25, all of the cells 51 to 53 are small-area transmission gate cells according to claim 2, and the cell 50 is a CMOS inverter gate cell. Next, these cells are arranged in a line so that there is no gap between adjacent cells. At this time, it is desirable to determine the arrangement order of the cells so that a desired logic function can be realized with the shortest possible wiring using these cells. FIG.
In FIG. 27, the four cells shown in FIG. 25 are arranged in a line without any gap, and wiring is performed between the cells to realize the circuit of FIG. The circuit shown in FIG. 27 is one of circuits used as a high-performance logic design unit when designing a pass transistor logic. A 2-input / 1-output selector is arranged in a tree shape and an output buffer CMOS inverter gate is provided. It is a thing. An example in which a CMOS inverter gate cell 50 using a large transistor is used as an output buffering CMOS inverter gate to increase the output driving capability. By combining a small area transmission gate cell and a CMOS gate cell according to the first to fourth aspects, it is possible to realize many useful cells that can be used as a high-performance logic design unit.

The described first embodiment in the following.
A plurality of cells necessary for configuring a desired logic function are selected from the small-area transmission gate cells corresponding to "claims 1 to 4". For example, when there are cells 40 to 44 shown in FIG. 21 as the plurality of cells, they are arranged in a row as illustrated in FIG. At this time, the arrangement order of the plurality of cells is determined so that the inter-cell wiring required to configure a desired logic function is as short as possible. Next, inter-cell wiring required to configure a desired logic function is provided. FIG. 23 shows an example in which inter-cell wiring is applied to the arrangement result shown in FIG.
According to the above procedure, a new cell having a desired logic function is formed.

The described second embodiment to the next.
As a plurality of cells required to configure a desired logic function, one or more of small area transmission gate cells and one or more of CMOS gate cells corresponding to the first to fourth aspects are selected. After arranging the plurality of cells in a line, inter-cell wiring necessary to configure a desired logic function is provided. As an arrangement method, for example, when the cells 50 to 53 shown in FIG.
As shown in FIG. At this time, the arrangement order of the plurality of cells is determined so that the inter-cell wiring required to configure a desired logic function is as short as possible. FIG.
Is an example in which wiring between cells is completed. By the above procedure, configuring the new cell with the desired logic function
Can also.

Next, an embodiment corresponding to claim 8 will be described. A cell required to realize an LSI having a desired function is defined as a cell according to claim 1 and a CMO.
A cell is selected from both of the S cell libraries, and these cells are laid out in a standard cell system.
That is, the plurality of cells are arranged in a plurality of cell rows parallel to each other, and wiring between cells necessary for configuring a desired logic and power supply wiring to all cells are provided. The layout obtained in this way is used as a block, used alone or mixed with other blocks, interconnected, and finally wired to external connection pads to obtain the layout of the entire LSI chip.

Hereinafter, specific embodiments of the present invention will be described in detail.

First, an embodiment corresponding to claim 2 will be described. In all of the embodiments corresponding to "claim 2," the circuit of the two-input one-output selector shown in FIG. 1 is realized as a small-area transmission gate cell. "Claim 2"
A first embodiment corresponding to FIG. 9 will be described in detail with reference to FIGS. 9 to 12 are layout drawings of a cell, FIG. 9 shows a well, a diffusion region, and a gate polysilicon wiring, FIG. 10 shows the entire layout of the cell, and FIG. 11 shows the aluminum first layer wiring in FIG. FIG. 12 also shows only the aluminum second layer wiring.

First, a description will be given with reference to FIG. P-type MO
A first diffusion region 11 and a second diffusion region 12 are provided inside a well 16 for forming an S transistor. At this time, the second diffusion region 12 is arranged below the first diffusion region 11 when the well 16 is arranged on the layout drawing. Next, a third diffusion region 13 and a fourth diffusion region 14 are provided outside the well 16 and below the well 16 on the layout drawing. At this time, the fourth diffusion region 14 is arranged below the third diffusion region 13 on the layout drawing. Next, one P-type MOS transistor 1 is provided on the first diffusion region 11, two adjacent P-type MOS transistors 3 and 5 are provided on the second diffusion region 12, and a third diffusion region is provided. 13
On top of two adjacent N-type MOS transistors 4,
6 is provided, and one N-type MOS transistor 2 is provided on the fourth diffusion region 14. At this time, the structure is such that the four MOS transistors 1, 2, 3, and 6 share one gate polysilicon wiring 15.

The two-input one-output selector shown in FIG. 1 is constituted by the MOS transistors provided as described above. First, a CMOS inverter gate 20 is formed using the P-type MOS transistor 1 and the N-type MOS transistor 2. The wiring for this will be described with reference to FIGS. Aluminum first layer wiring 30, 31 is CMO
This is the power supply wiring of the S inverter gate 20. Here, the diffusion region contact 609 connects the aluminum first layer wiring and the diffusion region. The gate input wiring of the CMOS inverter gate 20 is realized by the gate polysilicon wiring 15, and a signal input is given to a point A in FIG. The output wiring of the CMOS inverter gate 20 is the first aluminum wiring 3
2, 33 and the gate polysilicon wiring 34.
Here, the polysilicon contact 610 connects the aluminum first layer wiring and the gate polysilicon wiring. Next, a first CMOS transmission gate 21 is formed by the P-type MOS transistor 3 and the N-type MOS transistor 4. For this purpose, the input B wiring is made of aluminum first layer wiring 35.
And the aluminum second layer wiring 36 is used for the output Y wiring. Here, the via hole 611 connects the aluminum second layer wiring and the aluminum first layer wiring. Next, the second CM is formed by the P-type MOS transistor 5 and the N-type MOS transistor 6.
The OS transmission gate 22 is configured. As a wiring for this purpose, an aluminum second-layer wiring 37 and an aluminum first-layer wiring 38 are used for the input C wiring. The output Y wiring also serves as the aluminum second layer wiring 36. The connection between the output of the CMOS inverter gate 20 and the gate inputs of the MOS transistors 4 and 5 is made up of the aluminum first layer wirings 32 and 33, which are the output wirings of the CMOS inverter gate 20, and the gate polysilicon wiring 34. The connection between the input A and the gate inputs of the MOS transistors 3 and 6 is also made by the gate polysilicon wiring 15. From the above, CMO
S inverter gate 20 and first CMOS transmission gate 2
A two-input, one-output selector consisting of one and the second CMOS transmission gate 22 is obtained. By arranging the diffusion regions 11 to 14 and sharing the gate polysilicon wiring 15 with the four MOS transistors 1, 2, 3, and 6, a transmission gate cell with a small area is realized.

Next, second to fourth embodiments corresponding to claim 2 will be described with reference to FIGS. FIG. 28 shows an embodiment in which the arrangement in the left-right direction of FIG. 10 is reversed. FIG. 29 shows an embodiment in which only the position of the well 16 in FIG. 10 is preserved, and the arrangement other than the well 16 in FIG. 10 is vertically inverted. FIG. 30 shows an embodiment in which the arrangement in the left-right direction of FIG. 29 is reversed. 28 to 30 are exactly the same as FIG. 10 in that the function of the two-input one-output selector shown in FIG. 1 is realized. By preparing a plurality of cells having different arrangements in advance as described above, it is easy to implement "claim 6" and "claim 7."

Next, a fifth embodiment of the present invention will be described with reference to FIGS. FIG.
1 to 34 are cell layout drawings, FIG. 31 shows wells, diffusion regions, and gate polysilicon wirings, FIG. 32 shows the entire cell layout diagram, and FIG.
34 shows only the aluminum first layer wiring, and FIG. 34 also shows only the aluminum second layer wiring. This embodiment is also the same as the small-area transmission gate cell realizing the function of the two-input one-output selector shown in FIG. The differences from FIG. 9 and FIG. 10 which are the first embodiment corresponding to “Claim 2” are as follows. FIG. 31 differs from FIG. 9 in that the gate polysilicon wiring 15 is bent and arranged. As a result, in FIGS. 32 to 34, it is possible to connect the B input wiring as the aluminum first layer wiring 61 and the C input wiring as the aluminum second layer wiring 62 with the shortest distance, respectively. This is an excellent small area transmission gate cell in that the aluminum wiring capacitance of the CMOS transmission gate input section is reduced. The numbers of the diffusion region and the transistor correspond to all the numbers used in the description of the first embodiment corresponding to claim 2, and differ only in the way of wiring. To supplement the differences in the wiring, the gate polysilicon wiring 34 in FIG.
In FIG. 31, since the gate polysilicon wirings 63 and 64 are divided, two gate polysilicon wirings 63 and 6 are formed.
4 and an aluminum second layer wiring 65 which is also an output wiring of the CMOS inverter gate 20.
It should be noted that correspondence of all the wirings with the circuit configuration of FIG. 1 can be easily confirmed from FIGS. 31, 33 and 34. In FIG. 32, the position of input A in gate polysilicon wiring 15 is arranged to be sandwiched between diffusion region 13 and diffusion region 14. Therefore, the gate widths of MOS transistors 4 and 6 cannot be made larger than this. This is because if the size is increased, the cell height (the length in the vertical direction) is also increased. On the other hand, in the arrangement of FIG.
The transistors 4 and 6, and the MOS transistors 3 and 5, can be further increased in gate width without changing the wiring at all. That is, the cells are easy to adjust the output drive capability of the CMOS transmission gate. The embodiment shown in FIG. 9 is excellent.

Next, a sixth to an eighth embodiment corresponding to claim 2 will be described with reference to FIGS. FIG. 35 shows an embodiment in which the arrangement in the left-right direction of FIG. 32 is reversed, and only the input C wiring is changed to the aluminum first-layer wiring. FIG. 36 shows an embodiment in which only the position of the well 16 in FIG. 32 is preserved, the arrangement other than the well 16 in FIG. 32 is reversed up and down, and the input C wiring is changed to the aluminum first layer wiring. FIG. 37 shows an embodiment in which the arrangement in the left-right direction of FIG. 36 is reversed. 35 to 37 are exactly the same as FIG. 32 in that the function of the two-input one-output selector shown in FIG. 1 is realized. By preparing a plurality of cells having different arrangements in advance as described above, it is easy to implement "claim 6" and "claim 7."

Next, a ninth embodiment corresponding to "claim 2" will be described with reference to FIGS. FIG.
41 is a layout drawing of a cell, and FIG. 38 shows a well, a diffusion region, and a gate polysilicon wiring.
9 shows the entire layout of the cell, FIG. 40 shows only the aluminum first layer wiring in FIG. 39, and FIG. 41 shows only the aluminum second layer wiring. This embodiment also has the configuration shown in FIG.
It is not limited to a small area transmission gate cell realizing the function of the input 1 output selector. The difference from FIG. 37 which is the eighth embodiment corresponding to "claim 2" is as follows. The greatest difference between FIGS. 38 to 41 is that the cell height (the length of the cell in the vertical direction in the drawing) is smaller than that in FIG. That is, this is an embodiment of a small area transmission gate cell having a smaller cell area. Due to the reduced cell height, the shape of the diffusion region 11 has changed, and the connection position of the input A has also moved slightly. However, all wirings have a structure that can easily correspond to FIG. ing.

Next, a first embodiment of the present invention will be described with reference to FIGS. In this embodiment, as shown in FIG. 2, a two-input one-output selector in which one of the inputs is an inverted input is realized as a small-area transmission gate cell. 13 to 16 are layout drawings of the cell, FIG. 13 shows a well, a diffusion region, and a gate polysilicon wiring, FIG. 14 shows the entire layout of the cell, and FIG. 15 shows the aluminum first layer wiring in FIG. FIG. 16 also shows only the aluminum second layer wiring. The main parts in FIGS. 13 to 15 are the same as those in FIGS. 31 to 34 which are the fifth embodiment corresponding to “Claim 2”, and differ only in the following points. That is, M
Diffusion region 1 for forming OS transistors 7 and 8
2 and 13 are expanded, gate polysilicon wiring 66
That the MOS transistors 7 and 8 are formed,
A second CMOS inverter gate 23 is constituted by the S transistors 7 and 8, and power supply wirings 67 and 68 for the second CMOS inverter gate 23 are provided. This means that FIG. 31 to FIG.
The second CM composed of the MOS transistors 7 and 8 corresponds to the small area transmission gate cell of the two-input one-output selector shown in FIG.
By adding the OS inverter gate 23, a two-input one-output selector having one of the inputs inverted is realized. Particularly in the case of the present embodiment, the output wiring of the second CMOS inverter gate 23 is connected to the CMOS transmission gate 2.
One input wiring 69 also serves as a small area transmission gate cell corresponding to the circuit of FIG. 2 with a minimum number of wirings.

Next, a second embodiment of the present invention will be described with reference to FIGS. 42 and 43. This embodiment is a small area transmission gate cell having a circuit configuration in which the second CMOS inverter gate 23 in FIG. 2 is moved to the C input side. 42 and 43 are layout drawings of the cell, FIG. 42 shows a well, a diffusion region, and a gate polysilicon wiring, and FIG. 43 shows the entire layout of the cell. 42 is compared with FIG. 13 of the first embodiment corresponding to claim 3, the positions of the MOS transistors 7 and 8 constituting the second CMOS inverter gate 23 are set from the right ends of the diffusion regions 12 and 13. The difference is that it has moved to the left end, and the wiring in FIG.
Has moved.

Next, a first embodiment of the present invention will be described with reference to FIGS. This embodiment is a small-area transmission gate cell corresponding to the two-input one-output selector with the CMOS inverter gate for output buffer shown in FIG. 17 to 20 are layout drawings of the cell, FIG. 17 shows a well, a diffusion region, and a gate polysilicon wiring, FIG. 18 shows the entire layout of the cell, and FIG. 19 shows the aluminum first layer wiring in FIG. FIG. 20 also shows only the aluminum second layer wiring.

First, a description will be given with reference to FIG. P type M
A first diffusion region 11 and a second diffusion region 12 are provided inside a well 16 for forming an OS transistor. At this time, the second diffusion region 12 is arranged below the first diffusion region 11 when the well 16 is arranged on the layout drawing. Next, outside the well 16 and below the well 16 on the layout drawing,
A third diffusion region 13 and a fourth diffusion region 14 are provided. At this time, the fourth diffusion region 14 is arranged below the third diffusion region 13 on the layout drawing. Next, two adjacent P-type MOS transistors 1 and 9 are provided on the first diffusion region 11, and two adjacent P-type MOS transistors 3 and 5 are provided on the second diffusion region 12. Two N-type MOSs adjacent to each other on the three diffusion regions 13
Transistors 4 and 6 are provided, and two N-type MOS transistors 2 and 10 adjacent to each other are provided on the fourth diffusion region 14. At this time, four MOS transistors 1, 2,.
3 and 6 have a structure in which one gate polysilicon wiring 15 is shared.

With the MOS transistors provided as described above, the output buffer CMOS shown in FIG.
A two-input one-output selector with an inverter gate is constructed. First, a CMOS inverter gate 20 is constituted by the P-type MOS transistor 1 and the N-type MOS transistor 2, and a first CMOS transmission gate 21 is constituted by the P-type MOS transistor 3 and the N-type MOS transistor 4.
A second CMOS transmission gate 22 is constituted by the MOS transistor 5 and the N-type MOS transistor 6, and the CM
The OS inverter gate 20, the first CMOS transmission gate 21, and the second CMOS transmission gate 22 constitute a two-input one-output selector. The wiring to realize the above is
It is almost the same as the wiring of FIG. 30 which is the fourth embodiment corresponding to "Claim 2".
Only the shape of the input wiring 70 is different from FIG. Next, the output buffer C is controlled by the MOS transistors 9 and 10.
The MOS inverter gate 24 is configured. The aluminum first layer wirings 71 and 72 are power supply wirings common to the CMOS inverter gate 24 for output buffer and the CMOS inverter gate 20. The gate polysilicon wiring 7 is used as a gate input wiring for the CMOS inverter gate 24 for output buffer.
3 and an aluminum second layer wiring 74 is provided as an output wiring of the CMOS inverter gate 24 for output buffering. Further, the output of the two-input one-output selector and the output buffer CMOS
By connecting the gate input of the inverter gate 24 with the aluminum first layer wiring 75, a small-area transmission gate cell having a function of a two-input one-output selector with a CMOS inverter gate for output buffer is formed.

Next, a second embodiment of the present invention will be described with reference to FIGS. 44 to 47. This embodiment is a small-area transmission gate cell corresponding to the two-input one-output selector with the CMOS inverter gate for output buffer shown in FIG. This embodiment is different from the first embodiment corresponding to "claim 4" in the following points from FIG. 17 to FIG. The biggest difference is that the gate widths of the MOS transistors 9 and 10 constituting the output buffer CMOS inverter gate 24 are larger than those in FIG. 17, and the output driving capability is increased. Accordingly, the shape of the diffusion region and the shape of the wiring have changed. 44 to 47 are layout drawings of the cell, FIG. 44 shows a well, a diffusion region, and gate polysilicon wiring, FIG. 45 shows the entire layout of the cell, and FIG. 46 shows the aluminum first layer wiring in FIG. FIG. 47 also shows only the aluminum second layer wiring.

Output buffering CMOS inverter gate 24
The characteristic structure for increasing the gate width of the MOS transistors 9 and 10 constituting the structure will be described with reference to FIG. The difference from FIG. 17 is that the height of the left half (length in the vertical direction in the figure) of the diffusion regions 11 and 14 is large, and the gate polysilicon wiring 73 of the MOS transistors 9 and 10 is bent. That is. As a result, the gate widths of MOS transistors 9 and 10 are increased, and gate polysilicon wiring 7 is formed.
3 and a space between the diffusion regions 12 and 13 are secured.
Further, since the connection position between the gate polysilicon wiring 73 and the output wiring of the two-input one-output selector has changed, the connection position of the input A in the gate polysilicon wiring 15 has also changed. As a result of these changes, the shapes of the aluminum first layer wiring and the aluminum second layer wiring have also partially changed, but the aluminum wiring in FIGS. 19 and 20 and the aluminum wiring in FIGS. I can take it.

Next, an embodiment corresponding to claim 5 will be described with reference to FIGS. In this embodiment,
This is a cell including a small-area transmission gate cell corresponding to claim 3 as a partial structure. The function of this cell is a D-latch having an inverted output shown in FIG. 52, which is one of the applications of a 2-input / 1-output selector using a CMOS transmission gate. When the G input is high (equal to the supply voltage), the value of the D input is inverted and immediately transmitted to the negative output of Q. Then D
If the input changes, the negative output of Q also changes. Next, when the G input goes low (zero volts), the negative output of Q continues to hold its previous value. 48 to 51 are layout drawings of the cell of this embodiment, FIG. 48 shows a well, a diffusion region, and a gate polysilicon wiring, FIG. 49 shows the entire layout of the cell, and FIG. Only the first layer wiring is shown, and FIG. 51 also shows only the aluminum second layer wiring. The layout diagram of FIG. 49 includes, as a partial structure, the layout of the first embodiment corresponding to “Claim 3” shown in FIG. That is, the left side from the center of FIGS. 48 and 49 corresponds to FIGS. 13 and 14, and the diffusion regions 11 to 14, MOS transistors 1 to 8, and gate polysilicon wirings 15 and 66 are shown in FIG.
48 and FIG. 48. These parts are
The CMOS inverter gates 20, 23,
The CMOS transmission gates 21 and 22 are configured. On the other hand, the right end part of FIG. 48 is an expanded part of FIG.
The P-type MOS transistor 80 and the N-type MOS transistor 83 constitute the output buffering CMOS inverter gate 25 in FIG. 52, and the P-type MOS transistor 81 and the N-type MOS transistor 82 form the third CM.
The OS inverter gate 26 is constituted. Two commercials
In order to form the OS inverter gates 25 and 26, the diffusion regions 12 and 13 are expanded into irregular shapes.
This embodiment is an example in which a small-area transmission gate cell according to claim 3 is used as a partial structure, a part of the diffusion region is expanded and deformed, and a new MOS transistor is formed to realize a cell with higher function. It has become. In addition to the present embodiment, a cell corresponding to claims 1 to 4 may be included as a partial structure, and a diffusion region thereof may be expanded or deformed to add a MOS transistor, or a gate polysilicon wiring may be added. It is clear that a more sophisticated cell can be configured by extending the length of the cell and sharing it with a new MOS transistor.

Next, an embodiment of claim 6 will be described. The first embodiment corresponding to "Claim 6" is as described in the section of "Embodiment" with reference to FIGS. 21 to 24, and the description is omitted. Next, when the cells 43 and 44 in FIG. 21 are removed from the layout diagram in FIG. 23, cells having exactly the same circuit functions as those in FIG. 27 are obtained.
That is, the CMOS inverter 50 shown in FIG.
The combination of the two-input / one-output selector 51 of the MOS transmission gate corresponds to the cell 40, and the two-input / one-output selectors 52 and 53 in FIG. 27 correspond to the cells 41 and 42. However, since the output drive capability of the cell 40 is small, attention must be paid to its use. The circuit composed of the cells 40 to 42 described above is also one of those that can be used as a high-performance logic design unit in the logic design of the pass transistor logic.

Next, another embodiment corresponding to claim 6 will be described with reference to FIGS.
This embodiment is an extension of the first embodiment corresponding to "claim 6". FIG. 53 also shows a layout diagram of a plurality of cells. Each of the cells 40 to 46 is
This is a small area transmission gate cell corresponding to any one of claims 1 to 4. The cell 40 corresponds to “Claim 4”, and the cells 41 to 46 are all small-area transmission gate cells corresponding to “Claim 2”. Is different. Next, these cells are arranged in a line so that there is no gap between adjacent cells. At this time, it is desirable to determine the arrangement order of the cells so that a desired logic function can be realized with the shortest possible wiring using these cells. In FIG. 54, the seven cells shown in FIG. 53 are arranged in a row without any gap. FIG. 59 shows a circuit that can be configured using these cells and that can be used as a high-performance logic design unit in the logic design of pass transistor logic.
This is a circuit in which a two-input one-output selector is arranged in a tree shape and an output buffer CMOS inverter gate is provided. Figure 59
FIG. 56 shows a layout in which inter-cell wiring is added to the layout of FIG. 54 in order to realize the circuit of FIG. Fig. 56
FIG. 55 shows the diffusion region and gate polysilicon wiring extracted from FIG. 55, FIG. 57 shows the aluminum first layer wiring extracted, and FIG. 58 shows the aluminum second layer wiring extracted. Here, another feature of the present embodiment will be described. Focusing on the height (vertical length in the drawing) of the diffusion regions 90 to 103 in FIG.
The heights of 0 and 91 are minimum, and the heights of the diffusion regions 100 to 103 of the cells 45 and 46 are maximum. When the height of the diffusion region is small, the gate width of the MOS transistor realized is small, and when the height of the diffusion region is large, the gate width of the MOS transistor realized is large. These diffusion regions 90 to 103 are used to realize the CMOS transmission gates 21 and 22 in FIG. 1 or FIG. That is, in this embodiment, the gate width of the MOS transistor used for the CMOS transmission gate is changed.
The gate width of the MOS transistor in the CMOS transmission gate in the cell 40 closest to the output is minimized, and the gate width in the CMOS transmission gate in the cells 45 and 46 farthest from the output is maximized. The width is also set to an intermediate value. When the different gate widths are used as described above, the delay power product is improved as compared with the case where the same gate width is used in the CMOS transmission gates of all the cells, and a cell capable of high-speed operation is obtained.

Next, an embodiment of claim 7 will be described. The first embodiment corresponding to "Claim 7" is as described in the section of "Embodiment" with reference to FIGS. 25 to 27, and the description is omitted. Next, cell 4 in FIG.
After replacing 0 with the cells 50 and 51 in the first embodiment, by arranging the cells and performing inter-cell wiring, FIG.
A cell having a function equivalent to that of the circuit No. 4 and having an enhanced output drive capability of the output buffering CMOS inverter gate can be obtained. This is also one of the embodiments of "claim 7". Also, after replacing the cell 40 in FIG. 53 with the cells 50 and 51 in the first embodiment, by arranging the cells and wiring between the cells, the cell has a function equivalent to the circuit in FIG. In addition, a cell can be obtained in which the output and drive capability of the output buffer CMOS inverter gate are enhanced.
This is also one of the embodiments of "claim 7".

Next, another embodiment of the present invention will be described with reference to FIGS. In this embodiment, the cell 56 corresponding to claim 2 and the CMOS NA
The circuit function of the inverted output 2-input / 1-output selector with output enable shown in FIG. 62 is realized by the ND gate cell 55. That is, the cell 55 in FIG.
And cells 56 are arranged in a line so that there is no gap between adjacent cells,
Further, the layout shown in FIG. 61 is obtained by wiring between cells. As in the present embodiment, by arranging one or more small-area transmission gate cells and one or more CMOS gate cells according to claims 1 to 4 and providing wiring between cells, a useful cell having more advanced functions is provided. Can be realized.

[0068]

According to the present invention, when a cell of a two-input one-output selector, which is a minimum structural unit for configuring a pass transistor logic, is realized using a CMOS transmission gate, the cell size is smaller than that of the prior art. A cell having an area can be realized. When comparing the cell based on the prior art in FIG. 70 with the cell according to the embodiment of the present invention in FIG. 10, since the functions of the two are equal and the scale of the drawing is the same, the effect of reducing the area according to the present invention is obvious. is there. By configuring an LSI using cells having a small area, the chip area of the LSI is reduced, the LSI manufacturing cost is reduced, and the effects of reducing power consumption and operating speed of the LSI can be expected.

In other words, when using a pass transistor logic based on a CMOS transmission gate, which is suitable for operation at a low power supply voltage and thus enables realization of a low power consumption LSI, according to the prior art, Although the cell area is increased and the problem of the increase in the production cost is mainly caused, the implementation of the present invention enables the cell of a small area, and can solve or reduce the problem of the increase in the production cost.

Further, according to the present invention, since it is easy to construct a high-performance cell including a two-input one-output selector as a partial structure using a CMOS transmission gate, a high-performance cell which can be used as a logic design unit of pass transistor logic is provided. Types can be easily expanded. Since the preparation of the required high-function cells is facilitated, the design efficiency in the logic design of the pass transistor logic is improved. Further, according to the present invention, FIG.
When cells are arranged in a horizontal row as shown in FIG.
Compared to the case where the cells as shown in FIG.
The width can be reduced, so that the cells interconnecting
The wiring length is shortened and the amount of capacitors in the aluminum wiring part is reduced.
It is effective to shorten the circuit operation delay. Pastrun
In the register logic, for example, in FIG.
The wiring at the point 517, that is, the wiring interconnecting the cells
If the capacitor is large, the operation delay increases,
In particular, the rate of increase is greater than in conventional CMOS. this
Therefore, the present invention reduces the wiring length between cells and reduces
Has a significant effect on reducing operation delays.
You.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing functions of a small-area transmission gate cell of the present invention.

FIG. 2 is a circuit diagram showing functions of a small-area transmission gate cell of the present invention.

FIG. 3 is a circuit diagram showing functions of a small-area transmission gate cell according to the present invention.

FIG. 4 is a part of a layout diagram of a small-area transmission gate cell, showing an embodiment of the present invention.

FIG. 5 is a part of a layout diagram of a small-area transmission gate cell, showing an embodiment of the present invention.

FIG. 6 is a layout diagram of a small-area transmission gate cell;
1 shows an embodiment of the present invention.

FIG. 7 is a part of a layout diagram of a small-area transmission gate cell, showing an embodiment of the present invention.

FIG. 8 is a part of a layout diagram of a small-area transmission gate cell, showing an embodiment of the present invention.

FIG. 9 is a part of a layout diagram of a small-area transmission gate cell, showing an embodiment of the present invention.

FIG. 10 is a layout diagram of a small-area transmission gate cell, showing an embodiment of the present invention.

FIG. 11 is a part of a layout diagram of a small-area transmission gate cell, showing an embodiment of the present invention.

FIG. 12 is a part of a layout diagram of a small-area transmission gate cell, showing an embodiment of the present invention.

FIG. 13 is a portion of a layout diagram of a small area transmission gate cell, illustrating an embodiment of the present invention.

FIG. 14 is a layout diagram of a small area transmission gate cell, showing an embodiment of the present invention.

FIG. 15 is a portion of a layout diagram of a small area transmission gate cell, illustrating an embodiment of the present invention.

FIG. 16 is a part of a layout diagram of a small-area transmission gate cell, showing an embodiment of the present invention.

FIG. 17 is a part of a layout diagram of a small-area transmission gate cell, showing an embodiment of the present invention.

FIG. 18 is a layout diagram of a small-area transmission gate cell, showing an embodiment of the present invention.

FIG. 19 is a part of a layout diagram of a small-area transmission gate cell, showing an embodiment of the present invention.

FIG. 20 is a part of a layout diagram of a small-area transmission gate cell, showing an embodiment of the present invention.

FIG. 21 shows an arrangement of a plurality of small-area transmission gate cells;
1 shows an embodiment of the present invention.

FIG. 22 shows an arrangement of a plurality of small-area transmission gate cells,
1 shows an embodiment of the present invention.

FIG. 23 is a layout diagram of a cell, showing an embodiment of the present invention.

FIG. 24 is a circuit diagram showing functions of a cell including a plurality of small-area transmission gate cells.

FIG. 25 shows an arrangement of small area transmission gate cells and other cells, and represents an embodiment of the present invention.

FIG. 26 is a layout diagram of a cell, showing an embodiment of the present invention.

FIG. 27 is a circuit diagram illustrating functions of a cell including a small area transmission gate cell and another cell.

FIG. 28 is a layout diagram of a small area transmission gate cell and represents an embodiment of the present invention.

FIG. 29 is a layout diagram of a small area transmission gate cell and represents an embodiment of the present invention.

FIG. 30 is a layout diagram of a small area transmission gate cell and represents an embodiment of the present invention.

FIG. 31 is a portion of a layout diagram of a small-area transmission gate cell, illustrating an embodiment of the present invention.

FIG. 32 is a layout diagram of a small-area transmission gate cell and represents an embodiment of the present invention.

FIG. 33 is a portion of a layout diagram of a small-area transmission gate cell, illustrating an embodiment of the present invention.

FIG. 34 is a portion of a layout diagram of a small-area transmission gate cell, illustrating an embodiment of the present invention.

FIG. 35 is a layout diagram of a small area transmission gate cell and represents an embodiment of the present invention.

FIG. 36 is a layout diagram of a small-area transmission gate cell and represents an embodiment of the present invention.

FIG. 37 is a layout diagram of a small area transmission gate cell and represents an embodiment of the present invention.

FIG. 38 is a portion of a layout diagram of a small-area transmission gate cell, illustrating an embodiment of the present invention.

FIG. 39 is a layout diagram of a small area transmission gate cell and represents an embodiment of the present invention.

FIG. 40 is a portion of a layout diagram of a small-area transmission gate cell, illustrating an embodiment of the present invention.

FIG. 41 is a portion of a layout diagram of a small-area transmission gate cell, illustrating an embodiment of the present invention.

FIG. 42 is a portion of a layout diagram of a small-area transmission gate cell, illustrating an embodiment of the present invention.

FIG. 43 is a layout diagram of a small-area transmission gate cell and represents an embodiment of the present invention.

FIG. 44 is a portion of a layout diagram of a small-area transmission gate cell, illustrating an embodiment of the present invention.

FIG. 45 is a layout diagram of a small area transmission gate cell and represents an embodiment of the present invention.

FIG. 46 is a portion of a layout diagram of a small-area transmission gate cell, illustrating an embodiment of the present invention.

FIG. 47 is a portion of a layout diagram of a small-area transmission gate cell, illustrating an embodiment of the present invention.

FIG. 48 is a part of a cell layout diagram showing an embodiment of the present invention.

FIG. 49 is a layout diagram of a cell, showing an embodiment of the present invention.

FIG. 50 is a part of a cell layout diagram showing an embodiment of the present invention.

FIG. 51 is a part of a cell layout diagram showing an embodiment of the present invention.

FIG. 52 is a circuit diagram illustrating the function of a cell according to the present invention.

FIG. 53 shows an arrangement of a plurality of small-area transmission gate cells;
1 shows an embodiment of the present invention.

FIG. 54 shows an arrangement of a plurality of small-area transmission gate cells;
1 shows an embodiment of the present invention.

FIG. 55 is a portion of a cell layout diagram and represents an embodiment of the present invention.

FIG. 56 is a layout diagram of a cell, showing an embodiment of the present invention.

FIG. 57 is a portion of a cell layout diagram and represents an embodiment of the present invention.

FIG. 58 is a portion of a cell layout diagram and represents an embodiment of the present invention.

FIG. 59 is a circuit diagram illustrating functions of a cell including a plurality of small-area transmission gate cells.

FIG. 60 shows an arrangement of small area transmission gate cells and other cells, and represents an embodiment of the present invention.

FIG. 61 is a layout diagram of a cell, showing an embodiment of the present invention.

FIG. 62 is a circuit diagram illustrating functions of a cell including a small-area transmission gate cell and another cell.

FIG. 63 is a circuit diagram of pass transistor logic according to the related art.

FIG. 64 is a circuit diagram of pass transistor logic according to the related art.

FIG. 65 is a layout diagram of a conventional CMOS gate cell.

FIG. 66 is a circuit diagram illustrating functions of a CMOS gate cell according to the related art.

FIG. 67 is a part of a layout diagram of a conventional CMOS gate cell.

FIG. 68 is a part of a layout diagram of a conventional CMOS gate cell.

FIG. 69 is a part of a layout diagram of a conventional CMOS gate cell.

FIG. 70 is a prior art cell layout diagram equivalent to a small area transmission gate cell.

FIG. 71 is a prior art cell layout diagram equivalent to a small area transmission gate cell.

FIG. 72 is a layout diagram of a prior art cell equivalent to a small area transmission game cell.

FIG. 73 is a prior art cell layout diagram equivalent to a small area transmission gate cell.

[Explanation of symbols]

1,3,5,7,9,80,81,512,514,6
00,601 P-type MOS transistor 2,4,6,8,10,82,83 N-type MOS transistor 500,501,503,504,511,513,6
02,603 N-type MOS transistors 11,12,13,14,90-103 Diffusion region 605,606,611,612,613,614 Diffusion region 15,34,63,64,66,73,607,608
Gate polysilicon wiring 16,604 well 20,23,26,502,505,515 CMOS
Inverter gate 24, 25, 506 Output buffer CMOS inverter gate 21, 22 CMOS transmission gate 30, 31, 32, 33, 35, 38 Aluminum first layer wiring 61, 67, 68, 69, 70, 71, 72, 75 Aluminum first layer wiring 36,37,62,65,74 Aluminum second layer wiring 40-46,50-53,55,56 Cell 507,508,517 Output point of selection switch 609 Diffusion area contact 610 Polysilicon contact 611 Beer hall

Claims (8)

(57) [Claims] 1. A cell used as a component of an LSI formed by a CMOS process and having one well for forming a P-type MOS transistor.
When placing the well upwards, it has a first diffusion region and the second diffusion region in the interior of the well, and located below the second diffusion region is a first diffusion region, further external a and the c <br/> below the E Le has a third diffusion region and the fourth diffusion region, and positioned below the fourth diffusion region is the third diffusion region of the well The first feature of the present invention is that a P-type MOS transistor (1) is provided on the first diffusion region.
The a, has an N-type MOS transistor (2) to said fourth diffusion region has the second of the two P-type MOS transistor which are adjacent to each other in the diffusion region (3,5), Previous
Two N-type MOS adjacent to each other in serial third diffusion region
Transistors (4,6) has a said first P-type MOS transistor on the diffusion region (1)
And said fourth N-type MOS transistor on the diffusion region (2) constitute a CMOS inverter gate, said second P-type MOS transistor on the diffusion region (3) and the <br/> third diffusion region configure the N-type MOS transistor (4) is a first CMOS transmission gate above, the second P-type MOS transistor on the diffusion region (5) and the third N-type MOS transistor on the diffusion region (6 ) Is the second CMO
Configure the S transmission gate, and the CMOS inverter gates, said first CMOS transmission gate and the second C
A two-input one-output selector constituted by a MOS transmission gate, wherein a P-type MOS transistor (1) on the first diffusion region, an N-type MOS transistor (2) on the fourth diffusion region , A total of four MOS transistors, a P-type MOS transistor (3) on the second diffusion region and an N-type MOS transistor (6) on the third diffusion region, share one gate polysilicon wiring. A small-area transmission gate cell according to a second structural feature. 2. The semiconductor device according to claim 1, wherein only one P-type MOS transistor is provided on said first diffusion region, and only two P-type MOS transistors are provided on said second diffusion region. a has the third only two N-type MOS transistor in the diffusion region of the (4,6), only the fourth diffusion region 1
Has a number of N-type MOS transistor (2), it has a connection for configuring the CMOS inverter gate between the P-type MOS transistor (1) and N-type MOS transistor (2), the P-type MOS transistor (3) and the N-type has a connection for configuring the <br/> first CMOS transmission gate between the MOS transistor (4), the P-type MOS transistor (5) and the N-type MOS
Has a connection for constituting the second CMOS transfer gate between the transistor (6), further wherein the gate and the P-type MOS transistor of the output of the CMOS inverter gate the N-type MOS transistor (4) (5 )
2. The small-area transmission gate cell according to claim 1, wherein a two-input / one-output selector is formed by having a connection to the gate of (1) . 3. The semiconductor device according to claim 1, further comprising one P-type MOS transistor on said second diffusion region and one N-type MOS transistor on said third diffusion region.
It has the P-type MOS transistor (7) and the N-type MOS transistor (8) constitutes the second CMOS inverter gate, and one of the second output two inputs and one output selector of the CMOS inverter gate 2. The small-area transmission gate cell according to claim 1, wherein one input of the two- input / one-output selector is made an inverting input by being connected to an input of the small-area transmission gate cell. 4. The semiconductor device according to claim 1, further comprising one P-type MOS transistor on said first diffusion region, and one further N-type MOS transistor on said fourth diffusion region.
Has 0), the P-type MOS transistor (9) and N
Type MOS transistor (10) constitutes the output buffer for CMOS inverter gate, the connection to the gate of the gate and the N-type MOS transistor (10) of the output of 2-input 1-output selector the P-type MOS transistor (9) 2. The small area transmission gate cell according to claim 1, wherein the transmission gate cell has a two-input one-output selector with a CMOS inverter gate for output buffering. 5. Claim 1, Claim 2, Claim 3, Claim
Cells, wherein are Nde containing as any one or more partial structures of the small area transmission gate cell as claimed in claim 4. 6. Claim 1, Claim 2, Claim 3, Claim
6. The cell according to claim 5, wherein at least two of the small-area transmission gate cells according to item 4 are arranged in a line so that there is no gap between the cells, and wiring is provided between the cells. 7. Claim 1, Claim 2, Claim 3, Claim
And at least one and one or more CMOS gate cell having a small area transmission gate cell as claimed in claim 4 arranged in a row so that there is no gap between the cells, obtained by performing inter-cell wiring
A cell according to claim 5 . 8. The cell according to claim 1 , wherein at least
Stan <br/> Dadoseru system LSI, characterized in that also Nde contains the components of one.