JP3100010B2 - Power factor transducer - Google Patents

Power factor transducer

Info

Publication number
JP3100010B2
JP3100010B2 JP27701392A JP27701392A JP3100010B2 JP 3100010 B2 JP3100010 B2 JP 3100010B2 JP 27701392 A JP27701392 A JP 27701392A JP 27701392 A JP27701392 A JP 27701392A JP 3100010 B2 JP3100010 B2 JP 3100010B2
Authority
JP
Japan
Prior art keywords
signal
output
circuit
phase difference
power factor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP27701392A
Other languages
Japanese (ja)
Other versions
JPH06130096A (en
Inventor
正晃 西條
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Electric Corp filed Critical Yokogawa Electric Corp
Priority to JP27701392A priority Critical patent/JP3100010B2/en
Publication of JPH06130096A publication Critical patent/JPH06130096A/en
Application granted granted Critical
Publication of JP3100010B2 publication Critical patent/JP3100010B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、送電,配電,受電等の
電力ラインにおける力率をこれに対応した直流信号に変
換する力率トランスデューサに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power factor transducer for converting a power factor in a power line such as power transmission, distribution, and power reception into a DC signal corresponding to the power factor.

【0002】[0002]

【従来の技術】電力ラインにおける電圧と電流の位相差
ψ(図3に示す)は比較的簡単な回路によって高精度で
検出することが可能である。これに対して、力率±(1
−COSψ)(図4に示す)に比例した信号を得るには、
図3の位相差信号ψをアナログのリニアライズ回路を用
いて変換する方法がこれまでに幾つか提案されてきた
が、変換範囲が限定されたり、使用周波数も限定された
りして、必ずしも満足したものが得られないのが実情で
ある。
2. Description of the Related Art The phase difference 電 圧 (shown in FIG. 3) between a voltage and a current in a power line can be detected with high accuracy by a relatively simple circuit. On the other hand, the power factor ± (1
−COSψ) (shown in FIG. 4)
Several methods have been proposed so far for converting the phase difference signal て in FIG. 3 using an analog linearize circuit. However, the conversion range is limited and the frequency used is also limited. The fact is that you can't get anything.

【0003】[0003]

【発明が解決しようとする課題】本発明は、−90゜〜
0゜〜+90゜の広い入力範囲に亘った力率をこれに比
例した正確な出力に変換すると共に、入力周波数に依存
しない変換出力を得ることのできるトランスデューサを
実現することを目的としたものである。
DISCLOSURE OF THE INVENTION The present invention is directed to -90 ° to -90 °.
An object of the present invention is to realize a transducer capable of converting a power factor over a wide input range from 0 ° to + 90 ° into an accurate output proportional to the input factor and obtaining a converted output independent of an input frequency. is there.

【0004】[0004]

【課題を解決するための手段】本発明は、入力の交流電
圧と交流電流の位相差を検出する位相差検出回路、この
位相差検出回路の出力を正のみの信号に変換する絶対値
回路、前記位相差検出回路の出力と絶対値回路の出力と
を掛算するパルス幅変調方式の掛算器、及び前記絶対値
回路の出力が所定の電圧を越えると掛算器の出力にバイ
アスを加える手段を具備したものである。
According to the present invention, there is provided a phase difference detecting circuit for detecting a phase difference between an input AC voltage and an AC current, an absolute value circuit for converting an output of the phase difference detecting circuit into a positive-only signal, A pulse width modulation multiplier for multiplying the output of the phase difference detection circuit and the output of the absolute value circuit; and a means for applying a bias to the output of the multiplier when the output of the absolute value circuit exceeds a predetermined voltage. It was done.

【0005】[0005]

【作用】このような本発明では、パルス幅変調方式の掛
算器を用いた(2乗曲線)+(2乗曲線)によるリニア
ライズ回路で力率がこれに比例した直流信号に変換され
る。
According to the present invention, the power factor is converted into a DC signal whose power factor is proportional to the linearization circuit of (square curve) + (square curve) using the multiplier of the pulse width modulation system.

【0006】[0006]

【実施例】以下図面を用いて本発明を説明する。図1は
本発明に係わる力率トランスデューサの一実施例を示す
構成図である。図において、11は電力ラインにおける
交流電圧vが供給される変成器、12は同じく電流iが
供給される変成器、20は入力の交流電圧vと電流iの
位相差ψを検出する位相差検出回路である。この位相差
検出回路は公知の種々の回路を用いることができる。3
0は位相差検出回路20の出力ψを正極性出力のみに変
換する絶対値回路、40はコンパレータ、41は電圧V
xの電圧源である。コンパレータ40は絶対値変換回路
20の出力ψと電圧Vxとを比較する。60はパルス幅
変調方式を用いた公知の掛算器で、入力AとBを掛算
し、掛算結果Cを出力する。前記の位相差検出回路20
の出力端子は絶対値変換回路30の入力端子に接続され
ると共に、掛算器60のA入力端子に接続されている。
51,52はスイッチ、53〜55は抵抗素子、56は
電圧Vyの電圧源である。絶対値回路30の出力端子は
前記したようにコンパレータ40の入力端子に接続され
ると共に、抵抗素子53と,抵抗素子54とスイッチ5
1の直列回路を介して掛算器60のB入力端子に接続さ
れている。スイッチ52は抵抗素子55と電圧源Vyの
直列回路を介して掛算器60の出力端子Cに接続されて
いる。70は入力端Inから入力された信号に加算信号
端Adから入力された信号を加算する加算機能と、ここ
で得られた加算信号に対応する直流信号を出力するスケ
ーリング機能を備えたフイルター回路で、その入力端
は掛算器60の出力端子に接続されている。80は力
率に対応した直流信号が取り出される出力端子である。
前記の絶対値回路30のψ出力が基準電圧Vxより大き
くなったときに、スイッチ51はオンからオフに、逆に
スイッチ52はオフからオンに切り換えられるようにな
っている。このような構成の本発明に変わるトランスデ
ューサの動作を説明すると次の如くなる。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a configuration diagram showing one embodiment of a power factor transducer according to the present invention. In the figure, 11 is a transformer to which an AC voltage v is supplied in a power line, 12 is a transformer to which a current i is also supplied, and 20 is a phase difference detector for detecting a phase difference の between an input AC voltage v and a current i. Circuit. Various known circuits can be used as the phase difference detection circuit. 3
0 is an absolute value circuit that converts the output の of the phase difference detection circuit 20 into only a positive output, 40 is a comparator, 41 is a voltage V
x voltage source. Comparator 40 compares output ψ of absolute value conversion circuit 20 with voltage Vx. Reference numeral 60 denotes a known multiplier using a pulse width modulation method, multiplies inputs A and B, and outputs a multiplication result C. The phase difference detection circuit 20
Is connected to the input terminal of the absolute value conversion circuit 30 and to the A input terminal of the multiplier 60.
51 and 52 are switches, 53 to 55 are resistance elements, and 56 is a voltage source of the voltage Vy. The output terminal of the absolute value circuit 30 is connected to the input terminal of the comparator 40 as described above, and the resistance element 53, the resistance element 54 and the switch 5 are connected.
It is connected to the B input terminal of the multiplier 60 via one series circuit. The switch 52 is connected to the output terminal C of the multiplier 60 via a series circuit of the resistance element 55 and the voltage source Vy. 70 is a signal added to the signal input from the input terminal In.
An addition function for adding the signal input from the terminal Ad;
In filter circuit having a scale <br/>-ring function to output a DC signal that corresponds to the addition signal obtained by, its input terminal I
n is connected to the output terminal of the multiplier 60. Reference numeral 80 denotes an output terminal from which a DC signal corresponding to the power factor is extracted.
When the ψ output of the absolute value circuit 30 becomes larger than the reference voltage Vx, the switch 51 is switched from on to off, and conversely, the switch 52 is switched from off to on. The operation of the transducer having the above-mentioned structure and which is replaced by the present invention will be described as follows.

【0007】電力ラインにおける交流電圧vと電流iは
変成器11と12をそれぞれ介して位相差検出回路20
に加えられて両者の位相差ψが検出される。検出された
位相差信号ψは掛算器60にA信号として加えられると
共に、絶対値回路30に加えられて正のみの値を持つB
信号に変換された後、コンパレータ40に加えられる。
コンパレータ40はこの絶対値回路30の出力と基準電
圧Vxとを比較する。この場合、絶対値回路30のψ出
力が基準電圧Vxより小さい間はスイッチ51はオン、
スイッチ52はオフになり、上記A信号は上記位相差信
号ψに比例し、上記B信号は上記位相差信号ψの絶対値
に比例しているので、基準電圧Vxによって決定される −X≦ψ≦+X の範囲では掛算器60の出力Cは C=A×B=ψ×|ψ| …(1) で表される。一方、絶対値回路30のψ出力が基準電圧
Vxより大きくなるとスイッチ51はオフ、スイッチ5
2はオンになり、上記(1)式の場合と同様にA信号は
上記位相差信号ψに比例し、上記B信号は上記位相差信
号ψの絶対値に比例しているので、基準電圧Vxによっ
て決定される −90゜≦ψ≦−X,−90゜≦ψ≦+90゜ の範囲では掛算器60の出力Cは C=A×B=ψ×α|ψ| …(2)で表される。 但し、αは抵抗素子53と54によって定
まる係数である。 そしてスイッチ52がオンになること
により、フィルタ70の加算信号端Adに電圧Vyが印
加されるので、フィルタ70の加算機能により、入力端
Inに入力された(2)式で表される信号Cに電圧Vy
がバイアスとして加わる。このバイアスをYとすると D=α・ψ|ψ|+Y …(3)となり、 この(3)式で表される信号がフイルタ70の
スケーリング機能によって直流信号に変換され、その直
流信号が出力端子80より直流信号Eoとして取り出さ
れる。(1)式と(3)式で表されるCとDを図示する
と図2の如くなる。図2は図4で示す力率±(1−COS
ψ)近似した信号となる。
[0007] The AC voltage v and the current i in the power line are transmitted through transformers 11 and 12, respectively, to the phase difference detection circuit 20.
And the phase difference 両 者 between the two is detected. The detected phase difference signal ψ is applied to multiplier 60 as an A signal, and is also applied to absolute value circuit 30 so that B having a positive value only
After being converted into a signal , it is applied to a comparator 40.
The comparator 40 compares the output of the absolute value circuit 30 with the reference voltage Vx. In this case, while the ψ output of the absolute value circuit 30 is smaller than the reference voltage Vx, the switch 51 is turned on,
The switch 52 is turned off, and the signal A becomes the phase difference signal.
B signal is the absolute value of the phase difference signal ψ
Therefore, the output C of the multiplier 60 is expressed as follows: C = A × B = ψ × │ψ│ (1) in the range of −X ≦ ψ ≦ + X determined by the reference voltage Vx . On the other hand, when the ψ output of the absolute value circuit 30 becomes larger than the reference voltage Vx, the switch 51 is turned off, and the switch 5 is turned off.
2 is turned on, and the A signal becomes the same as in the case of the above equation (1).
The B signal is proportional to the phase difference signal ψ, and the B signal is
Since it is proportional to the absolute value of signal 、, it depends on the reference voltage Vx.
-90 ° ≦ [psi ≦ -X determined Te, the output C of the multiplier 60 in the range of -90 ° ≦ ψ ≦ + 90 DEG C = A × B = ψ × α | represented by ... (2) | ψ You. Here, α is a coefficient determined by the resistance elements 53 and 54 . When the switch 52 is turned on , the voltage Vy is impressed on the addition signal end Ad of the filter 70.
, The addition function of the filter 70 allows the input terminal
The voltage Vy is applied to the signal C represented by the equation (2) input to In.
Is added as a bias. Assuming that this bias is Y, D = α · ψ | ψ | + Y (3) , and the signal represented by the equation (3) is
The signal is converted into a DC signal by the scaling function , and the DC signal is extracted from the output terminal 80 as a DC signal Eo. FIG. 2 shows C and D expressed by the equations (1) and (3). FIG. 2 shows the power factor ± (1-COS
the approximate signal to [psi).

【0008】[0008]

【発明の効果】本発明によれば、(2乗曲線)+(2乗
曲線)によるリニアライズ回路で力率に比例した信号を
得る様にしたもので、その2乗曲線を得る掛算器として
パルス幅変調方式を用いている。パルス幅変調回路は入
力周波数に依存しないので、このようなパルス幅変調回
路をリニアライズ回路として用いるようにした本発明に
よれば周波数に依存しないトランスデューサを得ること
ができる。又、得られる力率信号は、バイアスVyによ
って決まる折点及び抵抗素子53及び54によって決ま
る2乗係数を適正値に選ぶことにより、−90゜〜0゜
〜+90゜の範囲で最大誤差を0.004(力率変換)
以下とすることが可能である。
According to the present invention, a signal proportional to the power factor is obtained by a linearization circuit based on (square curve) + (square curve). As a multiplier for obtaining the square curve, A pulse width modulation method is used. Since the pulse width modulation circuit does not depend on the input frequency, according to the present invention in which such a pulse width modulation circuit is used as a linearization circuit, a transducer that does not depend on the frequency can be obtained. The obtained power factor signal has a maximum error of 0 in the range of -90 ° to 0 ° to + 90 ° by selecting a breakpoint determined by the bias Vy and a square coefficient determined by the resistance elements 53 and 54 to appropriate values. .004 (power factor conversion)
It is possible to:

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の力率トランスデューサの一実施例を示
した回路図である。
FIG. 1 is a circuit diagram showing one embodiment of a power factor transducer of the present invention.

【図2】本発明のトランスデューサによって得られる力
率信号を示す図である。
FIG. 2 is a diagram showing a power factor signal obtained by the transducer of the present invention.

【図3】位相差信号を示す図である。FIG. 3 is a diagram illustrating a phase difference signal.

【図4】力率信号を示す図である。FIG. 4 is a diagram showing a power factor signal.

【符号の説明】[Explanation of symbols]

11,12 変成器 20 位相差検出回路 30 絶対値回路 40 コンパレータ 51,52 スイッチ 53〜55 抵抗素子 60 パルス幅変調回路 70 フイルタ 80 出力端子 11, 12 Transformer 20 Phase difference detection circuit 30 Absolute value circuit 40 Comparator 51, 52 Switch 53-55 Resistance element 60 Pulse width modulation circuit 70 Filter 80 Output terminal

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】入力の交流電圧と交流電流の位相差を検出
する位相差検出回路、この位相差検出回路の出力を正の
みの信号に変換する絶対値回路、前記位相差検出回路の
出力と絶対値回路の出力とを掛算するパルス幅変調方式
の掛算器、及び前記絶対値回路の出力が所定の電圧を越
えると前記掛算器の出力にバイアスを加える手段を具備
し、前記掛算器出力をフイルタを介して取り出すように
構成した力率トランスデューサ。
1. A phase difference detection circuit for detecting a phase difference between an input AC voltage and an AC current, an absolute value circuit for converting an output of the phase difference detection circuit into a positive-only signal, and an output of the phase difference detection circuit. A pulse width modulation multiplier for multiplying the output of the absolute value circuit, and a means for applying a bias to the output of the multiplier when the output of the absolute value circuit exceeds a predetermined voltage, A power factor transducer configured to be removed through a filter.
JP27701392A 1992-10-15 1992-10-15 Power factor transducer Expired - Fee Related JP3100010B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27701392A JP3100010B2 (en) 1992-10-15 1992-10-15 Power factor transducer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27701392A JP3100010B2 (en) 1992-10-15 1992-10-15 Power factor transducer

Publications (2)

Publication Number Publication Date
JPH06130096A JPH06130096A (en) 1994-05-13
JP3100010B2 true JP3100010B2 (en) 2000-10-16

Family

ID=17577555

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27701392A Expired - Fee Related JP3100010B2 (en) 1992-10-15 1992-10-15 Power factor transducer

Country Status (1)

Country Link
JP (1) JP3100010B2 (en)

Also Published As

Publication number Publication date
JPH06130096A (en) 1994-05-13

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