JP3099046B2 - Non-volatile storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field]   The present invention relates to a data storage technology or even a semiconductor memory.
Technology that is particularly effective when applied to
And configure, for example, a microcomputer system
Useful for address allocation method in memory board
About effective technology. [Background Art]   The main storage of a microcomputer system is an example
For example, RAM with short access time (random access memory)
Mori). However, RAM
Memory that can retain data when power is turned off.
I can't. Therefore, the data to be stored in RAM
To configure a system that can be maintained even after the power is turned off
Memory board backed up by a battery
(RAM board) has been proposed.   Battery-backed memory board
About Hitachi, Ltd. issued in September 1984
Catalog "16kbit Byte Battery Backup CMOS"
Memory Board H68CM1P-1 User's Manual "
It is listed.   However, battery-backed memory cards
In addition to RAM, battery and power supply voltage
Circuit to detect RAM degradation and prohibit access to RAM
Must be mounted on the board.
The mounting density of RAM on the memory will be reduced. In particular, 16
Microprocessors such as bit and 32-bit
Storage capacity increases as the address space increases.
It tends to be bigger. However, to increase storage capacity
As the number of RAMs used increases, the larger
Backup battery is required.
You.   Therefore, the present inventor has proposed a semiconductor device constituting a memory board.
As memory, backup by battery after power off
An electrically erasable EEPROM that does not require a
Recitalily erasable programmable leads
・ Only memory) was considered.   Here, EEPROM is for one cycle of data writing
For example, a relatively long time of about 10 ms is required. for that reason,
For example, the same address assignment as a memory board using RAM
Write data to one memory.
When it ends, it moves to the next memory
Write data to each EEPROM according to (See Fig. 5)
, On the other hand, a 10ms wait time for each data
Will be needed. As a result, extremely long write times
There is a disadvantage that it becomes. [Object of the invention]   It is an object of the present invention that a battery backup is required.
Data stored without need is retained even after power is turned off
To provide storage devices using such semiconductor memories
is there.   Another object of the present invention is to provide a storage device using a semiconductor memory.
The object is to improve the mounting density of the devices.   Still another object of the present invention is to write data.
Address allocation method that can reduce the
It is to be.   The above and other objects and novel features of the present invention
Is apparent from the description of the present specification and the accompanying drawings.
Will be. [Summary of the Invention]   Summary of typical inventions disclosed in this application
The point is as follows.   In other words, the semiconductor memory that constitutes the memory board
Using EEPROM instead of RAM,
Continuous to EPROM in byte units or word units
Address assignment to write data sequentially
Power off the stored data by adopting the method
Retain without battery backup
Memory and the amount of memory required
Package density can be increased and writing to one EEPROM
While writing to the next EEPROM.
To reduce the time required to write data.
This achieves the above object of shortening.   Hereinafter, the present invention will be specifically described with reference to the drawings. [Example]   Fig. 1 shows a 16-bit microprocessor of the 68000 series.
The present invention is applied to a memory board that constitutes a system using
One embodiment when applied is shown.   Although the memory board of this embodiment is not particularly limited,
16 or 16 sets of word accessible
EEPROM m₁~ M₁₆Equipped with 256k bytes (128k words)
Storage capacity. 8-bit commercially available
When using an EEPROM with a 64-kbit capacity of
As shown in FIG. 4, the EEPROM m
₁~ M₁₆May be configured.   In that case, one word in one of the two EEPROMs in the set
Lower 8 bits D of data₀~ D₇And on the other hand the top D₈
~ D₁₅And all other signals are applied in common
The connection may be made as follows.   EEPROM m above₁~ M₁₆Are the internal address buses A-BUS and
Address buffer via the internal data bus D-BUS
It is connected to the ABF and the data bus buffer DBF.
Address buffer ABF and data bus buffer on the board
The DBF is connected to the CPU (My Computer) via the system bus S-BUS.
Master board (hereinafter referred to as CPU)
Board, which complements the driving capability of the CPU.
You.   From the system bus S-BUS to the address buffer ABF
Captured address signal A₁~ A_{twenty three}A out of_Five~ A₁₇Of 13
Is the EEPROM m₁~ M₁₆Supplied to By this
To read and write data in word units.
You.   Address signal A taken into address buffer ABF₁
~ A_{twenty three}Out of A₁~ A₉And A₁₈~ A_{twenty three}Is a selection circuit
Is supplied to the decoder circuit DEC. Decode this
By the above EEPROM m₁~ M₁₆Select one of
Select signal CS for₁~ CS₁₆Is formed. Especially restricted
However, it will be explained in detail later in the decoder circuit DEC.
As shown in the figure, the end of the address space given to this memory board
Address setting that can set the head address arbitrarily
A circuit is provided.   The decoder circuit DEC has access to the memory board
Output from the CPU board to the system bus S-BUS
And the upper data stream captured by the control signal buffer CBF.
The trobe signal UDS, lower data strobe signal LDS and
Control signals ▲ ▼ and ▲ ▼ are supplied. This
As a result, these control signals and the address signal A₁~
A₉And A₁₈~ A_{twenty three}And the above selection signal CS₁~ CS₁₆
Is formed.   The above control signal IACK is currently being output from the CPU
3-bit funk indicating mode and cycle type
Decoding the application code on the CPU board
Is a signal formed by Control signal ▲ ▼
Is access to memory or access to I / O
Address signal on the CPU board.
It is generated by decoding the signal.   In addition, the control signal buffer CBF additionally has a CPU board.
Like 16MHz output on the system bus S-BUS from
Captures clock signal CLK and read / write control signal R / W
It is being rare.   Clock signal CLK taken into control signal buffer CBF
Is supplied to the frequency dividing circuit DVD and divided, for example, 625 μs
A clock signal φc having a cycle as shown in FIG.   The selection signal CS formed in the decoder circuit DEC₁
~ CS₁₆Is the above EEPROM m₁~ M₁₆Provided for
Read / write control circuit CNT₁~ CNT₁₆Each
Supplied. Read / write control circuit CNT₁~
CNT₁₆From the selection signal CSn and the system bus S-BUS
Read / write control incorporated in control signal buffer CBF
Each EEPROM m based on the control signal R / W and the clock signal φc.₁
~ M₁₆Write enable signal ▲ ▼ n or chip
Enable signal ▲ ▼ n and output enable ▲
Form n and output. EEPROM m₁~ M₁₆Are these
Control signals ▲ ▼ n, ▲ ▼ n, ▲ ▼ n and address
Signal A_Five~ A₁₇Is accessed with the supply of Light
When the enable signal ▲ ▼ n is at the high level,
16-bit data stored at the address
Is supplied to the data bus buffer DBF and the system bus S
-Output on BUS. On the other hand, the write enable signal ▲
▼ When n is at the low level, the system bus S
− 16-bit data bus buffer DBF
Data is EEPROM m₁~ M₁₆Write to the corresponding address in
I will.   Thus, in this embodiment, each EEPROM m₁~ M₁₆Against
Address is assigned in the manner shown in FIG. 6 (A).
Have been killed.   That is, AS₁~ AS₁₆The above each EEPROM m₁~ M₁₆
Address space of EEPROM m₁To the start address of
Is the first word 1 stored in EEPROM m_TwoFirst ad
The second word 2 is stored in the address. Like this
And EEPROM m₁₆When the 16th word 16 is stored in
The second word 17 is again EEPROM m₁Return to EEPROM m₁of
It is stored at the second address. After that, the first 16 words
In the same way as 1-16, the next 16 words 17-32 are EE
PROM m₁~ M₁₆Of addresses so that they are stored in order
Assignment has been made.   Moreover, in this embodiment, the EEPROM m₁~ M₁₆As an example
For example, an address like HN58064P-25 manufactured by Hitachi, Ltd.
And EEPROM with data latch function is used
I have.   In such an EEPROM with a latch function, each EEPROM m₁
~ M₁₆Address signal or data when
What is necessary is just to hold a signal for about 200 ns. However, one
The time required for writing data (8 bits) is 10 ms.   Therefore, each EEPROM m₁~ M₁₆Write one word data to
It takes about 10ms to insert. That is, the write enable signal
The signal ▲ ▼ needs to be held low for about 10 ms.
You. However, in the above embodiment, after 200 ns has elapsed,
Be moved to EEPROM access.   Therefore, EEPROM m₁Start writing from m_Two, m_Three, ‥
Proceed to ‥ and again EEPROM m₁When you return to the first access
It suffices that 10 ms have passed since the time of.   As a result, in the above embodiment, the EEPROM m₁~ M
₁₆Write all data with a margin for all
Can be. As a result, the RAM button as shown in FIG.
Access according to the same address assignment method as
Compared to the method of writing data to EEPROM
In the embodiment, writing data at 16 times speed
And be able to.   The number of EEPROMs on the memory board is limited to 16
Not more than 17 (2ⁿValue for each piece). Ma
Also, prepare multiple memory boards as described above, and
After writing to all EEPROMs on the board has completed one cycle,
If you move to the memory horde of
The time required for writing is shortened. FIG.
Shows the address assignment method when two memory boards are used.
You. Note that the memory board has a reset when the power is turned on.
A power-on reset circuit POR that generates a signal is provided.
ing. The reset signal RS generated here is
De-write control circuit CNT₁~ CNT₁₆Supplied to
The internal counter and latch circuit are reset.
Have been.   FIG. 2 shows the decoder circuit DEC in the above embodiment.
One configuration example is shown. Although not particularly limited, here
Uses up to 32 memory boards as in the above example
However, the same as the address allocation method shown in FIG.
Selection signal CS for accessing each EEPROM by allocation method₁~ CS
₁₆Is shown to be able to automatically form
You.   As shown in FIG. 7, the decoder circuit DEC of this embodiment has
8M words (16M bytes) corresponding to a 23-bit address
256k bytes in the CPU address space
Each memory board with a size of 128k words
Can be placed (assigned) at any position
Address setting means 1 is provided. This address
The setting means 1 sets the upper 6 bits of the address, that is, A18 to A
A switch consisting of six switches SW1 to SW6 corresponding to 23
Switch array 1a such as a pull-up switch and a pull-up resistor.
6 extras corresponding to anti-R1 to R6 and addresses A18 to A23
It is composed of exclusive OR gates G1 to G6. This
This allows each memory board in the CPU address space to be
Address area (memory space) can be set in units of 128k words
Position when using up to 32 memory boards.
Memory space occupied by all memory boards is 4M words
(8 Mbytes), 8 M words (16 Mbytes) of CPU space
Will account for half of the Remaining 4M words (8M bytes
G) is open for ROM and I / O. Figure 7
000000,040000, A00000, FC0000 are CPU address space
The start address of any memory board placed in
03FFFF, 07FFFF, A3FFFF, FFFFFF is the last address,
Each is shown in hexadecimal ("F" is decimal "15"
Hexadecimal equivalent to, "A" is 16 equivalent to decimal "10"
Hex).   Each switch SW in the switch array 1a₁~ SW₆One of
Terminal is commonly connected to the ground point, and the other terminal is
Each pull-up resistor R₁~ R₆Connected to power supply voltage Vcc
Have been.   Each switch SW₁~ SW₆Is set to the conductive state,
Exclusive OR Gate G₁~ G₆One input terminal of
Are fixed to the “0” level (ground potential). Therefore,
Crucial OR gate G₁~ G₆Is connected to the other input terminal.
Entered address A₁₈~ A_{twenty three}The next stage NAND gate
G₁₁~ G₁₅And inverter G₁₆To supply.   On the other hand, each switch SW₁~ SW₆Set to non-conducting state
And the corresponding exclusive OR gate G₁~ G₆One of
The input terminal is fixed at "1" level (power supply voltage Vcc).
Therefore, exclusive OR gate G₁~ G₆The inva
Address signal A₁₈~ A_{twenty three}Flip NA
ND gate G₁₁~ G₁₅And inverter G₁₆To supply. Entering
A of the address signals₁₈~ A_{twenty three}But switch array
All EXCLUSIVES when the settings match condition 1a
Shiv OR gate G₁~ G₆Becomes low level. Toes
Gate G₁~ G₆Constitutes a kind of address comparison circuit
I have.   This allows the switch array to be
By changing the setting of 1a, the same address
Signal A₁₈~ A_{twenty three}Is common to each memory board from the CPU board
Memory allocated to each memory board, even if supplied
Deco on the board only when space is accessed
The decoder circuit DEC is operated.   For example, if all the switches SW1 to SW6 are set to the conducting state,
The address space of the board is “0000” in hexadecimal.
The size is set to 256k bytes from 00 "to" 03FFFF ".
When the switches SW2 to SW6 are set to the conductive state,
The address space of the board is changed from "040000" to "07FFFF".
You. Table 4 shows the states of the switches SW6 to SW1 and the addresses A23 to A23.
18 and the relationship with the memory space.  Between 1 and 32 decoder circuits DECⁿAnd 2 (n
= 0,1, ‥‥ 6) memory boards.
And in each case the address as described above
To enable access using the assignment method,
Replacement means 2 is provided. This board switching means 2
5 switches for up to 32 boards_{twenty one}~ SW
_{twenty five}Switch array 2a consisting of
Up resistance R_{twenty one}~ R_{twenty five}And 5 NAND gates G each
₁₁~ G₁₅And OR gate G_{twenty one}~ G_{twenty five}Consists of And Sui
Switch_{twenty one}~ SW_{twenty five}Gate G corresponding to setting signal by₁₁; G
_{twenty one}~ G₁₅; G_{twenty five}Is applied to one of the input terminals.   Therefore, for example, if only one board is used,
Switch_{twenty one}~ SW_{twenty five}Are all set to a non-conductive state.
Then, OR gate G_{twenty one}~ G_{twenty five}One of the input terminals is
It is set to “1” level, and eventually all output signals are set to “1” level.
Fixed. As a result, the address conversion unit 3
All these signals are invalidated. Then, at this time
The signal of “1” level supplied from the switch array 2a
NAND gate G₁₁~ G₁₅All work as inverters
Is done. As a result, NAND gate G₁₁~ G₁₅Is the address ratio
Exclusive OR gate G for comparison₁~ G_FiveOutput
To the next stage, multi-input NAND gate G₄₀To supply.   If only one board is used, cut the board as described above.
OR gate G in exchange means 2_{twenty one}~ G_{twenty five}Output is set to “1”.
It is. Also, the address signal that has entered the decoder circuit is
A₁₈~ A_{twenty three}Is the address set in the address setting means 1.
Exclusive OR gate only if match
G₁~ G₆Are all set to low level.   As a result, the address assigned to this memory board
NAND gate G only when accessing the source space₄₀Input
Signals are all high level, output is low level
Change, this NAND gate G₄₀Like LS154 by the output of
The 4-bit decoder AD is activated.   This decoder AD has 16 EEPROMs on the board.
Address signal A corresponding to₁~ A_{twenty three}A out of₁~ A_Four4 bits
Is entered. Therefore, when there is only one board
Is the address A₁~ A_FourEEPROM on board only based on
 m₁~ M₁₆Selection signal CS for selecting one of₁~ CS₁₅But
Read-write formed at the coder AD
Control circuit CNT₁~ CNT₁₆Supplied to   On the other hand, if two boards are used,
1st switch SW in 2a_{twenty one}Is made conductive. Then,
Switch SW_{twenty one}NAND gate G connected to₁₁And OR gate G_{twenty one}
Is fixed at the “0” level.   Therefore, NAND gate G₁₁Output is fixed to high level
Exclusive OR gate G₁Output signal
To disable. OR gate G_{twenty one}Is the address translation of the previous stage
Multi-input NAND gate G without changing output signal from unit 3₄₀To
To tell.   However, the address conversion unit 3 includes the switch SW₃₁~ SW₃₅
Switch array 3a consisting of
Top resistance R₃₁~ R₃₅And the address signal A₁~ A_{twenty three}A out of_Five~ A
₉5 exclusive OR gates G connected₃₁~ G
₃₅It is composed of Gate G₃₁~ G₃₅The number of
G_{twenty one}~ G_{twenty five}Like the maximum number of boards used, "32"
Determined accordingly.   The switch array 3a in the address translator 3
A switch corresponding to the switch array 2a in the board switching means 2
Switches are selectively rendered conductive or non-conductive. Toes
The switch array 1a of the address setting means 1
Has the function of indicating the position of the
Thus, the switch array 3a of the address conversion unit 3 has a plurality of
Address A5 ~ input when the memory board is used
It has a function to convert A9. Specifically, address translation
In the case where address conversion is not performed, the section 3 shown in FIG.
The access target is on the same board as in words 16 and 17
Chip (EEPROM) continuous from AS16 to AS1
Address as shown in word 16 and word 17 in FIG.
Chip (EEPROM) AS16 on board with different access target
It has a function to convert to an address that moves from to AS17
You.   However, the addresses A5 to A9 are changed by the address conversion unit 3.
Bits to be replaced may vary depending on the number of boards
To be. For example, if the number of boards is two, address A5
When the number of boards is 4, addresses A5 and A6,
When the number of boards is 8, addresses A5 to A7 and the number of boards
Address A5 to A8 for 16 boards, address for 32 boards
Dresses A5 to A9 are eligible. Address A18-A22 is A1-A2
The relevant memory board in the CPU address space indicated by 3
Is a code indicating the address range of
Addresses A5 to A9 after the
EEPROM varies in size)
Can be considered as a code for specifying any of
You.   That is, the case where the number of boards used is two is described.
Then, the switch SW set to be conductive in the switch array 2a
_{twenty one}In response to the above, switch array 3a has two boards
Switch SW₃₁One is set to the conductive state, and the other is set to the conductive state.
Are left non-conductive. Then, the non-conductive switch
SW₃₁Exclusive OR gate G connected to₃₁Is the other
Address A that has entered the other input terminal_FiveAnd reverse
OR gate G_{twenty one}To supply. On the other hand, on other boards
Switch SW rendered conductive₃₁Ikusuru connected to
-OR gate G₃₁Is the input signal A_FiveTo the next OR
Gate G_{twenty one}To supply.   As a result, the address range is
The address space of two boards set identically
Accessed NAND gate G in board switching means 2₁₂~ G₁₅
When the output of the board is set to the high level, the NA on the two boards
ND gate G₄₀Is the above exclusive OR gate G₃₁Out of
One of them, that is, its output
The power is made low.   In the above embodiment, the multi-input NAND gate G₄₀,
G₁₁~ G₁₆And G_{twenty one}~ G_{twenty five}Control signal in addition to the output signal of
UDS, LDS, ▲ ▼, ▲ ▼ are entered
Output when all these signals go high.
Power goes low.   This allows each decoder AD on the two boards to be identical
Even if addresses A1 to A4 are supplied, according to address A5
Only the decoder on one of the boards is active
To the EEPROM on the activated board
One of the selection signals CS1 to SC16 corresponding to A1 to A4
The level is set to one level and one EEPROM is selected. The decoder
Select signals to EEPROM on boards that are not activated
The signals CS1 to CS16 are all set to the non-selection level.   Here, the address setting means 1 and the board switching means 2
Explain the relationship. Board switching when two boards are used
As described above in the means 2, the switch array 2a
Of the switches SW21 to SW25, only the switch SW21 is turned on. this
As a result, the NAND gate G11 of the board switching means 2 is addressed.
A signal corresponding to the address A18 of the
Will not be transmitted to the NAND gate G40 as
The state of address A18 and switch SW1 affect the decoder
No longer. As a result, the decoding range of the decoder (G40)
Enclosure, ie, the address range of the board is, for example, one
Is 000000 to 03FFFF, but double the size of 000000
~ 07FFFF.   On the other hand, on the address conversion unit 3 side,
Only G21 of OR gates G21 to G25 conducts switch SW21.
According to the setting, the signal of the gate G31 of the address conversion unit 3 is decoded.
To the coder (G40).
The state of switch SW31 now affects the decoder.
You. At this time, if the switch SW31 is non-conductive (off),
G31 one input goes high and the other input
Is inverted and input to the decoder. Ma
If the switch SW31 is conducting (ON), the gate G31
One input goes low and the other input
Input to the decoder as it is. In other words, two
The state of switch SW31 on the board to conduction and non-conduction
By doing so, one is selected for the same A5, the other is
The condition of non-selection can be given.   At this time, the switch array 2a of the board switching means 2
Of the switches SW21 to SW25 are non-conductive.
That the board switching means 2
G22 to G25 use the signal of the address conversion unit 3 as a decoder.
Set not to transmit to all NAND gates G40
Therefore, the addresses A6 to A9 and the status of switches SW32 to SW35 are
No effect on the coder.   As a result, switch SW31 of two boards is non-conductive.
The (Off) board decoder works in the right of FIG.
Indicated by rising hatching, 000000〜00001F, 000040〜00005F, 000080 to 00009F, 0000C0 ~ 0000DF, ...... 07FF00-07FF1F, 07FF40 ~ 07FF5F, 07FF80 ~ 07FF9F, 07FFC0 to 07FFDF (“C” is a decimal “12”, “D” is a decimal
(Equivalent to “13”).
You.   In addition, the data of the board where the switch SW31 is conductive (ON)
The operation of the coder is indicated by the hatching in the lower right of Fig. 8.
You 000020〜00003F, 000060〜00007F, 0000A0-0000BF, 0000E0-0000FF, ...... 07FF20 ~ 07FF3F, 07FF60 ~ 07FF7F, 07FFA0 ~ 07FFBF, 07FFE0 to 07FFFF (“B” is a decimal “11”, “E” is a decimal
An address range like "14") is obtained. like this
Address of the two memory boards every 16 words
These two memories will be assigned to each other.
If a continuous address within the address range of the board is
Then, for example, one of the menus follows the order shown in FIG.
Data transfer of words 1 to 16 to the memory board is completed.
Then the following words 17 to 32 are transferred to the other memory board.
Such access is performed.   If four boards are used, switch
B.Switches 2a and 3a, SW21 and SW22 and SW31 and SW32
To make similar settings. In addition, the number of boards is eight
Use the switches SW21 to SW23 and SW31 to SW33
When the number of boards is 16, switch SW21 ~
The setting may be made using SW24 and SW31 to SW34.   As an example, use four boards and change the start address to "A000
The setting method of each switch array when “00” is set is the first.
The results are shown in Tables 3 to 3 ("A" corresponds to decimal "10"). Was
Here, “○” indicates a conductive state, and “×” indicates a non-conductive state.
The state, “△” indicates that any may be used. Table 1
Table 2 and Table 2 show settings common to each board. Table 1
In, the switches SW1 and SW2 are marked with “△”
Changes the board when four memory boards are used.
In the means 2, the switches SW21 and SW22 are turned on.
One input of gate G11, G12 is fixed to low level
As a result, the switches SW1,
As a comparison result of the address signals A18 and A19 corresponding to SW2,
This is because the outputs of the gates G1 and G2 are invalidated. Toes
If multiple memory boards are used,
The switch array 1a
(SW1 to SW6) can be set to the same address.
Wear. Also, by setting the same address,
To make the address space of multiple memory boards the same
Address range of each board within the same address space
Are set so that they are alternately distributed by 16 words.   Table 2 shows the switches of the switch array 2a of the board switching means 2.
Switches SW21 and SW22 of the switches SW21 to SW25 to the conducting (ON) state.
Indicates setting. In this case, the board switcher
The NAND gates G11 and G12 of the stage 2 are the addresses of the address setting means 1.
Signals corresponding to the A18 and A19
Not be transmitted to the port G40, and addresses A18, A19
And the state of switches SW1 and SW2 do not affect the decoder.
Become. As a result, the decoding range of the decoder (G40)
The address range of the board is, for example, A000 for one board
What is 00 to A3FFFF is quadrupled as shown in FIG.
Of A00000 to AFFFFF.   On the other hand, on the address conversion unit 3 side,
Of the OR gates G21 to G25, G21 and G22 are switches SW21 and SW22.
The gates G31 and G32 of the address conversion unit 3
The signal is transmitted to the decoder (G40).
A5, A6 and the state of switches SW31, SW32 affect the decoder.
To give. At this time, switches SW31 and SW32 are non-conductive.
If it is off (off), one of the inputs of gates G31 and G32 is high
Level and invert the other input address A5, A6
And input it to the decoder. Also, switches SW31 and SW32
Is on (on), one of the inputs of gates G31 and G32 is
When it goes low, the other inputs, addresses A5 and A6,
The data is directly input to the decoder G40. In other words, four buttons
The state of switches SW31 and SW32 on the circuit
By setting it to any position, the same A5, A6
One board is selected, the other three boards are not selected
The condition of choice can be given.   At this time, the switch array 2a of the board switching means 2
Of the switches SW21 to SW25 are turned off.
That the board switching means 2
G23 to G25 use the signal of the address conversion unit 3 as a decoder.
Set not to transmit to all NAND gates G40
Therefore, the addresses A7 to A9 and the status of switches SW33 to SW35 are
No effect on the coder. Therefore, in Table 3,
Indicates that all of the switches SW31 to SW35 are non-conductive.
(X), but either conductive or non-conductive
May be.   As a result, the four boards are set with switches SW31 and SW32.
An address as shown in Table 5 below is input according to the fixed state
It will be activated on condition that   When switches SW31 and SW32 are set as shown in Table 5,
In this case, board 1 is valid when A5 = 0 and A6 = 0.
The address range is as shown in FIG. A00000 to A0001F, A00080 ~ A0009F, A00100 ~ A0011F, A00180 ~ A0019F, ...... AFFE00 ~ AFFE1F, AFFE80 ~ AFFE9F, AFFF00-AFFF1F, It is a range of skipping like AFFF80-AFFF9F.   Board 2 is valid when A5 = 1 and A6 = 0,
The address range is A00020 ~ A0003F, A000A0 ~ A000BF, A00120 ~ A0013F, A001A0 ~ A001BF, ...... AFFE20 ~ AFFE3F, AFFEA0 ~ AFFEBF, AFFF20 ~ AFFF3F, The range is like AFFFA0 to AFFFBF.   Board 3 is valid when A5 = 0 and A6 = 1,
The address range is A00040 to A0005F, A000C0 ~ A000DF, A00140 ~ A0015F, A001C0 ~ A001DF, ...... AFFE40 ~ AFFE5F, AFFEC0 ~ AFFEDF, AFFF40 ~ AFFF5F, The range is like AFFFC0 to AFFFDF.   Board 4 is valid when A5 = 1 and A6 = 1,
The address range is A00060 ~ A0007F, A000E0-A000FF, A00160 ~ A0017F, A001E0 ~ A001FF, ...... AFFE60 ~ AFFE7F, AFFEE0-AFFEFF, AFFF60 ~ AFFF7F, The range is like AFFFE0 to AFFFFF.   Each switch array 1a to 3a is set as shown in Tables 1 to 3.
In advance, address signals A1 to A2
When 3 is supplied, the decoder circuit, especially the address converter
6 (B) by the action of the switch 3 and the board switching section 2.
According to the same address allocation scheme as shown in
The selection signals CS1 to CS16 are formed dynamically and each of the EEPROMs m1 to m16
Access is going on.   As a result, the first word 1 is written to EEPROMm1.
Before the first 10 ms has elapsed, the next word 2, 3,
2, m3, ‥‥ are written one after another and used
Time required to write all data when there are four boards
Is significantly (1/64) shorter than the method shown in Fig. 5.
It is.   If the number of memory boards to be used is 8,
Of the switches SW21 to SW25 of the switching means 2, SW21, SW22, SW
Set 23 to ON, and set SW24 and SW25 to OFF. this
By the action of NAND gates G11, G12, and G13.
SW1 and address A18 of the address setting means 1 and SW2 and A1
9, SW3 and A20 do not affect the decoder G40. That
As a result, if the address range of the board is, for example, one,
What is 000000 to 03FFFF is 8 times larger than 000000 to
It becomes 1FFFFF.   On the other hand, on the address conversion unit 3 side,
Of the OR gates G21 to G25, G21 to G23 are switches SW21 to SW23.
Gates G31 to G33 of the address conversion unit 3 depending on the conduction setting of
Signal is transmitted to the decoder (G40).
A5 to A7 and the status of switches SW31 to SW33 affect the decoder.
It will affect you. At this time, switches SW31, SW32, SW
If 33 is non-conductive (off), one of gates G31, G32, G33
Address becomes high level and the other input is the address
A5, A6, and A7 are inverted and input to the decoder. Also, Sui
If the switches SW31, SW32, and SW33 are conducting (ON), the gate G31,
One input of G32, G33 becomes low level and the other input
Addresses A5, A6, and A7 are directly input to the decoder G40.
Let it. That is, the switches SW31 to SW33 on the eight boards
The state of the continuity or non-conduction
Any one board is selected for the same A5 to A7.
Select, the remaining seven boards must give the condition of non-selection.
Can be.   At this time, the switch array 2a of the board switching means 2
Of the switches SW21 to SW25 are non-conductive.
That the board switching means 2
G24 and G25 use the signal of the address conversion unit 3 as a decoder.
Set not to transmit to all NAND gates G40
Therefore, the addresses A8 and A9 and the status of switches SW34 and SW35 are
No longer affect the order.   As a result, eight boards are set with switches SW31 to SW33.
An address as shown in the following Table 6 is input according to the steady state.
It will be activated on condition that  If the number of memory boards to be used is 16,
SW21-SW24 of the switches SW21-SW25 of the mode switching means 2
Set to ON and SW25 to OFF. by this,
Address setting means 1 by the operation of NAND gates G11-G14
Switch SW1 and address A18, SW2 and A19, SW3 and A20, SW
4 and A21 have no effect on decoder G40. The result
As a result, the address range of the board is, for example, 00 for one board.
What is 0000 to 03FFFF is 000000 to 3F which is 16 times larger
It becomes FFFF.   On the other hand, on the address conversion unit 3 side,
Of the OR gates G21 to G25, G21 to G24 are switches SW21 to SW24.
Gates G31 to G34 of the address conversion unit 3 depending on the continuity setting of
Signal is transmitted to the decoder (G40).
A5 to A8 and the status of switches SW31 to SW34 affect the decoder.
It will affect you. At this time, switches SW31, SW32, SW
Gates G31, G32, G33, G if 33, SW34 are non-conductive (off)
One input of 34 goes high and is the other input
Addresses A5, A6, A7, A8 are inverted and input to the decoder.
You. Also, the switches SW31, SW32, SW33, and SW34 are turned on (off).
), One of the gates G31, G32, G33, G34
Address A5, A6, A7, A
8 is directly input to the decoder G40. In other words, 16
The state of switches SW31 to SW34 on the board
By setting to either, for the same A5 ~ A8
One of the boards is selected, the remaining 15 boards are non-
The condition of selection can be given.   At this time, the switch array 2a of the board switching means 2
Of the switches SW21 to SW25 are turned off.
The NAND gate G25 of the board switching means 2
Is a NAND gate serving as a decoder for the signal on the address conversion unit 3 side.
Port G40.
And the state of switch A9 and switch SW35 do not affect the decoder.
It becomes.   As a result, 16 boards are set with switches SW31 to SW34.
An address as shown in the following Table 7 is input according to the steady state.
It will be activated on condition that  If the number of memory boards to be used is 32,
Set all switches SW21 to SW25 of the mode switching means 2 to ON
I do. This allows the NAND gates G11-G15 to function.
The switch SW1 of the address setting means 1 and the address A18,
SW2 and A19, SW3 and A20, SW4 and A21, SW5 and A22 are decoder G4
No effect on 0. As a result, the address of the board
The range is, for example, 000000 to 03FFFF for one sheet.
It becomes 3200000 times of 000000-7FFFFF.   On the other hand, on the address conversion unit 3 side,
All of the OR gates G21 to G25 conduct the switches SW21 to SW25
The signals of the gates G31 to G35 of the address conversion unit 3 depending on the setting
To the decoder (G40), and the address A5
~ A9 and the state of switches SW31 ~ SW35 affect the decoder
I can get it. At this time, switches SW31 to SW35 are not
One of the corresponding gates G31 to G35 if off (off)
Address becomes high level and the other input is the address
A5 to A9 are inverted and input to the decoder. In addition, each sui
If the switches SW31 to SW35 are conducting (ON),
One of G31 to G35 becomes low level and the other input
Addresses A5 to A9 are directly input to the decoder G40.
Let In other words, the switches SW31 to SW35 on the 32 boards
By setting the state to either conductive or non-conductive,
Select one board for the same A5 to A9,
The other 31 boards can give the condition of non-selection
Wear. 32 buttons depending on the setting of switches SW31 to SW35
The address where the code is activated is 16 or more.
The description is omitted because it is the same.   Here, the interrelationship between the switch arrays 1a, 2a, 3a is organized.
Will be explained. First, the switching of the board switching means 2 is performed.
The setting state of the master array 2a is determined by the address of the address
Of the settings of switches A5 to A9 and switches SW31 to SW35
/ Disable control. Second, the switch of the board switching means 2
The setting state of the master array 2a is determined by the address of the address setting means 1.
Of the setting status of switches A17 to A22 and switches SW1 to SW5
Also controls invalidation. Table 8 shows the mutual relationship between the switch arrays 1a, 2a, and 3a.
Show the relationship. In Table 8, the column of the switch array 2a
"1" indicates a conductive state and "0" indicates a non-conductive state.
You. The "V" in the column of the switch arrays 1a and 3a is the switch.
“*” Indicates that the switch and address are valid,
Indicates that the address is invalid.  From Table 8, it can be seen that the addresses A18 to A22 and
Enable / disable of the setting status of switches SW1 to SW5 and
A5 to A9 of the address conversion unit 3 and switches SW31 to SW
The validity / invalidity of the 35 setting states means that the board switching means 2
Depending on the setting state of the switch array 2a, the reverse relationship (one
Is better when the other is disabled)
You.   The switch array 2a of the board switching means 2 is provided.
Depending on the fixed state, the input terminals TA0 to TA0 of the EEPROMs m1 to m16 are actually
Table 9 also shows the address signal (supply address) input to TA12.
It is changed as follows.   Next, FIG. 3 shows the data supplied from the decoder circuit DEC.
Select signal CSn and read / write control signal R / W, etc.
Based on the control signals ▲ ▼ n, ▲ for each EEPROMmn
Read / write control to form ▼ n, ▲ ▼ n
2 shows an example of a specific circuit configuration of the circuit CNTn.   This read / write control circuit CNTn
And a latch circuit LTH. Counter coun
T is such as 625 μs supplied from the frequency dividing circuit DVD.
Once every 10ms by counting clock signal φc
Each time a one-shot carry signal CRY is output
It is configured.   Carry signal CRY output from counter COUNT is NO
R gate G₅₁Through delay flip-flops etc.
It is supplied to the set terminal of the latch circuit LTH.   The latch circuit LTH outputs the carry CRY from the counter COUNT.
Each time it enters, it is set. And Invar
TA G₅₂Deco input to the clock terminal via
In synchronization with the fall of the selection signal CSn from the
At this time, the read / write system input to the data terminal is
Captures and holds the control signal R / W. In addition, the latch circuit LTH
Output is supplied to the above counter COUNT as a load signal
It is supposed to be.   Therefore, the read / write control signal R /
W is changed from high level to low level, then selected
When the signal CSn is changed from high level to low level,
Read / write control synchronized with falling of select signal CSn
The low level of the signal R / W is taken into the latch circuit LTH.
Then, the output Q of the latch circuit LTH changes from high level to low.
Level, and the output changes from low to high
Be changed.   By this output, "0" is displayed in the counter COUNT.
It is loaded and starts counting.
The signal CRY is output. This carry signal CRY
Switch LTH is set and output Q changes to high level
Is done. That is, the output Q of the latch circuit LTH is maintained for about 10 ms.
It is kept at low level. In this embodiment, the output Q
Changes the write enable signal to the corresponding EEPROM.
And holds the required write time of 10 ms.   The output Q of the latch circuit LTH is
Together with the control signal R / W, the NAND gate G₅₃Entered in
Output Q and read / write control signal R / W are both high.
NAND gate G only when level₅₃Output is low level
Is changed to This NAND gate G₅₃EEP corresponding to the output of
Supplied to ROM as out enable signal ▲ ▼ n
You. As a result, the out enable signal ▲ ▼ n becomes
High level when writing data, low level when reading
To be   On the other hand, the selection signal CSn is directly
Is supplied as a chip enable signal ▼ n.
The set terminal of the latch circuit LTH has a NOR gate
G₅₁From power-on reset circuit POR via
The signal RS is being input, and the
It is supposed to be.   The embodiment of the present invention has been described above.
Circuit DEC and read / write control circuit CNT implemented
It is not limited to the configuration of the example, and various modifications may be considered.
It is.   Further, each EEPROM m is provided on the memory board of the embodiment.₁
~ M₁₆Has a flag to indicate whether or not
You may do it. This flag is used by the CPU to write to the EEPROM.
Read before going to see if you can write
Can be Without such a flag, the CPU would write
If the EEPROM that was
May be waited (up to 10 ms), but a flag is set
This avoids the expected state of the CPU.
Can be. The above flag is output from the CPU board, for example.
Read using the control signal IOEN
Good.   In addition, the memory board has a parity
Can be configured to include a memory generation check circuit
It is. [effect] (1) RAM as a semiconductor memory constituting a memory board
I used EEPROM instead of
Data does not require battery backup
It can be maintained even after the power is turned off. This also allows the storage device
Can be improved. (2) RAM as a semiconductor memory that constitutes a memory board
Instead of using EEPROM, multiple EEPROMs
Data in byte or word units
Address assignment method that writes data sequentially.
Since it was adopted, write to one EEPROM
It is possible to move on to writing to the next EEPROM while
Operation reduces the time required to write data.
There is an effect that.   The invention made by the inventor above is based on the embodiment.
Although described specifically, the present invention is limited to the above embodiment.
It can be changed variously without departing from the gist
It goes without saying that it is capable. For example, in the above embodiment,
Is the address signal as the EEPROM that constitutes the memory board
Use a device with a built-in latch circuit to latch data signals.
Although the description has been given of the case where the
Configure the circuit that latches the signal with an external circuit
, An EEPROM without such a built-in latch circuit
It is also possible to use. [Applications]   In the above description, the invention mainly made by the inventor has been described.
Microcomputer, which is the application field behind
Applied to the memory board that composes the data system
However, the present invention is not limited to this.
System that has data that you want to save after
Can be used in general.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment when the present invention is applied to a memory board constituting a microcomputer system, and FIG. 2 is a circuit showing an example of a decoder circuit thereof. FIG. 3 is a circuit diagram showing an example of the read / write control circuit, FIG. 4 is a diagram showing a specific example of an EEPROM for storing data in word units, and FIG. FIG. 6A and FIG. 6B are explanatory diagrams showing an example of an address assignment system in a memory board according to the present invention. FIG. 7 is an address space map showing the relationship between the address space of the CPU and the address range of the memory board whose position is set by the address setting means. FIG. 8 shows a case where two memory boards are used.
4 is an address space map showing a relationship between a CPU address space and an address range of each memory board. FIG. 9 shows a case where four memory boards are used.
6 is an address space map showing a relationship between an address space of a CPU and an address range of the entire memory board and a detailed arrangement of an address range of each memory board. ABF: Address buffer, CBF: Control signal buffer,
DBF: Data bus buffer, DEC: Decoder circuit, CN
T _{1 to} CNT ₁₆ ...... Read / write control times, m _{1 to} m
₁₆ …… EEPROM, S-BUS …… System bus, A-BUS…
Internal address bus, D-BUS ... Internal data bus, 1 ...
... Address setting means, 2 ... Switching section (board switching means), 3 ... Address conversion section, 1a, 2a, 3a ... Memory array, DA ... Decoder, COUNT ... Counter, LTH ... Latch circuit.

Claims (1)

(57) [Claims] 2 ⁿ or 2 ⁿ (n is a positive integer) nonvolatile semiconductor memories each formed as a semiconductor integrated circuit on a semiconductor chip, and the plurality of nonvolatile semiconductor memories based on address signals supplied via a bus. A selection circuit for forming a signal for selecting one or a set of the semiconductor memories, and a write control signal provided for each or each of the plurality of nonvolatile semiconductor memories and supplied to the nonvolatile semiconductor memory And a control circuit for forming the control signal. The non-volatile storage device is composed of 2 ⁱ (i is a positive integer) memory boards each mounted with the control circuit. A latch circuit which captures and holds a read / write control signal supplied via a bus based on a change, and Timer means for measuring a time sufficient to write data to the storage element in the nonvolatile storage device based on the change of the above, and the signal held in the latch circuit is stored in the corresponding nonvolatile semiconductor memory in the corresponding nonvolatile semiconductor memory. The latch circuit is configured to be supplied as a write control signal and to reset the latch circuit when the timer measures a time sufficient to write data into the storage element. When a continuous address is supplied by decoding the number (n) of bits corresponding to the number or the number of sets (2 ⁿ ) of nonvolatile semiconductor memories from the lower side of the supplied address signal, A decoder for sequentially forming and outputting signals for sequentially selecting the nonvolatile semiconductor memory, and an address space allocated to the memory board are set. Setting means for comparing the upper few bits of the address signal supplied via the bus with the address set in the address setting means, and the non-volatility of the supplied address signal. When the i-bit signal on the lower side of the address supplied to the memory matches a state set for each memory board and the address comparison means detects a match, the decoder on the memory board is enabled. Board activation means, wherein when 2 ⁿ or 2 ⁿ sets of non-volatile semiconductor memories on one memory board are accessed once when continuous addresses are supplied, access to another memory board is performed. A non-volatile memory device configured to perform switching.