JP3097680B2 - ATM switch and control method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM switch for switching information in units of cells or an ATM switch in an ATM cross-connect and a control method therefor.

[0002]

2. Description of the Related Art In an ATM switch, an ATM cell is routed based on a routing tag assigned to the ATM cell. ATM cells are recommended by International Telegraph and Telephone Consultative Committee Recommendation I.
As specified in 432, the size is 53 bytes, and inside the switch, a routing tag is added to convert the size into an in-device ATM cell having a size of 54 to 64 bytes. The repetition period of the ATM cell is 150 Mb /
Approximately 44 cells per 125 μs per second. For example, 125
Approximately 2800 cells per μs (equivalent to 150 Mb / s x 64 cells)
The switching capacity of an ATM switch that processes
Gb / s. Conventionally, when configuring such a large-capacity switch, unit switches achievable in a one-chip LSI are two-dimensionally combined. For example, "Kaoi,
Other: Development of ATM switch LSI for broadband ISDN, 1
990 IEICE Spring National Convention, B-443,
(March 18, 1990) ", one chip of L
A switch having a size of 8 × 8 in terms of 150 Mb / s is configured in the SI, and a switch having a size of 64 × 64 in terms of 150 Mb / s is configured by combining the switches in a two-dimensional form with 64 chips.

[0003]

SUMMARY OF THE INVENTION The prior art AT
In the M-switch, the cells are routed based on the routing tag given to the ATM cell, so that the ATM cells including the routing tag are always switched integrally. For this reason, the switching capacity of a unit ATM switch is limited by the scale of switch hardware that can be mounted on a one-chip LSI and the capacity of signals that can be input and output to and from a one-chip LSI. As described above, the unit switches must be two-dimensionally combined. For this reason, there is a problem that the hardware scale increases in proportion to the square of the switch capacity.

An object of the present invention is to provide an ATM switch having a small hardware scale even when the switch capacity is large.

[0005]

In order to solve the above-mentioned problems, according to the present invention, an ATM switch is divided into N (N is an integer of 2 or more) partial cells of an ATM cell. A cell dividing circuit for providing a routing tag;
And N partial cell switches that independently route each of the partial cells based on the routing tag.

[0006]

The cell dividing circuit divides an ATM cell into N partial cells and sends each partial cell to N partial cell switches. Each partial cell switch routes partial cells from a plurality of cell division circuits. That is, the first
, The first partial cell from each cell dividing circuit is routed, the second partial cell switch routes the second partial cell from each cell dividing circuit, and so on. In the cell switch, the corresponding partial cell is routed.

[0007] Since routing is performed independently for each partial cell, the size of the switch hardware that can be mounted on a one-chip LSI and the capacity of signals that can be input and output to and from a one-chip LSI are limited by the unit. It is not the switching capacity of the ATM switch but the capacity of the unit partial cell switch. Therefore, the total switching capacity of the ATM switch is a value obtained by multiplying the capacity of the unit partial cell switch by the number of cell divisions. By increasing the number of cell divisions, it becomes possible to configure a very large capacity unit ATM switch.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment will be described below with reference to FIG. The ATM switch shown in FIG.
Gb / s input highways 1-8, cell division circuits 21-2
8, partial cell switches 30 to 37, and 2.4 Gb / s output highways 71 to 78. Cell division circuit 2
, 28, respectively, are routing tag assigning circuits 210-217, 220-227,.
87.

Next, the operation of the first embodiment will be described.
From the 2.4 Gb / s incoming highways 1 to 8, an ATM cell having a length of 56 bytes as shown in FIG.
It is input in the form of 4-bit parallel × 7 rows. The ATM cell is composed of an 8-byte cell header and a 48-byte cell information section. In the cell division circuits 21 to 28, 4
The cells of 0 Mb / s × 64 bits parallel × 7 rows are divided for every 8 bits parallel, and the same routing tag is assigned to each of them, and the eight partial cells 150 to 1 of the format as shown in FIG.
Convert to 57. Each partial cell is sent to a different partial cell switch. For example, the 0th partial cell 15 of the output of the routing applying circuit 210 in the cell dividing circuit 21
0 indicates that the partial cell switch 30 is connected to the routing application circuit 21.
1 of the first partial cell 151 is the partial cell switch 31
Sent to The partial cell switch 30 receives the 0th partial cell from each of the cell division circuits 21 to 28 and
The switching of the zeroth partial cell is executed based on the routing tag of the partial cell. In the same manner, the partial cell switches 31 to 37 perform switching of the first partial cell to the seventh partial cell, respectively. Since the same routing tag is assigned to each partial cell divided from one cell, all the partial cell switches perform the same switching operation as long as the circuit operates normally. Therefore, each partial cell divided from one cell is simultaneously output to the 2.4 Gb / s output highway.

Next, a second embodiment will be described with reference to FIG. The ATM switch shown in FIG. 4 includes 2.4 Gb / s input highways 1 to 8 and error correction code encoders 11 to 1.
8, cell division circuits 21 to 28, partial cell switch 30 to
39, error correction code decoding circuits 51 to 58, error counters 61 to 68, 2.4 Gb / s output highways 71 to 7
And 8. Cell dividing circuits 21, 22, ..., 2
8 are routing tag assigning circuits 210 to 21 respectively.
9, 220 to 229,..., 280 to 289.

Next, the operation of the second embodiment will be described.
The ATM cells having a length of 56 bytes shown in FIG. 2 are input from the 2.4 Gb / s input highways 1 to 8 in a format of 40 Mb / s × 64 bits parallel × 7 rows. In the error correction code encoding circuits 51 to 58, 64 bits arriving at the same time are
Error correction coding is performed using a 1-byte error correction Reed-Solomon code on the Galois field GF (2 ⁸ ). The error correction code is a shortened Reed-Solomon code generated by a generator polynomial, G (X) = (X + α) (X + α ² ). The code length is 10 bytes, the number of information symbols is 8 bytes, and the number of check symbols is 2
Bytes, minimum distance is 3 bytes. Where α is GF
It is a primitive element of ^{(2 8).} Error correction code encoding circuit 5
In steps 1 to 58, a 2-byte check symbol is generated based on the generator polynomial, and a highway cell is converted to 40 Mb / s × 8.
0-bit parallel × 7 rows format, cell dividing circuits 21 to 2
Send to 8. In the cell division circuits 21 to 28, 40 Mb / s
The cells of × 80 bits parallel × 7 rows are divided for every 8 bits parallel, and the same routing tag is assigned to each of them to convert them into ten partial cells 160 to 169 in the format as shown in FIG. The 0th partial cell 160 to the 7th partial cell 167
An ATM cell is obtained by adding a routing tag to a divided ATM cell, and includes an eighth partial cell 168 to a ninth partial cell 169.
Is obtained by adding a routing tag to the check symbol of the error correction code. Each partial cell is sent to a different partial cell switch. For example, the 0th partial cell 160 of the output of the routing applying circuit 210 in the cell dividing circuit 21
Is a routing cell providing circuit 211 for the partial cell switch 30.
Is output to the partial cell switch 31. In the partial cell switch 30, the cell division circuit 2
The 0th partial cell is input from each of the first to 28th cells, the 0th partial cell is switched based on the routing tag of each 0th partial cell, and the 0th partial cell is sent to the error correction code decoding circuit corresponding to the output highway. Send the cell. In a similar manner, in the partial cell switches 31 to 39,
Switching of the first to ninth partial cells is performed.
Since the same routing tag is assigned to each partial cell divided from one cell, all the partial cell switches perform the same switching operation as long as the circuit operates normally. Therefore, each partial cell divided from one cell arrives at the error correction code decoding circuit at the same time. In the error correction code decoding circuit 51, the 0th to 9th partial cells are input from the partial cell switches 30 to 39, respectively, and cells of 40 Mb / s × 80 bits parallel × 7 rows are reproduced. 1-byte error correction decoding of Reed-Solomon code is performed. As long as all the partial cell switches are operating normally, each partial cell divided from one cell is input at the same time, and no error occurs, so that no error correction is actually performed. However, for example, if an error occurs in any one of the 10 partial cells divided from one cell, the other 9 partial cells are correctly corrected by the error correction code decoding circuit 51.
However, there is a possibility that only the partial cell in which an error has occurred is not correctly routed and does not arrive at the correct error correction code decoding circuit at the correct time. Since the error correction code of the present embodiment has the ability to correct a one-byte error, in this case, by decoding the error correction code, the contents of one partial cell that did not arrive from nine correct partial cells are changed. Will be restored. Partial cell switch 30 ~
39 has a first-in first-out buffer for temporarily storing partial cells when a partial cell collision occurs. For this reason, once a malfunction due to a routing tag error occurs, the order of the partial cells in the queue in the first-in first-out buffer of the partial cell switch in which the malfunction has occurred becomes the order of the queues of the other partial cell switches. The order of the partial cells may be different. If the order of the partial cells in the queue is different from the others, the arrival times of the relevant partial cells to the error correction code decoding circuit 51 will be different from the arrival times of the other partial cells continuously. The error correction decoding circuit 51 uses the nine arriving partial cells to correctly read the contents of one partial cell that does not arrive correctly.
Continue to restore by byte error correction. The difference in the order of the partial cells of the queue in the first-in first-out buffer of the partial cell switch is that the queue length in the first-in first-out buffer is 0.
It is resolved when it becomes. However, if the queue length is 0
Assuming that the difference in the order of the partial cells in the queue continues for a long time, the error counter 61
The number of error corrections per unit time is counted, and when the state where the number of error corrections exceeds a specific value continues for a specific time, the queue of the partial cell switch is reset. If the partial cell switch has a buffer corresponding to the output highway, only the buffer of the corresponding output highway is reset.
Error correction decoding circuits 52 to 58 and error counter 62
The operations of .about.68 are also performed by the error correction decoding circuit 51 described above.
And the operation of the error counter 61.

In the second embodiment, an error correction code is used to prevent the propagation of an error caused by a malfunction of a partial cell switch. Therefore, there is an effect that ATM cells are not easily discarded even when a malfunction of a partial cell switch occurs. .

Next, a third embodiment will be described with reference to FIG. The ATM switch shown in FIG. 6 includes 2.4 Gb / s input highways 1 to 8, parity addition circuits 81 to 88, cell division circuits 21 to 28, partial cell switches 30 to 38, parity check circuits 101 to 108, and an error counter 61.
-68, 2.4 Gb / s output highways 71-78. The cell dividing circuits 21, 22,..., 28 are routing tag assigning circuits 210 to 218, 22 respectively.
.., 280-288. Next, the operation of the third embodiment will be described. 2.4 Gb /
ATM cells having a length of 56 bytes shown in FIG. 2 are input from the s-input highways 1 to 8 in a format of 40 Mb / s × 64 bits parallel × 7 rows. The parity adding circuits 81 to 88 add 8 parity bits in parallel to 64 bits that arrive at the same time. The n-th bit (n = 1 to 8) of the parity byte is an odd parity for the n-th bit of each byte of the corresponding row of the ATM cell. In the cell division circuits 21 to 28, 40M with an odd parity is added.
The cells of b / s × 72 bits parallel × 7 rows are divided every 8 bits parallel, the same routing tag is assigned to each, and the cells are converted into nine partial cells 170 to 178 in the format as shown in FIG. . 0th partial cell 170 to seventh partial cell 177
Is obtained by adding a routing tag to a divided ATM cell, and the eighth partial cell 178 is obtained by adding a routing tag to a parity byte. As in the first and second embodiments, each partial cell is sent to a different partial cell switch.
Switching of the 0th partial cell to the 8th partial cell is performed, and the partial cells are switched to the parity check circuits 101 to 1 respectively.
Send to 08. Since the same routing tag is assigned to each partial cell divided from one cell, as long as all partial cell switches are operating normally, each partial cell divided from one cell is simultaneously processed. The data is input to the parity check circuit 101. However, as described in the second embodiment, assuming a malfunction of the partial cell switch, the error counter 61 counts the number of error detections per unit time in the parity check circuit 101, and this count is equal to or larger than a specific value. If this state continues for a specific time, the queue of the partial cell switch is reset. If the partial cell switch has a buffer corresponding to the output highway, only the buffer of the corresponding output highway is reset. The operations of the parity check circuits 102 to 108 and the error counters 62 to 68 are the same as the operations of the parity check circuit 101 and the error counter 61 described above.

In the third embodiment, since the erroneous operation of the partial cell switch is detected by using the parity, it is possible to quickly return to the erroneous operation of the partial cell switch.

Next, a fourth embodiment will be described with reference to FIG. The ATM switch shown in FIG. 8 includes 2.4 Gb / s input highways 1 to 8, cell division circuits 41 to 48, partial cell switches 30 to 37, and sequence number check circuits 131 to 13.
8, error counters 61 to 68, and 2.4 Gb / s output highways 71 to 78. Cell division circuit 2
,..., 28 are routing tag / sequence number assigning circuits 310 to 318, 320 to 328,.
80 to 388. Next, the operation of the fourth embodiment will be described. From the 2.4 Gb / s incoming highways 1 to 8, the 56-byte ATM cell shown in FIG.
/ S × 64 bits parallel × 7 rows. The cell dividing circuits 41 to 48 divide the cells of 40 Mb / s × 64 bits parallel × 7 rows for every 8 bits parallel, assign the same routing tag and the same sequence number to each of them, and apply the format shown in FIG. This is converted into eight partial cells 180 to 187. The sequence number is from 0 to 255, 25
It is provided so as to increase cyclically in a cycle of 6 cells.
As in the first to third embodiments, each partial cell is sent to a different partial cell switch, and
37, the switching of the 0th partial cell to the 7th partial cell is performed, respectively.
138. The sequence number check circuit 131 checks whether or not the sequence numbers of the partial cells arriving at the same time are equal. Since the same routing tag is assigned to each partial cell divided from one cell, as long as all partial cell switches are operating normally, each partial cell divided from one cell is simultaneously processed. The sequence numbers are input to the sequence number check circuit 131, and the sequence numbers are equal to each other. However, as described in the second embodiment, assuming a malfunction of the partial cell switch, the error counter 61 counts the number of inconsistencies of the sequence numbers per unit time in the sequence number check circuit 131, and this is specified. If the state of exceeding the value continues for a specific time, the queue of the partial cell switch is reset. If the partial cell switch has a buffer corresponding to the output highway, only the buffer of the corresponding output highway is reset. Sequence number check circuit 1
The operations of 32-138 and error counters 62-68 are also
The operation is the same as that of the sequence number check circuit 131 and the error counter 61 described above.

In the fourth embodiment, since the malfunction of the partial cell switch is detected by using the sequence number, quick recovery is possible even when the partial cell switch malfunctions.

[0017]

In general, the hardware scale of a large capacity switch increases in proportion to the square of the signal transfer capacity. In the ATM switch of the present invention, the cells are divided into partial cells and independently routed. Therefore, the signal transfer capacity of each switch for routing the partial cells is a value obtained by dividing the total switch capacity by the number of divided cells. Becomes Therefore, the hardware scale of one partial cell switch is about (1 / division number) of the hardware scale of a switch that does not perform cell division.
² ) Therefore, the total hardware scale of the ATM switch according to the present invention is about (1 / the number of divisions) times the hardware scale of the switch that does not perform cell division. in this way,
According to the present invention, even when the switch capacity is large, the ATM switch can be configured with a small hardware scale.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a configuration diagram of an ATM cell used in an embodiment of the present invention.

FIG. 3 is a configuration diagram of a partial cell used in the first embodiment of the present invention.

FIG. 4 is a block diagram of a second embodiment of the present invention.

FIG. 5 is a configuration diagram of a partial cell used in a second embodiment of the present invention.

FIG. 6 is a block diagram of a third embodiment of the present invention.

FIG. 7 is a configuration diagram of a partial cell used in a third embodiment of the present invention.

FIG. 8 is a block diagram of a fourth embodiment of the present invention.

FIG. 9 is a configuration diagram of a partial cell used in a fourth embodiment of the present invention.

[Explanation of symbols]

 1-8: 2.4 Gb / s input highway, 21-28: cell dividing circuit, 30-39: partial cell switch, 71-78: 2.4 Gb / s output highway, 210-289: routing tag adding circuit, 11 ... 18: Error correction code encoding circuit, 51-58 ... Error correction code decoding circuit, 61-68 ... Error counter, 81-88 ... Parity addition circuit, 101-108 ... Parity check circuit, 41-48 ... Cell division circuit 131 to 138: sequence number check circuit; 310 to 388: routing tag / sequence number assignment circuit.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Akihiro Hiroshi 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi, Ltd. Totsuka Plant (56) References JP-A-2-67045 (JP, A) (58) ) Surveyed field (Int.Cl. ⁷ , DB name) H04L 12/28 H04L 12/56

Claims (10)

(57) [Claims] An ATM input from one of a plurality of input lines.
An ATM switch for transferring a cell to one of a plurality of output lines, comprising: an error correction code encoding circuit for adding a check symbol of an error correction code using the ATM cell as an information symbol to the ATM cell; The information part of the added ATM cell is N
A cell dividing circuit for dividing the check symbol part into M partial cells and assigning the same routing tag to each partial cell, and dividing the (N + M) partial cells based on the routing tag An ATM switch comprising: (N + M) partial cell switches that are independently routed; and an error correction code decoding circuit that receives the (N + M) partial cells after routing and performs error correction. 2. When the partial cell has a size of b bits, the error correction code is j = (b / m) bits (m is b
(1) is a code for performing error correction in a symbol unit with one symbol as a symbol.
The ATM switch according to the item. 3. A code for performing error correction in a symbol unit using the j bits as one symbol is a Galois field GF (2 **).
3. The ATM switch according to claim 2, wherein the ATM switch has a code above j). 4. The ATM switch according to claim 3, wherein the code on the Galois field GF (2 ** j) is a Reed-Solomon code. 5. An ATM input from one of a plurality of input lines.
An ATM switch for transferring a cell to one of a plurality of output lines, comprising: an error detection code encoding circuit for adding a check symbol of an error detection code using the ATM cell as an information symbol to the ATM cell; The information part of the added ATM cell is N
A cell dividing circuit for dividing the check symbol part into M partial cells and assigning the same routing tag to each partial cell, and dividing the (N + M) partial cells based on the routing tag An ATM switch comprising: (N + M) partial cell switches that are independently routed; and an error detection circuit that receives the (N + M) partial cells after routing and detects an error. 6. The ATM switch according to claim 5, wherein said error detection code is a parity check code. . 7. An ATM input from one of a plurality of input lines.
An ATM switch for transferring a cell to one of a plurality of output lines, comprising: a cell dividing circuit for dividing the ATM cell into N partial cells and assigning the same routing tag to each partial cell;
A circuit for assigning the same code to the partial cells, N switches for independently routing the N partial cells based on the routing tag, and receiving the N partial cells after routing, An ATM switch comprising: a coincidence detecting circuit for detecting coincidence of codes. 8. An ATM input from one of a plurality of input lines.
An ATM switch control method for transferring a cell to one of a plurality of output lines, comprising: an error correction code encoding circuit for adding a check symbol of an error correction code using the ATM cell as an information symbol to the ATM cell; , The information part of the ATM cell to which the check symbol is added is N
A cell dividing circuit for dividing the check symbol part into M partial cells and assigning the same routing tag to each partial cell, and dividing the (N + M) partial cells based on the routing tag (N + M) partial cell switches that are independently routed, and an error correction code decoding circuit that receives the (N + M) partial cells after the routing and performs error correction. An ATM characterized by resetting the (N + M) partial cell switches when an error is corrected or detected at a frequency higher than a specific frequency.
How to control the switch. 9. An ATM input from one of a plurality of input lines.
A method for controlling an ATM switch for transferring a cell to one of a plurality of output lines, comprising: an error detection code encoding circuit for adding a check symbol of an error detection code using the ATM cell as an information symbol to the ATM cell; , The information part of the ATM cell to which the check symbol is added is N
A cell dividing circuit for dividing the check symbol part into M partial cells and assigning the same routing tag to each partial cell, and dividing the (N + M) partial cells based on the routing tag (N + M) partial cell switches that are independently routed, and an error detection circuit that receives the (N + M) partial cells after the routing and performs error detection, wherein the error detection circuit has a frequency equal to or higher than a specific frequency. A method for controlling an ATM switch, comprising resetting the (N + M) partial cell switches upon detecting an error. 10. An AT input from one of a plurality of input lines.
A method of controlling an ATM switch for transferring an M cell to one of a plurality of output lines, comprising: a cell division circuit that divides the ATM cell into N partial cells and assigns the same routing tag to each partial cell; The N
A circuit for assigning the same code to the partial cells, N switches for independently routing the N partial cells based on the routing tag, and receiving the N partial cells after routing, A coincidence detection circuit for detecting code coincidence, wherein the coincidence detection circuit resets the N partial cell switches when detecting a code mismatch at a frequency equal to or higher than a specific frequency. .