JP3096763U - Anti-signal interference ribbon for integrated circuits - Google Patents

Abstract

(57) [Summary] (with correction) [Problem] To be able to lay out according to the same standard as a local circuit in an integrated circuit, adjust the length according to the required area, and improve the anti-signal interference effect in a unit area. A signal interference ribbon is provided. A Vcc metal ribbon and a Vcc metal ribbon electrically connected to a complementary metal oxide semiconductor device having a PNP composition, respectively.
An ND metal ribbon 60 ', the PNP structure creating a deep N-well layer 80 on the P-base 70, an N-well layer 90 thereon, and a P + layer 91' and an N- layer. 91, a dielectric layer 92 is formed, and a contact hole is formed in the N- layer to electrically connect the metal layers 50, 50 'and the deep N well layer to form a positive voltage ribbon.
Forming a contact hole in the + layer to electrically connect to the metal layer, connecting the contact hole to the Vcc metal ribbon,
A source and a drain are formed by connecting the contact hole and the Vcc metal ribbon in the N− layer, and the GND metal layer is electrically connected to a lower dielectric layer to form a gate.

Description

[Detailed description of the device]

[0001]

[Technical field to which the device belongs]

The present invention relates to an anti-signal interference ribbon, and in particular, it is installed around a local circuit inside an integrated circuit. The anti-signal interference ribbon that prevents electromagnetic waves from entering and leaking to the outside. To do.

[0002]

[Prior art]

Due to the progress of science and technology, the products used in daily life have an increasingly precise structure. Has become. More precise design is also required for integrated circuits. Collection The structure of the product circuit is laid out based on the layout standard of the electronic circuit. However In an electronic circuit, noise is always generated by mutual interference. Especially integrated circuits To reduce this signal interference to a minimum by Is an extremely important issue.

[0003] Traditional methods for reducing signal interference include housing shields and gap seals. It is isolated from the interference of noise from the outside by combining with the field. However, such a method can completely isolate noise interference from the outside. Can not. Also, conventional integrated circuits are preferred for internal structure design. The measures and the structure are not designed. An integrated circuit is an internal circuit It is getting more and more dense. The noise generated by the circuit is Flow greatly affects the electrical characteristics, stability, or quality of integrated circuits. give. Therefore, effective improvement measures are desired.

[0004]

[Problems to be solved by the device]

This device can be laid out with the same standard as the local circuit inside the integrated circuit. In the integrated circuit, the length is adjusted according to the area required for anti-signal interference of the local circuit. The anti-signal interference ribbon that can enhance the anti-signal interference effect in a unit area of The task is to serve.

[0005] Also, the invention is to match the integrated circuit of complementary thin film metal oxide transistor. It is an object of the present invention to provide an anti-signal interference ribbon that can be produced and has high industrial utility value.

[0006]

[Means for Solving the Problems]

Therefore, as a result of earnest studies by the present inventor in view of the drawbacks of the conventional technique, V Vcc metal ribbon electrically connected to cc positive voltage and GND grounded And a metal ribbon, each metal ribbon having a PNP composition of a complementary metal acid. Focused on solving problems with a structure that is electrically connected to a chemical film semiconductor element Then, the present invention has been completed based on such knowledge.

[0007] That is, the PNP structure produces a deep N-well layer on the P-base, An N well layer is formed on the N well layer, and a P + layer, an N- layer, and an N well layer are formed on the N well layer. And a dielectric layer and a contact hole at the position of the N-layer, The positive voltage ribbon is formed by electrically connecting the metal layer and the deep N-well layer. , Separately forming a contact hole at the position of the P + layer to electrically connect to the metal layer, Further, the contact hole and the Vcc metal ribbon are electrically connected to each other, and the N-layer is By electrically connecting the contact hole to the Vcc metal ribbon. And a drain and the GND metal layer is electrically connected to the underlying dielectric layer. Form a hood. The problem of the present invention is solved by using such a PNP structure. A determined anti-signal interference ribbon is obtained.

[0008] The present invention will be specifically described below. The signal interference ribbon against an integrated circuit according to claim 1, is a circuit surrounding a local circuit in the integrated circuit. It is an anti-signal interference ribbon of an integrated circuit installed in the enclosure, which is electrically connected to Vcc plus voltage. Including a Vcc metal ribbon electrically connected to each other and a GND metal ribbon grounded to GND And each metal ribbon is electrically connected to the complementary metal oxide semiconductor element of PNP composition. The PNP structure has a deep N-well layer on the P-base. Forming a N well layer on the deep N well layer, and forming a P + layer on the N well layer And an N-layer and a dielectric layer are formed, and a contact hole is formed at the position of the N-layer. To form a positive electrode by electrically connecting the metal layer and the deep N-well layer. A pressure ribbon is formed, and a contact hole is separately formed at the position of the P + layer to form a metal layer. Electrically connects the contact hole to the Vcc metal ribbon. And electrically connect the contact hole and the Vcc metal ribbon in the N− layer. Thereby forming a source and a drain, and the GND metal layer is electrically connected to the underlying dielectric layer. The gates are formed by connecting with each other.

[0009] The anti-signal interference ribbon according to claim 2 is the positive voltage ribbon according to claim 1. , N well layer and a deep N well layer.

[0010]

[Embodiment of device]

This invention is provided around a local circuit inside an integrated circuit, and allows electromagnetic waves to travel from the outside. It provides an anti-signal interference ribbon to prevent leakage and leakage to the outside. Vcc metal ribbon electrically connected to the lath voltage and GND metal ribbon grounded to GND. And a metal ribbon each of which has a PNP composition and is a complementary metal oxide film half. It is configured by being electrically connected to the conductor element. In order to detail the structure and characteristics of such an anti-signal interference ribbon, specific examples will be given. , Will be described below with reference to the drawings.

[0011]

【Example】

The mode of use of the anti-signal interference ribbon according to the present invention is disclosed in FIG. According to the drawing The anti-signal interference ribbon (C) surrounds the local circuit (B) inside the integrated circuit (A). Is laid out. That is, the local circuit (B) is connected to the anti-signal interference ribbon (C). Therefore, it is protected. Further, the anti-signal interference ribbon (C) is a local part inside the integrated circuit (A). It is laid out according to the same standard as the circuit (B).

[0012] FIG. 2 is a plan view of an anti-signal interference ribbon (C) according to the present invention, and FIG. Fig. 4 is an exploded view, and Fig. 4 is a partially enlarged view. According to the drawing, the anti-signal interference ribbon (C) A number of PNP structures (10) and a plurality of dielectric layers (ie Po1y 1ayer) layers (92) , P + layer (91 '), N- layer (91), and a plurality of metal layers (50) (50'). , Vcc metal ribbon (60), GND metal ribbon (60 '), and a plurality of cores. Contact holes (911) (911 ') (921) (61) (61'). And forming a deep N-well layer (80) on the P-base (70), Forming an N well layer (90) on the N well layer (80), and further forming the N well layer (90) (90) is a positive value P + layer (91 '), a negative value N- layer (91), and And the dielectric layer (92) are formed, and at the negative N-layer (91) position, The contact hole (911) is formed, and the metal layer (50) and the deep N well layer are formed. (80) is electrically connected.

[0013] In addition, a contact hole (911 ') is formed at the position of the positive P + layer (91'). Formed and electrically connected to the metal layer (50). Further contact holes (61 ) And the Vcc metal ribbon (60) are electrically connected.

[0014] The Vcc metal ribbon (60) is connected to the source (S) by applying a positive voltage. ) And a drain (D) are formed.

[0015] A contact hole (921) is formed at the position of the dielectric layer (92) to form a metal layer. (50 ') electrically connected. Furthermore, contact hole (61 ') and GND metal The ribbon (60 ') is electrically connected to form a GND ground gate (G). It

[0016] As disclosed in FIG. 5, the Vcc metal ribbon (60) and the GND metal ribbon (60 ′) Are electrically connected to the anode lead and cathode lead of the integrated circuit power supply, respectively. The PNP structure (10), a plus P + layer (91 '), and a minus The value N-layer (91) provides the required driving voltage. Also, Vcc metal ribbon The bottom surface of (60) has a plurality of contact holes (61) and a metal layer (50). It is electrically connected and transmits the positive voltage supplied from the power source to the metal layer (50). .

[0017] Also, a plurality of contact holes (61 ') are formed on the bottom surface of the GND metal ribbon (60'). ) Is formed to electrically connect to another metal layer (50 ') and is supplied from a power source. The voltage of the eggplant is transmitted to the metal layer (50 ') and thus supplied from the anode and cathode of the power source. Of the applied voltage to the metal layer (50) and the metal layer (50 ') respectively. Therefore, the PNP structure (10), the P + layer (91 ') having a plus value, and the minus value The value N-layer (91) is activated.

[0018] That is, a positive value P + layer (91 ') and a negative value N- layer (91) The source (S) and drain (D), which are represented by The voltage supplied from the cathode of the power supply is transmitted to the dielectric layer (92), A parasitic capacitor is generated in the dielectric layer (92) between the source (S) and the drain (D). And achieve the effect of preventing the entry of electromagnetic waves. However, the amount of electricity of the parasitic capacitor and The signal interference unit area or the amount of interference current is not fixed and invariable. Structure (10), dielectric layer (20), positive value P + layer (91 '), and Eggplant N-layer (91), metal layers (50) (51 '), Vcc metal ribbon ( 60), and the layout volume and area of the GND metal ribbon (60 '). It can be adjusted appropriately.

[0019] The above is a preferred embodiment of the present invention and limits the scope of implementation of the present invention. Not a thing. Therefore, it is a modification or change that can be Nothing made in the spirit of the idea and having an equal effect on this device The deviation also belongs to the scope of claims for utility model registration of this invention.

[0020]

[Effect of device]

The anti-signal interference ribbon according to this invention has the same standard as the local circuit inside the integrated circuit. And the length of the local circuit depends on the area required for anti-signal interference. Has the effect of adjusting the height and enhancing the anti-signal interference effect in a unit area in the integrated circuit. It

[0021] The anti-signal interference ribbon according to the present invention is a complementary thin film metal oxide transistor. It can be matched with the integrated circuit of, has high industrial utility value, and has an inventive step.

[Brief description of drawings]

FIG. 1 is an explanatory view showing a usage mode of an anti-signal interference ribbon according to the present invention.

FIG. 2 is a plan view of an anti-signal interference ribbon according to the present invention.

FIG. 3 is a partial exploded view of the anti-signal interference ribbon disclosed in FIG.

FIG. 4 is an enlarged view of a portion A in FIG.

FIG. 5 is an explanatory view showing a sectional structure of an anti-signal interference ribbon according to the present invention.

[Explanation of symbols]

C Anti-signal interference ribbon A Integrated circuit B Local circuit 10 PNP structure 20 Dielectric layer 50,50 'Metal layer 60 Vcc Metal ribbon 60' GND Metal ribbon 911,911 ', 921,61,61' Contact hole 70 P-veyor 80 deep N well layer 90 N well layer 91 'P + layer 91 N- layer 92 dielectric layer G gate S source D drain

Claims (2)

[Scope of utility model registration request] 1. An anti-signal interference ribbon of an integrated circuit provided around a local circuit in the integrated circuit, comprising a Vcc metal ribbon electrically connected to a Vcc positive voltage and a GND metal ribbon grounded to GND. And each metal ribbon is electrically connected to a complementary metal oxide semiconductor device having a PNP composition, the PNP structure producing a deep N-well layer on a P-base, An N well layer is formed on the deep N well layer, a P + layer, an N− layer, and a dielectric layer are formed on the N well layer, and the N− layer is formed.
A contact hole is formed at the layer position, the metal layer and the deep N-well layer are electrically connected to form a positive voltage ribbon, and a contact hole is separately formed at the P + layer position to form the metal layer. Forming a source and a drain by electrically connecting the contact hole and the Vcc metal ribbon to each other, and electrically connecting the contact hole and the Vcc metal ribbon in the N− layer.
An anti-signal interference ribbon of an integrated circuit, wherein the GND metal layer is electrically connected to an underlying dielectric layer to form a gate. 2. The positive voltage ribbon includes an N well layer,
The anti-signal interference ribbon of an integrated circuit of claim 1 comprising a deep N-well layer.