JP3095556B2 - On-line test method of processor mechanism - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for testing a processor mechanism in a computer system, and more particularly to a method for testing a processor mechanism in an online job by effectively utilizing a compiler provided in an operating system (OS). The present invention relates to an online test method for a processor mechanism.

[0002]

2. Description of the Related Art In recent years, a microprocessor is often used as a processor mechanism in a computer system. The microprocessor used generally has a pipeline control mechanism, an instruction cache, a data cache, and various buffers in order to increase the processing speed.

In order to test the processor mechanism of such a computer system online, that is, to check online whether or not the above functions in the microprocessor are operating normally, conventionally, the following method is used. The method was commonly used.

(1) A method in which a manually created test program is executed as a normal job for testing. (2) A method of using an application program as a test program.

[0005]

However, each of the above-mentioned conventional methods has the following problems.

(1) In the method using a test program created by hand, the mechanism of a microprocessor
Although suitable for the purpose of testing the function, it has the disadvantage of little change in terms of the combination of instructions to be tested.

(2) The method of using an application program as a test program has a drawback that the range of test cases is narrow because the application program is not created for the purpose of testing the processor mechanism.

As described above, the conventional method cannot be said to be a sufficient method for testing a microprocessor having advanced functions on-line, and it has been desired to develop a more effective on-line test method.

The present invention has been made in view of the above problems, and a processor mechanism capable of automatically generating a test program by effectively utilizing resources of an operating system (OS) and performing a variety of tests. The purpose of the present invention is to provide an online test method.

[0010]

According to the present invention, the above objects are achieved by the means as set forth in the appended claims.

That is, according to the first aspect of the invention, in a computer system equipped with a compiler, a group of unrelated source programs is compiled, and at least one of the linkage order or the execution order of the compiled programs is performed. Is an on-line test method for a processor mechanism that determines and executes a program based on a random number, and detects a processing inconsistency from the execution result.

According to the second aspect of the present invention, an assemble list of each of the source programs is stored, and when a failure is detected, the assemble list is attached as failure information to notify the failure. 4 is an online test method for the described processor mechanism.

According to a third aspect of the present invention, there is provided the online testing method for a processor mechanism according to the first aspect, wherein when compiling each of the source programs, a compiler optimization option is set according to the purpose of the test. .

According to a fourth aspect of the present invention, there is provided the online testing method for a processor mechanism according to the first aspect, wherein when compiling each of the source programs, a compiler optimization option is determined by random numbers and compiled.

According to a fifth aspect of the present invention, when compiling the source program, the compiler option specifies two cases, that is, a case where a floating-point operation instruction is expanded and a case where a floating-point operation instruction is not expanded. 2. The online testing method for a processor mechanism according to claim 1, wherein the program is executed for the above two cases.

According to the invention described in claim 6, the source program is constituted by a plurality of logic program blocks which do not interfere with each other, and the blocks are arbitrarily replaced and compiled to generate and execute a plurality of execution programs. An online test method for a processor mechanism according to claim 1.

[0017]

According to the online test method of the present invention, a test program is automatically generated while operating as a job under the OS, and logic for changing the pipeline control state of the processor is incorporated, thereby enabling the processor test to be executed. The variations (changes) are increased to solve the problems of the prior art.

That is, according to the first aspect of the present invention, the problems of the prior art can be solved by determining the execution position and execution order of each test program by random numbers and increasing the variation (change) of the processor test.

Hereinafter, an example of the processing operation will be described with reference to FIG. 1 illustrating the principle of the test method of the present invention. In FIG. 1, 1 is an operating system (OS), 2 is a compiler provided in the OS, 3
Is a linkage editor, 4 is a test generation program according to the present invention, 5 is a source file storing a test program (Ta · Tz), 6 is a compiled object file, 7 is an executable format test after linkage It is a program file.

The test programs (Ta..Tz) in the source file 5 are unrelated programs, and are described so as to store the processing results at addresses given as arguments.

Hereinafter, the processing performed in the principle explanatory diagram of FIG. 1 will be described. (1) First, the test generation program 4 executes each test program (Ta · Tz) in the source file 5.
Is compiled by the compiler 2 to create an object file 6.

(2) Each test program (Ta... T) in the object file 6 is determined by a random number.
The linkage order of z) is determined, and the test program file 7 in the executable format is generated.

(3) Next, the test generation program 4 dynamically loads the generated executable test program file 7 and combines it with the test generation program 4 itself. Each test program (Ta ・ ・ Tz)
Are determined using random numbers.

(4) The test program (Ta..Tz) is started in accordance with the determined execution order, and the execution result is saved. The first result is used as an expected value in the subsequent processing.

(5) From the second time onward, the subsequent processing from the linkage processing of the above item (2) is performed in the same manner and compared with the first expected value. In this manner, by changing the execution order of the test program (Ta · Tz) or the execution address at random, the test can be performed while the state of the hardware is variously changed. .

The invention described in claim 2 is based on claim 1.
In addition to the method of the invention described above, when compiling each test program (Ta..Tz) in the source file 5, an assemble list is saved, and when a fault is detected, the fault information is stored. Assemble
Notify by attaching a list.

By doing so, the cause of the failure can be easily grasped.

The third aspect of the present invention relates to the first aspect.
In addition to the method of the invention described, the source file 5
When compiling the middle test program (Ta · Tz), the compiler optimization options are not fixed, but are set according to the purpose of the test.

By adopting such a method, the machine instruction sequence can be changed according to the test purpose without changing the logic (configuration logic) of the test program, and the variation (change) of the test content can be reduced. It is possible to increase.

[0030] The invention described in claim 4 is based on claim 1.
In addition to the method of the invention described above, when compiling each test program (Ta · Tz) in each source file 5, a compiler optimization option is determined by a random number.

By adopting this method, the machine instruction sequence can be changed without changing the logic of the test program, and the test variation (change)
Can be increased.

The invention described in claim 5 is based on claim 1.
In addition to the method of the invention described above, when compiling each test program (Ta... Tz) in each source file 5, as a compiler option, expansion of floating-point operation instructions is performed and not performed. Compiling is performed by designating the two cases, and for the above two cases, the program is executed, and processing inconsistency of hardware or a compiler is detected.

In this way, it is possible to further increase the variations (changes) of the test cases.

The invention described in claim 6 is based on claim 1.
In addition to the method of the invention described, the source program is further composed of a plurality of logic program blocks that do not interfere with each other, and the blocks are interchanged and compiled to generate a plurality of execution programs, each of which is executed. Detect processing inconsistency.

As described above, a test program rich in variations can be automatically generated based on a manually created source file.

[0036]

【Example】

(A) First Embodiment As a first embodiment of the present invention, a method of determining the execution position and execution order of each test program by using random numbers will be described. This embodiment is an embodiment corresponding to the first aspect of the present invention.

FIG. 2 is a block diagram showing the configuration of one embodiment of the present invention. In FIG. 2, reference numeral 8 denotes an execution result storage area for storing an execution result of the program, 9 denotes a link order determination table 9a for determining a linkage order of each test program (Ta · Tz) and an execution order determination table for determining an execution order. 9b shows a linkage / execution order determination table consisting of 9b. Other symbols are the same as those in FIG.
The description is omitted.

Each test program (Ta..Tz) in each source file 5 is a program unrelated to each other, and is described so as to store a processing result at an address given as an argument.

Hereinafter, the operation of FIG. 2 will be described. (1) First, the test generation program 4 executes each test program (Ta · Tz) in the source file 5.
Is compiled by the compiler 2 provided in the OS1,
Create the object file 6.

(2) Then, using the random numbers, each test program (Ta..T) in the object file 6
The linkage order of z) is determined and registered in the link order determination table 9a.

(3) The test generation program 4 executes the object file 6 according to the link order determination table 9a.
Is input, the linkage editor is called, and an executable test program file 7 is generated.

(4) Each test program (Ta... T
Similarly to the linkage order, the execution order of z) is determined by random numbers and set in the execution order determination table 9b. (5) Next, the test generation program 4 dynamically loads the generated executable test program file 7 and combines it with the test generation program 7 itself (test generation program). ..Tz) and save the execution result in the execution result storage area 8. The result obtained in the first processing is set as an expected value of the subsequent processing.

(6) From the second time onward, the subsequent processing from the linkage processing of item (2) above is performed in the same manner and compared with the first expected value. Such processing is repeated until the execution time expires or there is a termination request.

As described above, by randomly changing the execution order and the execution address of the test program and executing the test program, it is possible to change the state of the hardware variously.
Testing can be performed.

The above processing is shown in the flowcharts of FIGS. 3 and 4 for explaining the processing in the first and second embodiments of the present invention.

Hereinafter, the processing performed according to the flowcharts of FIGS. 3 and 4 will be described. The symbol [S] is used to represent the meaning of the steps in the flowchart. (1) In S301, each test program (Ta ·
Compile each test source file in which Tz) is stored to create an object file.

(2) In S302, the link order of each test program (Ta..Tz) is determined by random numbers and registered in the link order determination table 9a. (3) In S303, the input to the linkage / editor 3 is determined according to the link order determination table 9a, and an executable test program file 7 is created.

(4) In S304, the execution order of each test program (Ta..Tz) is determined by random numbers,
It is registered in the execution order determination table 9b. (5) In S305, the test program file 7 in the executable format is combined with the test generation program 4.

(6) In S306 of FIG. 4, the test program is started according to the execution order determination table 9b. (7) In S307 of FIG. 4, it is determined whether or not the first test program is executed. If it is the first time, S30
8 and registers the execution result in the execution result storage area 8 as an expected value. If it is the second or later execution, S3
Move to 09.

(8) In S309 of FIG. 4, it is compared whether the execution result is equal to the expected value. If not, report an error. If it is equal to the expected value,
The process moves to S310.

(9) In S310 of FIG. 4, it is checked whether all tests have been completed. If all the tests have been completed, the process proceeds to S311. If not, the process returns to S306 of FIG. 3 again to start the test.

(10) In S311, it is determined whether or not there is a test termination instruction. If there is a termination instruction, the test is completed. If there is no termination instruction, the flow returns to S302 in FIG.

(B) Second Embodiment As a second embodiment of the present invention, a method of attaching an assemble list to information at the time of detecting a failure will be described. This embodiment is an embodiment corresponding to the second aspect of the present invention.

In the first embodiment, when compiling the source of each test program (Ta..Tz), the assemble list is left as a temporary file. If a failure is detected as a result of the test, an assemble list file is output as a part of the error information. If the test is completed successfully,
The assemble list file is deleted.

By doing so, it becomes easy to grasp the failure.

The above processing is shown in the flowcharts of FIGS. 3 and 4 for explaining the processing in the first and second embodiments of the present invention. That is, S312 in FIG.
In FIG. 4, the assemble list of each test program (Ta..Tz) is stored and stored in a temporary file, and when an error is detected in S309 of FIG. 4, the assemble list is displayed together with an error notification.

(C) Third Embodiment As a third embodiment of the present invention, a method of generating a test program according to a test purpose will be described. This embodiment is an embodiment corresponding to the third aspect of the present invention.

In the method of the first embodiment, when compiling the source file 5 of each test program (Ta · Tz), optimizing options are not fixed and each source is compiled according to the purpose of the test. For each, determine the optimization options.

By adopting such a method, the machine instruction sequence can be changed according to the test purpose without changing the logic (configuration logic) of the test program, and the variation (change) of the test contents can be reduced. Will increase.

That is, in the case of compilation without the optimization option, there is a high probability that register interference and memory interference will occur. Conversely, when the highest optimization option is specified, such interference hardly occurs.

In the present embodiment, for example, there are four types of optimization options from "0" to "4", and if the option designation is "0", no optimization is performed, and if "4", optimization is performed most. Assume that you compile.

If a test for causing memory interference and register interference to occur as frequently as possible is desired, the test generation program 4 is started by designating "0" as the start option. As a result, the test generation program 4 specifies the optimization option “0” of the compiler and calls the compiler. If it is desired to perform the test without causing pipeline interference as much as possible, "4" may be specified as the start option.

The above processing is the third, fourth, and fourth steps of the present invention shown in FIG.
S500, S501 and S502 on the flowchart for explaining the processing in the fifth embodiment are shown.

(D) Fourth Embodiment As a fourth embodiment of the present invention, a description will be given of a method of generating a test program for determining a designated level of an optimization option at the time of a compiler by using a random number. This embodiment is an embodiment corresponding to the invention described in claim 4.

In the third embodiment, the specification level of the optimization option of the compiler is fixed in accordance with the purpose of the test. However, by randomly selecting the specification level of the optimization option, the variation (change) of the test contents can be changed. ) Can be increased.

By adopting this method, the machine instruction sequence can be changed without changing the logic of the test program, and the test variations (changes) increase.

The above processing is performed in steps S500, S503, S504 and S505 in the flowchart of FIG.
Is shown in

(E) Fifth Embodiment A description will be given of a method of generating a test program by controlling FPU instruction expansion options as a fifth embodiment of the present invention. This embodiment is an embodiment corresponding to the invention described in claim 5.

As a compiler option, there is an option for setting whether or not to expand an FPU instruction (floating-point operation instruction). When this option is set, a floating-point instruction is expanded. Expands the logic that emulates floating-point instructions.

By providing this optional control in the compilation procedure in the first embodiment, it is possible to further increase the number of test case variations. For example, when the test program is executed a plurality of times to detect a processing inconsistency, when the test program is executed in the odd number of times, all the test programs (Ta..Tz) are compiled and executed with the FPU expansion designation, and the even number of times Compile and execute without FPU, and confirm that the result is the same.

As in the fourth embodiment, the validity / invalidity of this option can be determined by random numbers.

(F) Sixth Embodiment As a sixth embodiment of the present invention, a method for automatically generating a test program will be described. This embodiment corresponds to claim 6
It is an example corresponding to the described invention.

The above-described methods from the first embodiment to the fifth embodiment are directed to a method of increasing the types of machine instruction strings to be developed by manually expanding a test program by making full use of compiler options. is there. The method described here is a method of increasing the variations of the machine instruction sequence to be expanded by replacing and compiling the internal logic of the source program of the test program.

FIGS. 6 and 7 are diagrams for explaining the sixth embodiment of the present invention. Reference numeral 11 denotes a source file of a basic test program (described in C language);
Is a test generation program, and 13 is a source file resulting from replacing the logic and exists as a temporary file. The logics 1 to 5 are logics in the test program, and the logics 1 to 5 are described so as not to affect each other. Numeral 14 denotes a comment description (portion between symbols “/” and “/”), which is described at the boundary of each logic. The logic sandwiched between the two comments is logically closed, and is separated from other logics. Means irrelevant. For example, even if the logic 1 and the logic 5 are replaced, the results of the other logics 2, 3, and 4 as well as the logics 1 and 5 are not affected. The test generation program 12 reads the source file 11, arbitrarily replaces the internal logics 1 to 5 using a random number, and writes it into a temporary source file 13. And this temporary input source file 1
3 is input to the compiler.

Further, by not only replacing the logic but also continuously developing or deleting the same logic, the size of the test program in the input source file 13 can be freely changed.

As described above, according to the method of the sixth embodiment, a variety of test programs can be automatically generated based on a manually created source file. The above processing is shown in the flowcharts of FIGS. 8 and 9 for explaining the processing in the sixth embodiment of the present invention.

(1) In S801, an input source file storing a basic test program and an output source file storing a test program resulting from replacing logic are opened.

(2) In S802, one line of text in the source list of the test program is read (read).
I do. (3) In S803, the comment “logic st
is determined as “art”. If the result is YES, the process proceeds to S805, and if NO, the read text is stored in the pre-processing area in S804, and the process proceeds to S8.
Return to 02, and continue reading (reading) the text.

(4) In S805, 1 is set in the logic counter. (5) In S806, one line of the text is read (read). (6) In S807, it is determined whether or not the read text is a comment “logic end”.
If the result is TES, the flow shifts to S811 in FIG. If the result is NO, the process moves to S808.

(6-1) In S808, it is determined whether or not the read text is a comment "logic bound". If the result is NO, S809
In, the read text is stored in the logic stack area indicated by the logic counter, and the process returns to S806. If the result is YES, the logic counter is updated in S810, and the process returns to S806.

(7) In S811 of FIG. 9, all remaining texts are read and stored in the post-processing area. (8) In S812 in FIG. 9, the preprocessing is written to the output source file.

(9) In S813 of FIG. 9, the number of logic stack areas indicated by the logic counter is selected by a random number, and is written to the output source file. (10) In S814 of FIG. 9, post-processing is written to the output source file.

(11) In S815 of FIG.
Close the output source file. (12) In S816 in FIG. 9, the output source file is compiled.

[0084]

As described above, by using the online testing method of the processor mechanism of the present invention, the O
A test program of a different machine instruction sequence is automatically generated while using the resources of S, and the test is performed with variously changed test conditions, so that the internal state of a complicated processor can be verified.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining the principle of the test method of the present invention.

FIG. 2 is a block diagram showing a configuration of one embodiment of the present invention.

FIG. 3 is a flowchart (first half) illustrating processing in the first and second embodiments of the present invention.

FIG. 4 is a flowchart (second half) for explaining processing in the first and second embodiments of the present invention;

FIG. 5 is a flowchart for explaining processing in third, fourth, and fifth embodiments of the present invention.

FIG. 6 is a diagram (first half) for explaining a sixth embodiment of the present invention.

FIG. 7 is a diagram (second half) for explaining a sixth embodiment of the present invention.

FIG. 8 is a flowchart (first half) illustrating a process according to a sixth embodiment of the present invention.

FIG. 9 is a flowchart (second half) for explaining processing in a sixth embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Operating system (OS) 2 Compiler 3 Linkage editor 4 Test generation program 5 Source file 6 Object file 7 Executable test program file 8 Execution result storage area 9 Linkage / execution order determination table 11 Original test program Source file 12 Test generator 13 Source file resulting from replacing logic 14 Comment description

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 11/22-11/26 G06F 9/45 CSDB (Japan Patent Office)

Claims (6)

(57) [Claims] In a computer system equipped with a compiler, a source program group having no relation to each other is compiled, and at least one of a linkage order and an execution order of each of the compiled programs is determined by a random number and executed. An on-line test method for a processor mechanism, wherein a processing inconsistency is detected from the execution result. 2. When compiling each of the source programs, the assemble list is saved, and when a failure is detected, the assemble list is attached as the failure information and notified. 2. An online test method for a processor mechanism according to claim 1, wherein 3. The method according to claim 1, wherein when compiling each of the source programs, a compiler optimization option is set in accordance with the purpose of the test. 4. The online testing method of a processor mechanism according to claim 1, wherein when compiling each of the source programs, a compiler optimization option is determined by a random number and compiled. 5. When compiling the source program, compiling is performed by designating two cases, that is, a case where a floating-point operation instruction is expanded and a case where it is not performed, as a compiler option. 2. The method according to claim 1, further comprising executing a program. 6. The method according to claim 1, wherein the source program is composed of a plurality of logic program blocks that do not interfere with each other, the blocks are arbitrarily replaced and compiled, and a plurality of execution programs are generated and executed. Item 10. An online test method for a processor mechanism according to Item 1.