JP3095507B2 - Data compression and recording method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data compression / recording method , and more particularly to a data compression / recording method suitable for use in an image pickup apparatus suitable for picking up still images.
Data compression / recording method .

[0002]

2. Description of the Related Art FIG. 6 is a diagram showing an example of the configuration of a conventional image pickup apparatus for recording a still image on a memory card. 6, reference numeral 101 denotes a solid-state imaging device used as a sensor that converts an optical image into an electric signal; 300, a lens that forms an optical image on the solid-state imaging device 101;
An aperture for adjusting the amount of light incident on the solid-state imaging device 101, a shutter for adjusting the exposure time of the solid-state imaging device 101, an AD conversion circuit 203 for converting the output of the solid-state imaging device 101 into a digital signal, and a solid-state conversion device 204 A frame memory 205 serving as a storage unit for temporarily storing a signal for one frame of the image sensor 101;
A recording signal processing circuit which extracts at least two lines of data which are adjacent to each other from the output signal of the solid-state imaging device 101 and calculates a luminance signal and a color difference signal by calculation; An image compression circuit for encoding signals and color difference signals and compressing the data; 207, a memory card as recording means constituted by a semiconductor memory for recording an image;
Reference numeral 08 denotes an image decompression circuit for decompressing encoded image data read from the memory card 207, and reference numeral 209 denotes a reproduction signal processing circuit for displaying the decompressed luminance signal and color signal on an external monitor. 210 is a system controller for controlling the operation of the image sensor, and 211 is a trigger switch for starting a photographing sequence.

FIG. 7 is a diagram showing a sequence for recording a still image by the imaging apparatus of FIG. When the trigger switch 211 is turned on at time T0, a series of still image recording sequences is started. First, between time T0 and T1, dark charge accumulated in the solid-state imaging device 101 is transferred and removed, and then a photometry operation is performed by a photometry device (not shown). Is set. Next, from time T2 to T3, the shutter 202
Is opened, and the exposure operation to the solid-state imaging device 101 is performed.
Next, when the shutter 202 is closed at the time T3, the exposure signal charges are read from the solid-state imaging device 101.
A signal read from the solid-state imaging device 101 is converted into a digital signal by an AD conversion circuit 203, and a signal for one frame is temporarily stored in a frame memory 204. Next, when the reading of the exposure signal is completed at time T4, the signal once stored in the frame memory 204 is read from time T4 to T5, and the recording signal processing circuit 205 detects several pixels of the solid-state imaging device 101 which are adjacent to each other. From the data, a luminance signal and a color difference signal are obtained by calculation.
The luminance signal and the color difference signal are coded data compressed by means specified by the JPEG standard by the image compression circuit 206 and recorded on the memory card 207.

FIG. 8 is an explanatory diagram of an interline type CCD as an example of a commonly used solid-state imaging device. In FIG. 8, reference numeral 101 denotes a solid-state imaging device which is an interline CCD, 102 denotes a photodiode which converts light into electric charges and accumulates, and 103 denotes a vertical which vertically transfers electric charges transferred from the photodiode 102 one by one to 1H. It is a CCD. V1 to V4 are transfer electrodes of the vertical CCD 103, and V1 also serves as a transfer gate for transferring odd-numbered charges of the photodiode 102 to the vertical CCD 103. Similarly, V3 is a transfer gate corresponding to the photodiode 102 in the even-numbered row. The vertical CCD 103 is driven by four-phase transfer pulses applied to the transfer electrodes V1 to V4. Reference numeral 104 denotes a horizontal CCD for horizontally transferring the electric charges transferred one stage to the 1H from the vertical CCD 103. H
Reference numerals 1 and 2 denote transfer electrodes of the horizontal CCD 104, which are driven by two-phase pulses. An output amplifier (FDA) 105 converts a charge into a voltage and outputs the voltage. VOUT is an output terminal. Reference numeral 106 denotes a top drain for sweeping out unnecessary charges.

FIG. 9 is a diagram showing the read timing of the interline CCD shown in FIG. At time t1, the vertical blanking period starts. At time t2, the potential of the transfer electrode V1 becomes Hi level and the transfer gate is opened.
3 is transferred. From time t3, the charge of the vertical CCD 103 is transferred in the direction of the one-stage horizontal CCD 104 in one horizontal period, and the charge transferred to the horizontal CCD 104 is transferred at high speed, converted into a voltage by the FDA 105, and output. The reading of the charges of all the odd lines ends at time t4.

Next, from time t5 of the vertical blanking period, the potential of the transfer electrode V3 becomes Hi level, and the charges of the photodiodes 102 on the even-numbered lines are transferred to the vertical CCD 103, and one line horizontal CCD from time t6 for one horizontal period.
The data is transferred to the same 104, and is similarly transferred at a high speed and output.

FIG. 10 is a diagram showing a color arrangement of a color filter provided corresponding to each color on each light receiving element of the solid-state imaging device 101 for imaging a color signal. It is shown in FIG.

In FIG. 10A, the symbol Ye is yellow,
Cy indicates cyan, Mg indicates magenta, and G indicates green.
F1: n indicates that the signal is read as the signal on the n-th line of the first field, and F2: n indicates that the signal is read on the n-th line of the second field. Similarly, F1: n + 1 indicates that the signal is read as the signal on the (n + 1) th line of the first field, and F2: n +
1 indicates that the signal is read on the (n + 1) th line of the second field. FIG. 10B shows an example of a calculation necessary for extracting the luminance signal and the color difference signal. Since the luminance signal and the color difference signal are obtained from the four color signals of Ye, Cy, Mg, and G, when reading the signal from the frame memory 204, for example, the signal of the nth line of the first field and the nth line of the second field The luminance signal and the chrominance signal of the n'th line are simultaneously read and operated to simultaneously read the signal of the n'th line of the second field and the signal of the (n + 1) th line of the first field. By performing the operation, the luminance signal and the color difference signal of the n ′ + 1th line are sequentially obtained, and n ′, n ′ +
A luminance signal and a color difference signal corresponding to the non-interlaced scanning lines of 1, n '+ 2, ... are obtained. As described above, a frame memory 204 is required to convert a signal read out from the solid-state imaging device 101 by interlacing to non-interlace and obtain pixel information of a neighboring scanning line. Storing all the pixel information of the image sensor 101 requires a large capacity because the precision of the AD conversion of the pixel information for each pixel is required to be 10 bits and the like, which increases the cost of the image pickup apparatus.

[0009]

[0010]

[Means for Solving the Problems] The imaging apparatus of the present invention comprises:
The exposure charge signal stored in the solid-state imaging device is AD-converted, and
Row reversible data compression by a constant data compression means
Once the obtained data is stored in the storage means,
And decompressing the data after subjected to predetermined signal processing, said plant
It is characterized in that reversible data compression or irreversible data compression is performed by a fixed data compression means and then recorded in the recording means.

[0011]

[0012]

According to the present invention, data obtained by imaging
Finally, the signal is compressed by subjecting it to predetermined signal processing and recorded in the recording means.
If you attempt to record,
By performing storage in the storage unit, the predetermined signal processing is performed.
Before performing the operation, temporarily reduce the capacity to store the data.
Before the signal processing, the image represented by the data
The image quality (image quality) is not degraded.
In addition, the above temporary lossless compression and predetermined signal processing were performed.
A single compression means combines the subsequent compression
This realizes a small-scale and low-cost.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing an example of an image pickup apparatus to which the present invention is applied . Note that the same reference numerals are given to block components having the same functions as those in FIG. 6, and a description thereof will be partially omitted.

In FIG. 1, reference numeral 3 denotes an image compression circuit having means for reversibly compressing data. SW1 is a switch for switching the input of the image compression circuit 3, and the output of the recording signal processing circuit 205 is on the a side, and the AD conversion circuit 2 is on the b side.
03 is connected. Reference numeral 2 denotes a frame memory serving as storage means for storing data reversibly compressed by the image compression circuit 3. SW2 is a switch for switching the output of the image compression circuit 3;
On the side, it is connected to a memory card 207 as recording means.

Reference numeral 4 denotes an image expansion circuit for expanding compressed data. Reference numeral 1 denotes a two-line buffer memory for storing expanded data of two adjacent lines. S
W3 is a switch for switching the input of the image expansion circuit 4. The output of the memory card 207 is connected to the a side, and the output of the frame memory 2 is connected to the image expansion circuit 4 on the b side.
SW4 is a switch for switching the output of the image decompression circuit 4, and is connected to the two-line buffer memory 1 on the a side and to the reproduction signal processing circuit 209 on the b side.

FIG. 3 is a diagram showing the configuration of the image compression circuit 3 and the image expansion circuit 4. In FIG. 3, the image compression circuit 3
Is composed of a system that performs lossless compression and a system that performs lossy compression. Reference numeral 5 denotes a DCT operation circuit that performs a two-dimensional DCT operation on an input image to divide the image into two-dimensional spatial frequency components. Reference numeral 6 denotes a quantization circuit for quantizing DCT coefficients, and reference numeral 7 denotes an entropy encoder for Huffman encoding the quantized DCT coefficients. DCT operation circuit 5, quantization circuit 6,
Irreversible image compression is performed by the entropy encoder 7. Reference numeral 8 denotes a predictor, which predicts data of a certain pixel by using data of one pixel before, and 9 denotes an entropy encoder, which performs Huffman encoding of a difference between a certain pixel and a pixel predicted by the predictor 8. Thus, reversible data compression is performed by the predictor 8 and the entropy encoder 9. SW5 is a switch for selecting whether to perform a reversible compression operation or an irreversible compression operation. The a side selects reversible compression operation, and the b side selects irreversible compression operation.

The image expansion circuit 4 comprises a system for performing reversible expansion and a system for performing irreversible expansion. The entropy decoder 10 and the decoder 11 decode the losslessly compressed data by the operation reverse to that of the entropy encoder 9 and the predictor 8.
The entropy decoder 12, the inverse quantization circuit 13, and the inverse DCT operation circuit 14 decode the data compressed by the operation reverse to that of the DCT operation circuit 5, the quantization circuit 6, and the entropy encoder 7. SW6 is a switch for selecting whether to perform a reversible expansion operation or an irreversible expansion operation.
The reversible extension operation is selected on the side, and the irreversible extension operation is selected on the b side.

FIG. 2 is a diagram for explaining the operation timing of the above embodiment. The operation of the above embodiment will be described based on FIG. 2, FIG. 1, and FIG. In FIG. 2, when the trigger switch 211 is turned on at a time T0, first, the dark charge of the solid-state imaging device 101 is removed, and a photographing operation is started. From time T1 to T2, a photometric operation is performed by a photometric sensor (not shown), and an appropriate aperture and shutter speed are set. Shutter 20 from time T2 to T3
2 is opened and the exposure signal charges are accumulated. At time T3, the shutter 202 is closed, and the exposure signal charges are read from the solid-state imaging device 101 from time T3 to T4. At this time, the switch SW1 is set to the b side and the switch SW2 is set to a
By setting the switch SW5 to the a side,
The output signal of the solid-state imaging device 101 is reversibly compressed by a method as shown in FIG.

FIG. 4 is an explanatory diagram of a method of performing a reversible compression method of the pixel data of the solid-state imaging device 101.
10A shows a color filter having the same arrangement as that of FIG. 10, but a signal for explanation is given to a signal on the n-th line in the first field and a signal on the n-th line in the second field. FIG.
(B) shows an example of a method of performing reversible compression, in which the data before one pixel is used as a prediction value, the difference in the value between adjacent pixels is calculated, and Huffman coding is further performed to compress the data amount. When calculating the difference between the pixels, the difference between the same colors having a high correlation is calculated as shown in FIG. Next, from the compressed data once stored in the frame memory 2 from time T4 to T5, data of two adjacent lines, for example, a signal of the nth line of the first field and a signal of the nth line of the second field are read and compressed. The data is decompressed and read out to the two-line buffer memory 1 by the operation reverse to that described above, and the operation shown in FIG. 10B is performed to calculate the luminance signal and the color difference signal. After going, the memory card 20
Record in 7. The switch SW1 is on the a side and the switch SW
2 on the b side, switch SW3 on the b side, switch SW4
The switch SW5 is set to the a side when performing reversible compression, and the switch SW5 is set to the b side when performing irreversible compression. To obtain a reproduction output, set the switch SW3 to the a side,
The switch SW4 is set to the b side, and the switch SW6 is set to the a side when performing reversible data expansion, and the b side when performing irreversible compression. The signal is input to the signal processing circuit 209.

In the reversible compression as described above, the data amount after compression differs depending on the image, but in most images, the data amount before compression is less than half. It can be reduced by about half. However, when the capacity of the frame memory 2 is less than half of that of the conventional example, or when a special pattern image is used, all data may not be written.

FIG. 5 is a flowchart of an embodiment in which the photographing can be performed even when the capacity of the frame memory 2 becomes insufficient. That is, when the capacity of the frame memory 2 becomes insufficient, data is written to the free space of the memory card 207, thereby enabling photographing. If the access speed of the memory card increases in the future, the frame memory may be eliminated and the data of the solid-state imaging device once compressed may be stored in the memory card.

[0023]

As described above, according to the present invention, the solid
The exposure charge signal stored in the image pickup device is AD-converted to a predetermined value.
Perform reversible data compression by data compression means
The stored data is temporarily stored in the storage means, and the data is stored at predetermined intervals.
After decompressing the data and performing predetermined signal processing, the predetermined data
Reversible data compression or non-
After recording in the recording means after performing reverse data compression
So that the final
Is subjected to predetermined signal processing and compressed, and the recording means (in the embodiment,
Indicates that when trying to record on the memory card 207)
And temporarily store lossless compression and storage means (frames in this embodiment).
By storing in the memory 2), the predetermined signal is stored.
The above data should be temporarily stored before performing the signal processing.
The volume can be reduced, and the data
Does not degrade the quality (image quality) of the image represented by. Furthermore,
The pressure after performing the above temporary lossless compression and predetermined signal processing
Compression and single compression means are combined so that the
Small scale and low cost can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of an imaging apparatus to which the present invention is applied .

FIG. 2 is a diagram illustrating the operation timing of the embodiment.

FIG. 3 is a diagram illustrating a configuration of an image compression circuit and an image decompression circuit.

FIG. 4 is an explanatory diagram of a method of performing reversible compression of pixel data of a solid-state imaging device.

FIG. 5 is a flowchart of an embodiment improved to enable shooting even when the capacity of the frame memory is insufficient.

FIG. 6 is a diagram illustrating a configuration example of a conventional imaging device that records a still image on a memory card.

FIG. 7 is a diagram showing a sequence for recording a still image by the imaging device of FIG. 6;

FIG. 8 is an explanatory diagram of an interline CCD as an example of a solid-state imaging device.

FIG. 9 is a diagram showing read timing of the interline CCD of FIG. 8;

FIG. 10 is a diagram showing a color arrangement of a color filter provided corresponding to each color on each light receiving element of the solid-state imaging device.

[Explanation of symbols]

 2 Frame memory 3 Image compression circuit 4 Image expansion circuit 101 Solid-state image sensor 201 Aperture 202 Shutter 203 AD conversion circuit 205 Recording signal processing circuit 207 Memory card 209 Reproduction signal processing circuit 210 System controller 211 Trigger switch 300 Lens

Claims (1)

(57) [Claims] An A / D converter converts an exposure charge signal stored in a solid-state imaging device into an AD signal, and performs reversible data compression by predetermined data compression means.
The obtained data is temporarily stored in a storage unit, and after decompressing the data by a predetermined amount and performing predetermined signal processing, the predetermined data compression unit performs reversible data compression or irreversible data compression. A data compression / recording method characterized in that data is recorded in a recording means after data compression.
Law .