JP3094458B2 - Carry transmission circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a carry transmission circuit used for an increment circuit and the like, and more particularly to a carry look ahead (hereinafter referred to as "CL") for transmitting a carry at a high speed.
A) and an improved carry transfer circuit.

[0002]

2. Description of the Related Art FIG. 3 shows a configuration of a conventional increment circuit for handling 8-bit data using a CLA circuit. The increment circuit of FIG. 3 includes a latch circuit 1 for storing an increment result at a clock φ1 for holding data of the first bit, and an output of the latch circuit 1 at a clock φ2.
EOR of the latch circuit 2 stored by the following equation and the carry signal Cn (n = 0 to 7) from the lower bit of the output of the latch circuit 2
(Exclusive OR) and a logic circuit block CNTn composed of an EOR circuit 3 and the carry signal C
and a CLA circuit 10 for obtaining n at a high speed.

The CLA circuit 10 receives a carry signal C from the outside, and outputs a carry signal C0 of the first bit as it is, a data output D1 of the first bit and a carry signal C1. And a logical circuit G1 that outputs a carry signal C1 of the second bit by taking AND logic of
And a logic circuit G2 that performs an AND logic operation on the data output D1 of the first bit, the data output D2 of the second bit, and the carry signal C to output a carry signal C2 of the third bit
Similarly, in the same manner, the N outputs from the data output D1 of the first bit to the data output DN of the Nth bit are ANDed with the carry signal C to carry the carry signal of the Nth bit. A logic circuit Gn (n = 1 to 8) for outputting Cn.

CLA circuit 10 for transmitting carry
Indicates that, when the data to be incremented is data in which all the digits are "1" and a carry from the lower bit occurs, a logical operation operation of outputting a carry signal to the upper bit is performed by two logical gates. Since it can be performed only by requiring a delay time, the increment operation can be performed at high speed.

[0005]

However, since the above-mentioned conventional CLA circuit is basically constituted by combining logic gate circuits, the number of transistors constituting the circuit increases, and this circuit is integrated into an integrated circuit. When applied, there is a disadvantage that the chip size of the integrated circuit becomes large.

The present invention has been made in view of such a problem, and a circuit capable of CLA operation is formed by combining an N-type MOS transistor and a P-type MOS transistor instead of a combination of logic gate circuits, and has the same function. It is another object of the present invention to provide a carry transfer circuit capable of reducing the number of transistors required to obtain the same performance and reducing the chip area when applied to an integrated circuit.

[0007]

A carry transmission circuit according to the present invention comprises a cascade connection of (N + 1) N-type MOS transistors with a source-drain connected in series,
An N-type MOS transistor circuit in which a reference potential is applied to one end of a series circuit of drains;
Source-drain between the drain of each of the K-th (2 ≦ K ≦ N + 1) N-type MOS transistors from the second to (N + 1) th counting from the reference potential side of the OS transistor and the power supply potential And a P-type MOS transistor circuit in which K P-type MOS transistors are connected in parallel, and the gate of the K-th N-type MOS transistor from the reference potential side of the N-type MOS transistor circuit is (K−1) A data signal of a bit is input, and the K P-type transistors of the P-type MOS transistor circuit connected to the drain of the N-type MOS transistor
1 from the (K-1) th bit to the gate of the OS transistor
The (K-1) data signals and the carry signal up to the bit are respectively inputted, and the carry signal is inputted to the gate of the N-type MOS transistor connected to the reference voltage of the N-type MOS transistor circuit. It is characterized by the following.

[0008]

In the carry transmission circuit according to the present invention, an N-type MOS transistor and a P-type MOS transistor are combined, instead of a combination of logic gate circuits, to form a dedicated C-type MOS transistor.
Since a circuit capable of LA operation is configured, the conventional CLA
The number of transistors required to obtain the same function and the same performance as the circuit can be reduced. Therefore, when this circuit is applied to an integrated circuit, the chip area can be reduced.

[0009]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows a configuration of an 8-bit increment circuit using a carry transmission circuit according to a first embodiment of the present invention.

As in the case of the CLA circuit 10 shown in FIG. 3, the input / output signals of the carry transmission circuit 11 shown in FIG. 1 include an external carry signal C and 8-bit data D1, D2, D3 to be incremented. D4, D5, D6, D7, D8 are input signals, and carry signals C0, C1, C2, C
3, C4, C5, C6, C7, and C8 are generated.

Carry transmission circuit 11 is configured as follows. That is, nine N-type MOS transistors Q _{N0 to} Q _N8
Are connected in cascade with the source-drain in series. Connecting the source of the N-type MOS transistor Q _NO located at one end of the series circuit to the reference potential. Nodes of the source and the drain of the series circuit, that is, connection points are N1 to N8, N-type MOS
The drain of the transistor Q _N8 is N 9, and each of the nodes N 2 to N 9 except the node N 1 has the same number of P-type MOS transistors Q _{P11 to} Q P as the number of N-type MOS transistors connected from that node to the reference potential. _P18 , Q _P21 ~
Q _P28 , Q _{P32 to} Q _P38 , Q _{P43 to} Q _P48 , Q _{P54 to} Q _P58 ,
Q _{P65 to} Q _P68 , Q _{P76 to} Q _P78 , Q _P87 , Q _P88 , and Q
_The source and the drain are connected in parallel between _P98 and the power supply. Each P-type MOS transistor Q _{P11 to} Q _P18 , Q _{P21
~Q P28, Q P32 ~Q P38,} Q P43 ~Q P48, Q P54 ~
Q _P58 , Q _{P65 to} Q _P68 , Q _{P76 to} Q _P78 , Q _P87 , Q _P88 ,
And the gate of Q _P98 receives the same signal as that input to the gate of each N-type MOS transistor connected between the corresponding node and the reference potential. The carry signal C is applied to the gates of the N-type MOS transistors Q _{N0 to} Q _N8 , the first bit data output D1 is applied to the gate of the N-type MOS transistor Q _N1 , and the second bit is applied to the gate of the N-type MOS transistor Q _N2 . Data output D2, N type M
The third bit data output D3 is applied to the gate of the OS transistor Q _N3 , and 4 is applied to the gate of the N-type MOS transistor Q _N4
Data output D4 of the bit, N-type MOS transistor Q
The gate of _N5 has a data output D5 of the fifth bit and an N-type MO.
The gate of the S transistor Q _N6 has a data output D6 of the sixth bit, the gate of the N-type MOS transistor Q _N7 has a data output D7 of the seventh bit, and the N-type MOS transistor Q _N8.
Are connected to an eighth-bit data output D8. The carry signals C0 to C8 of the respective bits correspond to the nodes N1 to N1.
Each is taken out from N9 via an inverter.

In response to the data of the input signals D1 to D8 at this time, when the increment signal C becomes active, that is, when "1" is input as the increment signal C, each N-type MOS transistor of the carry transmission circuit 11 The transistors Q _{N0 to} Q _N8 , each P-type MOS transistor Q _P11 to
Q _P18 , Q _{P21 to} Q _P28 , Q _{P32 to} Q _P38 , Q _{P43 to} Q _P48 ,
Q _{P54 to} Q _P58 , Q _{P65 to} Q _P68 , Q _{P76 to} Q _P78 , Q _P87 ,
Tables 1 to 48 show the states of Q _P88 and Q _P98 and the truth tables of the outputs C1 to C8. According to Tables 1 to 48, FIG.
It can be understood that the same logical output as that of the conventional CLA circuit can be obtained by the carry transmission circuit 11 of FIG. ■ 0014 ■

[Table 1] ■ 0015 ■

[Table 2] ■ 0016 ■

[Table 3] ■ 0017 ■

[Table 4] ■ 0018 ■

[Table 5] ■ 0019 ■

[Table 6] ■ 0020 ■

[Table 7] ■ 0021 ■

[Table 8] ■ 0022 ■

[Table 9] ■ 0023 ■

[Table 10] ■ 0024 ■

[Table 11] ■ 0025 ■

[Table 12] ■ 0026 ■

[Table 13] ■ 0027 ■

[Table 14] ■ 0028 ■

[Table 15] ■ 0029 ■

[Table 16] ■ 0030 ■

[Table 17] ■ 0031 ■

[Table 18] ■ 0032 ■

[Table 19] ■ 0033 ■

[Table 20] ■ 0034 ■

[Table 21] ■ 0035 ■

[Table 22] ■ 0036 ■

[Table 23] ■ 0037 ■

[Table 24] ■ 0038 ■

[Table 25] ■ 0039 ■

[Table 26] ■ 0040 ■

[Table 27] ■ 0041 ■

[Table 28] ■ 0042 ■

[Table 29] ■ 0043 ■

[Table 30] ■ 0044 ■

[Table 31] ■ 0045 ■

[Table 32] ■ 0046 ■

[Table 33] ■ 0047 ■

[Table 34] ■ 0048 ■

[Table 35] ■ 0049 ■

[Table 36] ■ 0050 ■

[Table 37] ■ 0051 ■

[Table 38] ■ 0052 ■

[Table 39] ■ 0053 ■

[Table 40] ■ 0054 ■

[Table 41] ■ 0055 ■

[Table 42] ■ 0056 ■

[Table 43] ■ 0057 ■

[Table 44] ■ 0058 ■

[Table 45] ■ 0059 ■

[Table 46] ■ 0060 ■

[Table 47] ■ 0061 ■

[Table 48] As described above, while the conventional CLA circuit is configured by a combination of logic gate circuits, in the present embodiment, a circuit capable of performing a dedicated CLA operation is formed by combining an N-type MOS transistor and a P-type MOS transistor. With the configuration, the number of transistors required to obtain the same function and the same performance as the conventional CLA circuit can be reduced.
That is, when this circuit is applied to an integrated circuit, the chip area of the circuit can be reduced.

Incidentally, when the carry transmission circuit of 8 bits is configured, the number of MOS transistors constituting the conventional CLA circuit is 104, whereas the configuration of the present embodiment requires only 69 transistors. Therefore, by applying the configuration of this embodiment, it is possible to achieve a reduction in the number of elements of about 35%, that is, a reduction in the chip occupation area.

FIG. 1 shows an embodiment in which the carry transmission circuit according to the present invention is applied to an increment circuit. However, as shown in FIG.
Insert an inverter into the signal system of D1 to D8, and carry C1.
By removing the inverter from the signal system of ~ C8,
As a configuration that operates in the opposite phase in the case of carry, the carry transfer circuit according to the present invention can be applied to a decrement circuit by using it as a borrow transfer circuit.

[0064]

As described above, according to the present invention, not a combination of logic gate circuits, but also a combination of an N-type MOS transistor and a P-type MOS transistor to form a circuit capable of performing a dedicated CLA operation. Provided is a carry transmission circuit that can reduce the number of transistors required to obtain the same function and performance as the conventional CLA circuit, and can reduce the chip area when applied to an integrated circuit. be able to.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of an 8-bit increment circuit to which a carry transmission circuit according to an embodiment of the present invention is applied.

FIG. 2 is a circuit configuration diagram showing a configuration of a decrement circuit using a borrow transmission circuit configured by applying the carry transmission circuit of the present invention, which is another embodiment according to the present invention.

FIG. 3 is a block diagram illustrating a configuration of a conventional increment circuit that handles 8-bit data using a CLA circuit.

[Explanation of symbols]

Latch circuit 3: EOR circuit 11; Carry transmission circuit CNT0 to CNT7; Data holding logic circuit block Q _{N0 to} Q _N8 ; N-type MOS transistor Q _{P11 to} Q _P18 , Q _{P21 to} Q _P28 , Q _{P32 to} Q _P38 , Q _P43 ~
Q _P48 , Q _{P54 to} Q _P58 , Q _{P65 to} Q _P68 , Q _{P76 to} Q _P78 ,
Q _P87 , Q _P88 , Q _P98 ; P-type MOS transistor

Claims (1)

(57) [Claims] 1. A source-drain (N +
1) N-type MOS transistors in which cascade-connected N-type MOS transistors are connected, and a reference potential is applied to one end of the series circuit of the source and the drain; and a reference potential side of the (N + 1) N-type MOS transistors The source-drain is connected in parallel between the drain of each N-type MOS transistor of the K-th (2 ≦ K ≦ N + 1) -th N-type MOS transistor from the second to (N + 1) th counted from the power supply potential and P-type MO with P-type MOS transistors connected in parallel
An S transistor circuit, and a (K-1) th data signal is input to the gate of the K-th N-type MOS transistor from the reference potential side of the N-type MOS transistor circuit, and the drain of the N-type MOS transistor (K-1) data signals and carry signals from the (K-1) th bit to the first bit are respectively applied to the gates of the K P-type MOS transistors of the P-type MOS transistor circuit connected to A carry transmission circuit for inputting the carry signal to a gate of an N-type MOS transistor connected to a reference voltage of the N-type MOS transistor circuit.