JP3088520B2 - Thermal head drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thermal head driving circuit for driving a thermal head used as a printing unit of a facsimile or a printer.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram showing a conventional one-dot thermal head drive circuit.
This thermal head drive circuit is prepared for a predetermined number of dots. In the figure, reference numeral 1 denotes a shift register that shifts input data of the current line according to a clock, and has a number of stages corresponding to the number of dots of the thermal head.

Reference numeral 2 denotes a latch circuit which captures and holds data appearing at the tap of the shift register 1;
It is a gate signal generator that generates two gate signals GA, GB, and GC. 4 is a latch output Q2, Q of the latch circuit 2.
3 and the gate signals GB, G from the gate signal generator 3.
Inverted logical product (hereinafter referred to as N
AND).

Reference numeral 5 denotes a logic circuit as a gate circuit for introducing the gate output of the NAND gate 4, the latch output Q1 of the latch circuit 2, and the gate signal GA from the gate signal generation unit 3 to output a pulse signal indicating a conduction state. Product (hereinafter,
AND). Reference numeral 6 denotes a Darlington transistor as a drive circuit for driving the heating resistor 7 of the thermal head in accordance with a pulse signal output from the AND gate 5.

Next, the operation will be described. Here, FIG.
FIG. 4 is a timing chart showing a time relationship between signals.

First, the shift register 1 captures data shown in FIG. 4B, which is an image signal, according to a clock signal shown in FIG. 4A, and shifts it. The latch circuit 2 sequentially takes in data from the tap of the shift register 1 corresponding to the dot in accordance with the latch signal shown in FIG.

At this time, the latch circuit 2 takes in data from the shift register 1 in response to the latch signal and shifts the latched data by one stage. As a result, the data of the dot of the previous line appears at the Q2 terminal of the latch 2 and the data of the dot of the line before the second appears at the Q3 terminal.

On the other hand, the gate signal generator 3 is provided, for example, in FIG.
As shown in (D), (E), and (F), gate signals GA, GB, and GC of a predetermined pattern are generated. The gate signals GA to GC and the output of the latch circuit 2 are Q1, Q
2, Q3, and the NAND gate 4 and the AND gate 5 determine the signal supplied to the heating resistor 7.

The Darlington transistor 6 uses the AND
The heating resistor 7 is driven in accordance with a signal from the gate 5, and the heating resistor 7 generates heat in accordance with the amount of current flowing by driving the Darlington transistor 6, thereby causing the heat-sensitive paper or the like located thereon to develop color. .

Here, the history control of the amount of current supplied to the heating resistor 7 will be described. As shown in FIG. 5A, the energizing time by the Darlington transistor 6 is 1 m.
In the case of s, the temperature of the heating resistor 7 becomes 300 ° C.
However, as shown in FIG. 5B, the repetition period is 2 ms.
Is repeated, the temperature rises to 500 ° C.

As described above, even when the same amount of current is applied, if the temperature at the start of energization is high, the temperature at the end of energization is high. That is, under the use condition in which the power is supplied at a fast repetition cycle, the color density becomes high unless the energy applied to the heating resistor 7 is controlled.

Therefore, it is necessary to control the amount of energy in accordance with the temperature at the start of energization. Specifically, energization is controlled based on whether or not recording was performed before the previous line.

In order to perform such a history control, how to apply energy to the dots of the current line based on the recording status of the dots of the previous line and the line before the next line,
In other words, in order to determine how to energize, it is necessary to know the degree of temperature rise for each pattern (recording state of the dot on the current line, the previous line, and the line before the previous line).

FIG. 6 is an explanatory diagram showing a simplified result of simulating a temperature rise in each pattern when the history control is not performed. In the figure, “H” indicates that recording (energization) has been performed, and “L” indicates that recording (energization) has not been performed. For example, FIG.
Indicates a case where recording is performed on the dot in the line before the previous line, and no recording is performed on the previous line.

Further, a value obtained by normalizing the temperature at the time when the energization is completed in the current line (this value indicates the degree of temperature increase, but this is called the number of points) is shown as a numerical value. For example, in the case shown in FIG. 6A, the point number is as small as "1.0" so that a large energy is given. In the case shown in FIG. 6D, the point number is "3.0". It is understood that history control should be performed so that small energy is given.

Next, the number of points shown in FIG. 6 and the latch data Q1, Q2, Q
Table 1 below shows the relationship with No. 3.

[0017]

[Table 1]

As described above, the latch data Q1, Q
2 and Q3 indicate whether the dot is recorded in the line before the previous line, the previous line, and the current line. Here, the number of levels is defined according to the number of “H”, and the higher the number of “H” appearing in the pattern, the higher the level.
4G to 4J show an example of an appropriate energization state according to the four types of patterns shown in Table 1. FIG.

In order to set an appropriate amount of current in accordance with the number of points, the gate signal generating unit 3 is provided with the gate signal generator shown in FIG.
Gate signals GA, GB, G as shown in (E) and (F)
C is generated. As a result, the output of the AND gate 5 according to the output pattern of the latch circuit 2 becomes as shown in FIGS. 4G to 4J, and the current amount according to the number of points is set.

That is, the pattern (L, L, H) having a small number of points is controlled to increase the amount of current, and the pattern having a large number of points is controlled to decrease the amount of current. You.

Normally, the pulse widths of the gate signals GB and GC are the same, and are within the same level, that is, level 2
For both patterns, the total energization time is the same.

References describing techniques related to such a conventional thermal head drive circuit include, for example, JP-A-63-203346 and JP-A-64-3.
No. 2973, Japanese Patent Application Laid-Open No. 64-67365 and the like.

[0023]

Since the conventional thermal head drive circuit is configured as described above, when the number of outputs of the latch circuit 2 is increased in order to perform the history control more strictly, the control object is not controlled. However, there is a problem that it is difficult to perform appropriate control because the number of patterns to be increased increases.

The present invention has been made in order to solve the above-described problems. Even if the number of patterns to be controlled is increased as a result of increasing the number of outputs of the latch circuit, the heating resistor may be used. It is an object of the present invention to obtain a thermal head drive circuit capable of executing history control for appropriately setting the heat generation amount of the semiconductor device with a smaller number of gate signals.

[0025]

According to the thermal head driving circuit of the present invention, a latch circuit is provided in a latch circuit before a current line.
Record information of at least the past 3 lines
Information as well as a small number of lines
At least three lines before the previous line
The first line group is the first front line group, and the other previous lines are the second front line group.
1st previous line group of the latch circuit
Of the second previous line group
And a matching circuit for outputting a signal for limiting the amount of current to the heating resistor according to the matching result.

[0026]

The collating circuit according to the present invention is a first circuit in a latch circuit for latching the recording information of the current line and the recording information of three or more past lines preceding the current line of the dot to be driven by the thermal head . In the previous line group
Constant latch output and one of the second previous line group
Against a latch output of, verification by the result to output a signal that limits the amount of current to the heating resistor in response to enables the calorific value of the control of the past record information referenced heating resistor and less A thermal head drive circuit capable of executing appropriate history control with the number of gate signals and appropriately setting the amount of heat generated by the heat generating resistor is realized.

[0027]

[Embodiment 1] An embodiment of the present invention will be described below with reference to the drawings. FIG.
1, 1 is a shift register, 4 is a NAND gate as a gate circuit, 5 is an AND gate as a gate circuit, 6 is a Darlington transistor as a drive circuit,
Reference numeral 7 denotes a heating resistor, which is the same as or a part corresponding to the conventional one denoted by the same reference numeral in FIG.

[0028] 8 in terms of holding the record information of the record information and the past seven lines of the current line, a different latch circuit from that reference numeral 2 in FIG. 3, in the embodiment 1, their
Q2 to Q5 among the past 7 lines are set as the second previous line group.
Then, Q6 to Q8 are classified as a first previous line group. 9
Are the gate signals GD and GE in addition to the gate signals GA to GC.
This is a gate signal generator different from that denoted by reference numeral 3 in FIG.

Reference numeral 10 compares the latch outputs Q6, Q7, and Q8 of the first preceding line group of the latch circuit 8 with the latch outputs Q3 of the second preceding line group of the latch circuit 8 and determines the collation result. This is a matching circuit that outputs a signal for limiting the amount of current to the heating resistor in response. This matching circuit 10
In the figure, reference numeral 11 denotes A in which the latch outputs Q6 to Q8 are introduced.
An ND gate (logic gate) 12 is a logical sum (hereinafter referred to as O ) of the output of the AND gate 11 and the latch output Q3.
R) (logical gate) .

Next, the operation will be described. Latch circuit 8
Captures data of recording information from the shift register 1 in accordance with a latch signal, similarly to the conventional latch circuit 2. In this case, since the latch circuit 8 has an eight-stage configuration,
The recording information one line before appears at the Q2 terminal, the recording information two lines before the Q3 terminal, the recording information three lines before the Q4 terminal, and so on. Appear in each.

Here, when there are four types of patterns to be controlled as in the conventional case, the patterns shown in FIGS.
As shown in (J), using the three types of gate signals GA to GC, if the pattern is (H, L, H), the gate signal G
The energization control is simple, such as controlling with A, GB, and controlling the pattern (L, H, H) with the gate signals GA, GB, GC.

However, when the current line energization control is performed on the dot in consideration of the control information of the past four lines, the types of patterns to be controlled are increased to 16 types as shown in Table 2 below. I do.

[0033]

[Table 2]

As described above, when the pattern to be controlled is 16
When there are five types of gate signals of GA to GE, energization control can be performed if there are five types of patterns. However, when more types of patterns are to be controlled, the number of output signal lines of the gate signal generation unit 9 is reduced. And the control method becomes unrealistic.

Therefore, in this embodiment, for the latch output after the latch output Q6, only the record information of a specific pattern is collated with the predetermined latch output via the collation circuit 10 in the past. Energization control is being performed.

For example, if it is a bar code pattern,
There are five thick bars and two thin bars, and the pattern has regularity. Therefore, as shown in FIGS. 2A and 2B, the recording information of the latch outputs Q1 to Q5 is the same, but the recording information of the latch outputs Q6 to Q8 is completely different.
Therefore, in such a case, if the energization control is performed only by the latch outputs Q1 to Q5, a current for generating the same amount of heat is supplied to the heat generating resistor 7.

Therefore, in this embodiment, the first front line
The latch outputs Q6 to Q8 of the group of signals are sent to the collating circuit 10, and they are collectively input to the AND gate 11 to be ANDed.
2 is input to the OR gate 12 and is compared with the latch output Q3 of the second previous line group .
When the latch outputs Q6, Q7, and Q8 are all black (H) as in (A), the output of the NAND gate 4, to which the signal from the OR gate 12 is input, is the output period of the gate signal GD (H period). Be sure to turn off the middle. By doing this,
If a long black (H) print has been made in the past and the amount of accumulated heat is large, the energy supply period of the calorific value is shortened.

On the other hand, when at least one of the latch outputs Q6, Q7, and Q8 has white (L), the output of the AND gate 11 in the verification circuit 10 goes low, and the OR gate 12
Pass the latch output Q3 as it is. Therefore, energization control is performed on the heating resistor 7 in accordance with the pattern of the latch outputs Q1 to Q5.

As described above, FIG.
FIG. 2 with the pattern shown in (B) and black bars continuing in the past
In the pattern shown in FIG. 2A, obviously, the pattern shown in FIG. 2A should have more heat accumulation, but even in such a case, the number of output signal lines of the gate signal generator 9 is reduced. It is possible to cope without increasing.

Embodiment 2 FIG. In the above embodiment, the latch outputs Q6 to Q8 of the first preceding line group are put together and the AND gate 11
Is shown, and the energization control is performed by comparing with the latch output Q3. However, the number of latch outputs to be input to the AND gate 11 does not need to be three, and can be arbitrarily changed to one or more. , The output of the OR gate 12 of the matching circuit 10 is also a specific one other than the latch output Q3 of the second previous line group.
You may make it collate with more than three latch outputs.

Embodiment 3 FIG. In the above embodiment, the matching circuit 10 is connected to the AND gate 1
1 and the OR gate 12 have been described, but other logical circuits may be used, and the same effects as in the above embodiment can be obtained.

[0042]

As is evident from the foregoing description, according to the present invention, rat
In the switch circuit, as the record information of the line before the current line,
At least record information of the last three lines
At least three of the previous lines
The line before going back is set as the first front line group, and
Other previous lines as a second previous line group,
A predetermined latch output from the first previous line group of the latch circuit
Output to one of the latches of the second previous line group.
And controls the amount of current to the heating resistor according to the matching result.
Since it is configured to so that provided a matching circuit for outputting a signal to limit enables the calorific value of the control of the past record information referenced heating resistor, and even when the number of patterns to be controlled is large, the gate signal There is an effect that a thermal head drive circuit that can execute appropriate history control without increasing the number of gate signals generated by the generation unit is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a thermal head drive circuit according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an example of a barcode pattern for explaining the operation of the embodiment.

FIG. 3 is a block diagram showing a conventional thermal head drive circuit.

FIG. 4 is a timing chart for explaining the operation.

FIG. 5 is an explanatory diagram showing a relationship between an applied pulse of a heating resistor and a temperature.

FIG. 6 is an explanatory diagram schematically showing a temperature rise in four types of latch patterns.

[Explanation of symbols]

 Reference Signs List 4 Gate circuit (NAND gate) 5 Gate circuit (AND gate) 6 Driving circuit (Darlington transistor) 7 Heating resistor 8 Latch circuit 9 Gate signal generator 10 Collation circuit

Claims (1)

(57) [Claims] 1. A latch circuit for holding recording information of a current line and recording information of a line preceding the current line in dots to be driven by the thermal head, and the thermal head based on an output pattern of the latch circuit. A gate circuit for outputting a pulse signal indicating the energized state of the heating resistor of the dot to be driven, and the gate circuit generating a pulse signal indicating the energized state of the heating resistor based on the output pattern of the latch circuit A gate signal generator for generating a gate signal for supplying the gate signal to the gate circuit, and according to a pulse signal output from the gate circuit,
A driving circuit for driving the heating resistor, wherein the latch circuit holds at least the past three lines of recording information as the recording information of the line preceding the current line, and , The line preceding at least three lines after the previous line is defined as a first preceding line group, and the other preceding lines are classified as a second preceding line group, and the first preceding line of the latch circuit is divided. A predetermined latch output of the group
A collation circuit comprising a logic gate for collating with any one of the latch outputs of the second previous line group and outputting a signal for limiting the amount of current to the heating resistor according to the collation result; A thermal head drive circuit characterized by the following.