JP3087189B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP3087189B2
JP3087189B2 JP03212103A JP21210391A JP3087189B2 JP 3087189 B2 JP3087189 B2 JP 3087189B2 JP 03212103 A JP03212103 A JP 03212103A JP 21210391 A JP21210391 A JP 21210391A JP 3087189 B2 JP3087189 B2 JP 3087189B2
Authority
JP
Japan
Prior art keywords
oxide film
sio
heat treatment
film
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP03212103A
Other languages
Japanese (ja)
Other versions
JPH0555200A (en
Inventor
俊郎 中西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP03212103A priority Critical patent/JP3087189B2/en
Publication of JPH0555200A publication Critical patent/JPH0555200A/en
Application granted granted Critical
Publication of JP3087189B2 publication Critical patent/JP3087189B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、酸化膜の耐圧強度を高
めることにより、長期間の電界印加においても酸化膜の
絶縁破壊の発生を防止して、長期信頼性を高めた半導体
装置の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which the breakdown voltage of an oxide film is increased to prevent occurrence of dielectric breakdown of the oxide film even when an electric field is applied for a long time, thereby improving long-term reliability. About the method.

【0002】[0002]

【従来の技術】近年のコンピュータシステムの高度化に
伴い、その頭脳となるLSIは益々信頼性を向上するこ
とが要求されている。特に長期の運転において半導体素
子中の絶縁膜に絶縁破壊が発生することはシステムにと
って致命的となるため種々の対応策が講じられている。
典型的には、LSIの製造プロセスはクリーン化を図
り、絶縁膜に粒子レベルあるいは原子レベルの不純物が
混入しないように努力がなされている。
2. Description of the Related Art With the advancement of computer systems in recent years, it has been demanded that LSIs, which are the brains of such systems, have higher reliability. In particular, various measures have been taken since the occurrence of dielectric breakdown in the insulating film in the semiconductor element during long-term operation is fatal to the system.
Typically, efforts are made to clean the LSI manufacturing process and to prevent impurities at the particle level or the atomic level from entering the insulating film.

【0003】一般に、半導体素子のMOS構造を作成す
る場合、ゲート酸化膜や蓄積キャパシター酸化膜を酸素
雰囲気下での熱処理により形成し、その上部に多結晶S
i(ポリシリコン)等の電極を堆積させる。ところが、
素子が微細化されるほど酸化膜に加わる電界が高くな
り、絶縁破壊を引き起こしやすくなる。
In general, when fabricating a MOS structure of a semiconductor device, a gate oxide film and a storage capacitor oxide film are formed by a heat treatment in an oxygen atmosphere, and a polycrystalline S
An electrode such as i (polysilicon) is deposited. However,
As the element is miniaturized, the electric field applied to the oxide film becomes higher, and dielectric breakdown is more likely to occur.

【0004】絶縁破壊の原因の一つに、酸化膜中に取り
込まれた重金属不純物がある。重金属不純物による絶縁
破壊の典型的なメカニズムを、図3を参照して説明す
る。同図はSi基板31上にSiO2 の酸化膜32を形
成し、その上に多結晶Siの電極層33を形成した構造
を示す。まず同図(A)は、酸化膜32中に取り込まれ
た重金属(M)が膜中で遊離金属原子の形で析出物34
を形成した場合で、この析出物34で基板31と電極3
3とが短絡することによる絶縁破壊である。酸化膜中で
の析出の発生は、酸化膜中への重金属元素の固溶度の大
きさによって左右される。酸化膜中の固溶度の小さい金
属、例えばSiO2 中のFeは析出し易く、SiO2
の耐圧強度を低下させる原因になる。
[0004] One of the causes of dielectric breakdown is heavy metal impurities taken into the oxide film. A typical mechanism of dielectric breakdown caused by heavy metal impurities will be described with reference to FIG. FIG. 2 shows a structure in which an SiO 2 oxide film 32 is formed on a Si substrate 31 and a polycrystalline Si electrode layer 33 is formed thereon. First, FIG. 3A shows that heavy metal (M) taken in oxide film 32 is deposited in the form of free metal atoms in the precipitate 34 in the film.
In this case, the substrate 34 and the electrode 3 are
3 is a dielectric breakdown caused by a short circuit. The occurrence of precipitation in the oxide film depends on the solid solubility of the heavy metal element in the oxide film. A metal having a low solid solubility in an oxide film, for example, Fe in SiO 2 is easily precipitated, which causes a reduction in the pressure resistance of the SiO 2 film.

【0005】次に同図(B)の場合は、酸化膜32中に
取り込まれた重金属(M)が、その後の工程で熱処理を
受けた際に、酸化膜32のSiO2 の酸素と結合して金
属酸化物(MO)35を形成し、その結果Si原子36
が掃き出されて酸化膜32中に過剰に存在するようにな
り、絶縁破壊を生ずる。一般に問題となる不純物金属
(Al、Fe、Cu、Ni、Co、Cr、Mn)につい
て、この結合・掃き出し反応は次のように起こる。
Next, in the case of FIG. 1B, the heavy metal (M) taken in the oxide film 32 is combined with oxygen of SiO 2 of the oxide film 32 when subjected to a heat treatment in a subsequent step. To form a metal oxide (MO) 35, resulting in Si atoms 36
Is swept out and becomes excessively present in the oxide film 32, causing dielectric breakdown. For impurity metals (Al, Fe, Cu, Ni, Co, Cr, Mn), which are generally problematic, this binding / sweeping-out reaction occurs as follows.

【0006】 4/3Al+SiO2 →2/3Al2 3 +Si 3/2Fe+SiO2 →1/2Fe3 +Si 4Cu+SiO2 →2Cu2 O+Si 2Ni+SiO2 →2NiO+Si 2Co+SiO2 →2CoO+Si 4/3Cr+SiO2 →2/3Cr2 3 +Si 2Mn+SiO2 →2Mn+Si 上記反応で掃き出されたSi原子が酸化膜の導電率を上
げ耐圧強度を下げる。
4 / 3Al + SiO 2 → 2 / 3Al 2 O 3 + Si 3 / 2Fe + SiO 2 → 1 / 2Fe 3 + Si 4Cu + SiO 2 → 2Cu 2 O + Si 2Ni + SiO 2 → 2NiO + Si 2Co + SiO 2 → 2CoO + Si 4 / 3Cr + SiO 2 → 2 / 3Cr 2 O 3 + Si 2 Mn + SiO 2 → 2Mn + Si The Si atoms swept out by the above reaction increase the conductivity of the oxide film and lower the breakdown voltage strength.

【0007】そこで、重金属汚染を低減するために、使
用するガス、薬品、材料の高純度化を図り汚染物質の付
着を防止することと、付着した汚染物質を洗浄によって
除去することが行われている。
Therefore, in order to reduce heavy metal contamination, it is necessary to purify gases, chemicals and materials used to prevent the adhesion of contaminants, and to remove the adhered contaminants by washing. I have.

【0008】[0008]

【発明が解決しようとする課題】しかし、汚染物質の付
着を防止するためには、装置を含めて総合的に高純度化
を図る必要があり、また洗浄には付着物除去作用と同時
に望ましくないエッチング作用が伴う。このように、耐
圧不良の少ない酸化膜を得るためには、汚染物質の付着
防止に多大な投資と時間と手間がかかる。また汚染除去
効果のある洗浄を仕手も表面のエッチング量をコントロ
ールする必要があり、表面形状の乱れを引き起こすとい
う難点も考慮しなくてはならない。
However, in order to prevent contaminants from adhering, it is necessary to purify the entire system including the apparatus, and it is not desirable to clean the apparatus simultaneously with the action of removing the contaminants. Etching is involved. As described above, in order to obtain an oxide film with a low withstand voltage, a great deal of investment, time, and effort are required to prevent the adhesion of contaminants. In addition, it is necessary for the operator to control the amount of etching of the surface for cleaning having an effect of removing contamination, and it is necessary to consider the difficulty of causing surface shape disorder.

【0009】本発明は、多大な投資や手間と時間を要さ
ず、望ましくないエッチング作用も伴わずに、絶縁破壊
が生じにくい酸化膜を形成できる半導体装置の製造方法
を提供することを目的とする。
An object of the present invention is to provide a method of manufacturing a semiconductor device capable of forming an oxide film which is less likely to cause dielectric breakdown without requiring a large investment, labor and time, and without an undesirable etching action. I do.

【0010】[0010]

【課題を解決するための手段】上記の目的を達成するた
めに、本発明の半導体装置の製造方法は、半導体基板上
ゲート酸化膜または蓄積キャパシター酸化膜としての
酸化膜を形成する工程、および該酸化膜に10 12 cm -2
超え10 16 cm -2 未満のドーズ量で酸素イオンを注入した
後に熱処理することにより、該酸化膜中に存在する遊離
金属原子を酸化物とする工程を含むことを特徴とする。
In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises forming an oxide film as a gate oxide film or a storage capacitor oxide film on a semiconductor substrate. And applying 10 12 cm -2 to the oxide film.
A step of implanting oxygen ions at a dose of more than 10 16 cm -2 and then performing a heat treatment to convert free metal atoms present in the oxide film into oxides.

【0011】[0011]

【作用】本発明は、イオン注入により酸素を酸化膜中に
導入し、その後に熱処理することによって、酸化膜中に
不純物として存在する遊離状態の金属原子を酸化物とす
ると同時に半導体元素が原子の形で掃き出されることを
防止して、前記(A)遊離不純物金属の析出による短絡
作用および(B)掃き出された半導体原子による短絡作
用を共に防止する。
According to the present invention, oxygen is introduced into an oxide film by ion implantation, and then heat treatment is performed to convert free metal atoms present as impurities in the oxide film into oxides, and at the same time, the semiconductor elements are converted into atoms. And (B) the short-circuit effect due to the precipitation of the free impurity metal and (B) the short-circuit effect due to the swept-out semiconductor atoms.

【0012】図2は、SiO2 からなる酸化膜の場合を
例にして、本発明の原理を説明する模式図である。まず
同図(a)に示すように、イオン注入によりSiO2
中に酸素(O)を導入して、不純物金属元素(M)が存
在するSiO2 ネットワーク中に、この導入された酸素
(O)が付加された状態にする。
FIG. 2 is a schematic view illustrating the principle of the present invention, taking an oxide film made of SiO 2 as an example. First, as shown in FIG. 2A, oxygen (O) is introduced into the SiO 2 film by ion implantation, and the introduced oxygen (O) is introduced into the SiO 2 network where the impurity metal element (M) exists. ) Is added.

【0013】この状態から熱処理をすることにより、同
図(b)に示すように、金属元素(M)は金属酸化物
(MO)を形成する。このとき、酸化膜のSiO2 はS
i原子として掃き出されることなく酸化物の形で維持さ
れる。この酸化物形成反応は、金属元素MがAl、F
e、Cu、Ni、Co、Cr、Mnである場合、それぞ
れ次のように起こる。
By performing heat treatment from this state, the metal element (M) forms a metal oxide (MO) as shown in FIG. At this time, the SiO 2 of the oxide film is S
It is maintained in the form of an oxide without being swept out as an i atom. In this oxide formation reaction, the metal element M is Al, F
In the case of e, Cu, Ni, Co, Cr, and Mn, the following occurs respectively.

【0014】 4/3Al+SiO2 +O2 →2/3Al2 3 +SiO2 3/2Fe+SiO2 +O2 →1/2Fe3 +SiO2 4Cu+SiO2 +O2 →2Cu2 O+SiO2 2Ni+SiO2 +O2 →2NiO+SiO2 2Co+SiO2 +O2 →2CoO+SiO2 4/3Cr+SiO2 +O2 →2/3Cr2 3 +SiO2 2Mn+SiO2 +O2 →2Mn+SiO2 このように、酸化膜中の不純物金属も酸化膜を構成する
SiO2 もいずれも酸化物の形で存在するようになるの
で、従来のように遊離金属原子の析出や掃き出された半
導体原子による短絡作用が生ずることがない。
4/3 Al + SiO 2 + O 2 → 2/3 Al 2 O 3 + SiO 2 3 / 2Fe + SiO 2 + O 2 → 1 / 2Fe 3 + SiO 2 4Cu + SiO 2 + O 2 → 2Cu 2 O + SiO 2 2Ni + SiO 2 + O 2 → 2NiO + SiO 2 2Co + SiO 2 + O 2 → 2CoO + SiO 2 4 / 3Cr + SiO 2 + O 2 → 2 / 3Cr 2 O 3 + SiO 2 2Mn + SiO 2 + O 2 → 2Mn + SiO 2 Thus, both the impurity metal in the oxide film and the SiO 2 constituting the oxide film are both oxides. Since it exists in the form, no precipitation of free metal atoms and no short-circuiting action by the swept-out semiconductor atoms occur as in the related art.

【0015】酸素イオン注入によるドーズ量は1013
1015cm-2程度とすることが適当である。1012cm-2
下では明瞭な効果が認められず、1016cm-2以上では酸
化膜中の欠陥が多くなり後の熱処理でも回復が困難にな
るので好ましくない。酸素イオン注入後に行う熱処理
は、900℃以下の温度で行うことが適当である。10
00℃以上の熱処理ではSiO2 表面およびSi/Si
2 界面に荒れを生ずるため効果が失われる。熱処理温
度の下限は特に定める必要はなく、900℃以下の温度
で効果の認められる範囲で適宜設定することができる。
熱処理時間は10〜30分程度で十分であり、通常、熱
処理雰囲気としては窒素ガス雰囲気等の不活性ガス雰囲
気を用いる。
The dose by oxygen ion implantation is 10 13 to
It is appropriate to be about 10 15 cm -2 . At 10 12 cm -2 or less, a clear effect is not recognized, and at 10 16 cm -2 or more, defects in the oxide film increase and recovery becomes difficult even by heat treatment, which is not preferable. It is appropriate that the heat treatment performed after the oxygen ion implantation be performed at a temperature of 900 ° C. or lower. 10
In a heat treatment of 00 ° C. or more, the SiO 2 surface and Si / Si
The effect is lost due to the roughening of the O 2 interface. The lower limit of the heat treatment temperature does not need to be particularly determined, and can be appropriately set within a range where the effect is recognized at a temperature of 900 ° C. or less.
A heat treatment time of about 10 to 30 minutes is sufficient. Usually, an inert gas atmosphere such as a nitrogen gas atmosphere is used as the heat treatment atmosphere.

【0016】以下に、実施例によって本発明を更に詳細
に説明する。
Hereinafter, the present invention will be described in more detail by way of examples.

【0017】[0017]

【実施例】図1(a)〜(c)を参照して、本発明に従
ってSiO2 膜を処理した例を説明する。まず同図
(a)に示したように、P型(100)Siウェハ11
を、1000℃、乾燥酸素雰囲気中で熱処理して、表面
に厚さ20nmの酸化膜(SiO2 膜)12を形成し
た。
1A to 1C, an example in which an SiO 2 film is processed according to the present invention will be described. First, as shown in FIG. 1A, a P-type (100) Si wafer 11 is formed.
Was heat-treated in a dry oxygen atmosphere at 1000 ° C. to form an oxide film (SiO 2 film) 12 having a thickness of 20 nm on the surface.

【0018】次に同図(b)に示したように、このSi
2 膜12に酸素イオン13を注入した。イオン注入条
件は、照射角度7°、注入エネルギー4keV 、ドーズ量
10 13cm-2であった。注入された酸素は、同図(c)に
示したようにSiO2 膜12の膜厚中央付近にRp(分
布のピーク)14を持つ状態で膜12中に存在する。酸
素イオン注入後、電気炉内、窒素ガス雰囲気中で800
℃、10分間の熱処理を行った。
Next, as shown in FIG.
OTwoOxygen ions 13 were implanted into the film 12. Ion implantation strip
The subject is an irradiation angle of 7 °, an implantation energy of 4 keV, and a dose amount.
10 13cm-2Met. The injected oxygen is shown in FIG.
As shown, SiOTwoIn the vicinity of the center of the film thickness of the film 12, Rp (min.
It is present in the film 12 in a state having a cloth peak) 14. acid
After implantation of elementary ions, 800 in an electric furnace and in a nitrogen gas atmosphere.
A heat treatment was performed at 10 ° C. for 10 minutes.

【0019】以上の処理を行って作製したMOS構造に
ついて、トンネルリーク電流の測定結果の一例をFowler
-Nordheim プロットで図4に示す。同図には比較のた
め、酸素イオン注入を行わなかったサンプルおよびイオ
ン注入ままのサンプルの結果も合わせて示した。同図横
軸のEは印加した電界強度を、縦軸のJは測定された電
流密度である。Fowler-Nordheim プロットが直線性を示
すことは、酸化膜中をトンネル電流が流れていることを
示す。
An example of the measurement result of the tunnel leak current of the MOS structure manufactured by performing the above processing is described in Fowler.
FIG. 4 shows a -Nordheim plot. For comparison, the figure also shows the results of a sample without oxygen ion implantation and a sample without ion implantation. In the figure, E on the horizontal axis indicates the applied electric field intensity, and J on the vertical axis indicates the measured current density. The linearity of the Fowler-Nordheim plot indicates that a tunnel current is flowing in the oxide film.

【0020】同図の結果から、本発明による処理を行っ
た場合は、電界強度E=10MV/cm(図中では1/E
=1×10-7cm/V)を印加した時の電流値が、処理な
しの場合に比べて約1/3に低減し、耐リーク特性が著
しく向上していることが分かる。図5(a)は、上記処
理を行って作製した180個のMOSダイオードの耐圧
強度のヒストグラムであり、同図(b)は本発明の処理
を行わない比較例についてのヒストグラムである。10
MV/cm以上の耐圧を持つ良品率は、処理なしの比較例
が69%であったのに対して、本発明の処理を行うこと
によって93%に向上した。
From the results shown in the figure, when the processing according to the present invention was performed, the electric field intensity E = 10 MV / cm (1 / E in the figure).
= 1 × 10 −7 cm / V), the current value is reduced to about 3 as compared with the case without the treatment, and it can be seen that the leak resistance is remarkably improved. FIG. 5A is a histogram of the breakdown voltage of the 180 MOS diodes manufactured by performing the above-described processing, and FIG. 5B is a histogram of a comparative example in which the processing of the present invention is not performed. 10
The non-defective product having a withstand voltage of MV / cm or more was improved to 93% by performing the treatment of the present invention, while the comparative example without treatment was 69%.

【0021】[0021]

【発明の効果】以上説明したように、本発明によれば、
酸素イオン注入と熱処理を行うことにより、多大な投資
や手間と時間を要さず、望ましくないエッチング作用も
伴わずに、酸化膜の耐圧強度を高めた半導体装置を製造
することができる。
As described above, according to the present invention,
By performing the oxygen ion implantation and the heat treatment, it is possible to manufacture a semiconductor device in which the breakdown voltage strength of the oxide film is increased without requiring a large investment, labor and time, and without an undesirable etching action.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に従って酸化膜の処理を行う工程の一例
を示す断面図である。
FIG. 1 is a cross-sectional view showing an example of a process for performing an oxide film treatment according to the present invention.

【図2】本発明に従って酸素イオン注入およびその後の
熱処理を行った状態の酸化膜の構造を原子レベルで示す
模式図である。
FIG. 2 is a schematic diagram showing, at an atomic level, a structure of an oxide film after oxygen ion implantation and subsequent heat treatment are performed according to the present invention.

【図3】酸化膜中に取り込まれた金属元素によって酸化
膜の絶縁破壊が生ずるメカニズムを模式的に示す断面図
である。
FIG. 3 is a cross-sectional view schematically showing a mechanism in which dielectric breakdown of an oxide film occurs due to a metal element taken into the oxide film.

【図4】本発明に従って酸化膜に酸素イオン注入および
その後の熱処理を行って作製したMOS構造のトンネル
リーク電流の挙動を、酸素イオン注入をせずに作製した
従来のMOS構造および酸素イオン注入ままで熱処理は
せずに作製したMOS構造の場合と比較して示すグラフ
である。
FIG. 4 shows the behavior of a tunnel leak current of a MOS structure fabricated by performing oxygen ion implantation and subsequent heat treatment on an oxide film according to the present invention, as compared with a conventional MOS structure fabricated without oxygen ion implantation and oxygen ion implantation. 7 is a graph showing a comparison with a MOS structure manufactured without heat treatment.

【図5】本発明に従って酸化膜に酸素イオン注入および
その後の熱処理を行って作製したMOSダイオードの耐
圧強度の出現頻度を、酸素イオン注入を行わない従来の
場合と比較して示すグラフである。
FIG. 5 is a graph showing the appearance frequency of the breakdown voltage strength of a MOS diode manufactured by performing oxygen ion implantation and subsequent heat treatment on an oxide film according to the present invention, as compared with a conventional case in which oxygen ion implantation is not performed.

【符号の説明】[Explanation of symbols]

11…P型(100)Siウェハ 12…酸化膜(SiO2 膜) 13…酸素イオンビーム 14…酸化膜12中に注入された酸素の分布ピーク位置 21…Si原子 22…酸素原子 23…金属原子 31…Si基板 32…酸化膜(Si膜) 33…多結晶Si膜(ポリシリコン膜) 34…析出金属(M) 35…金属酸化物(MO) 36…掃き出されたSi原子11 ... P-type (100) Si wafer 12 ... oxide film (SiO 2 film) 13 ... oxygen ion beam 14 ... distribution peak position 21 ... Si atoms 22 ... oxygen atom 23 ... metal atom of oxygen injected into the oxide film 12 DESCRIPTION OF SYMBOLS 31 ... Si substrate 32 ... Oxide film (Si film) 33 ... Polycrystalline Si film (polysilicon film) 34 ... Deposited metal (M) 35 ... Metal oxide (MO) 36 ... Sweeped Si atoms

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 半導体基板上にゲート酸化膜または蓄積
キャパシター酸化膜としての酸化膜を形成する工程、お
よび該酸化膜に10 12 cm -2 を超え10 16 cm -2 未満のドー
ズ量で酸素イオンを注入した後に熱処理することによ
り、該酸化膜中に存在する遊離金属原子を酸化物とする
工程を含むことを特徴とする半導体装置の製造方法。
A gate oxide film or accumulation on a semiconductor substrate
Forming an oxide film as a capacitor oxide film, and oxide film to 10 12 cm -2 to exceed 10 16 cm -2 than the dough
A method of manufacturing a semiconductor device, comprising the step of: converting a free metal atom present in an oxide film into an oxide by performing a heat treatment after implanting oxygen ions in a small amount .
【請求項2】 前記酸素イオン注入によるドーズ量を1
13〜1015cm-2とし、前記熱処理を900℃以下の温
度で行うことを特徴とする請求項1記載の半導体装置の
製造方法。
2. The method according to claim 1, wherein a dose of said oxygen ion implantation is 1
0 13 ~10 15 cm -2 and then, the method of manufacturing a semiconductor device according to claim 1, characterized in that the heat treatment at 900 ° C. or lower.
JP03212103A 1991-08-23 1991-08-23 Method for manufacturing semiconductor device Expired - Fee Related JP3087189B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP03212103A JP3087189B2 (en) 1991-08-23 1991-08-23 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP03212103A JP3087189B2 (en) 1991-08-23 1991-08-23 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH0555200A JPH0555200A (en) 1993-03-05
JP3087189B2 true JP3087189B2 (en) 2000-09-11

Family

ID=16616935

Family Applications (1)

Application Number Title Priority Date Filing Date
JP03212103A Expired - Fee Related JP3087189B2 (en) 1991-08-23 1991-08-23 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP3087189B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101432766B1 (en) 2006-05-26 2014-08-21 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device and manufacturing method thereof
JP2013254794A (en) * 2012-06-05 2013-12-19 Fujitsu Ltd Manufacturing method of oxide film

Also Published As

Publication number Publication date
JPH0555200A (en) 1993-03-05

Similar Documents

Publication Publication Date Title
CA1061915A (en) Method of fabricating metal-semiconductor interfaces
JP3105770B2 (en) Method for manufacturing semiconductor device
EP0758796A1 (en) A process for semiconductor device fabrication
US4243865A (en) Process for treating material in plasma environment
JP3087189B2 (en) Method for manufacturing semiconductor device
CA1243133A (en) Method of manufacturing a semiconductor device, in which a double layer-consisting of poly si and a silicide-present on a layer of silicon oxide is etched in a plasma
JPH0629314A (en) Semiconductor device and manufacture thereof
JP2776583B2 (en) Semiconductor substrate processing solution and processing method
Takano et al. Chemical oxide passivation for very thin oxide formation
Henley et al. Effects of iron contamination in silicon on thin oxide breakdown and reliability characteristics
JP3416716B2 (en) Method for forming oxide film on semiconductor substrate surface
Choi et al. Cleaning of Si and properties of the HfO 2–Si interface
Hao et al. Surface cleaning effect on dielectric integrity for ultrathin oxynitrides grown in N2O
Ohmi et al. Influence of silicon wafer surface orientation on very thin oxide quality
US5021358A (en) Semiconductor fabrication process using sacrificial oxidation to reduce tunnel formation during tungsten deposition
JPH0682652B2 (en) Method for forming silicon thermal oxide film
JP2834344B2 (en) Method for manufacturing insulating film of semiconductor device
JPS609166A (en) Manufacture of semiconductor device
Dori et al. Moderate‐temperature anneal of 7‐nm thermal SiO2 in O2‐and H2O‐free atmosphere: Effects on Si‐SiO2 interface‐trap distribution
Wong et al. Direct tungsten on silicon dioxide formed by RF plasma-enhanced chemical vapor deposition
EP0194569B1 (en) Thin-film layer structure with a reactive intermediate layer for integrated circuits
Rai et al. Current transport phenomena in SiO2 films
JPH03183132A (en) Manufacture of semiconductor device
JPS5988830A (en) Semiconductor structure
JP3523016B2 (en) Method for manufacturing semiconductor device

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20000523

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080714

Year of fee payment: 8

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090714

Year of fee payment: 9

LAPS Cancellation because of no payment of annual fees