JP3085267B2 - Memory access acceleration device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for speeding up memory access, and more particularly to a method and apparatus for speeding up memory access for improving a system processing performance by improving a gap in access speed between a main memory and a cache memory. About.

[0002]

2. Description of the Related Art In recent years, a technology for using a cache memory in an information processing apparatus has become popular due to an increase in demand for higher integration and higher speed of LSI. The principle of the cache memory is to store a copy of the main memory in a high-speed and small-capacity buffer memory using the locality of the access address,
It is to improve the main memory access speed in a pseudo manner.

On the other hand, there is a problem that the access delay of the main storage device is becoming relatively large with the increase in the speed of the machine clock of the CPU. That is,
There is no problem while hitting the cache memory, but once a cache miss occurs, the delay in data acquisition is large, which has been a barrier to performance improvement.

[0004] In addition, High Performance
In the Computing (hereinafter, referred to as HPC) area, a large amount of data which is discrete and refers to the entire main memory is handled. In such an application, the data stored in the cache is replaced with other data before the data read from the main memory is reused, and the cache memory is assumed to have access locality. There is a problem that the effect is difficult to obtain.

As described above, all of the conventional cache memories operate passively from the time of receiving a request, and it was impossible to reduce the frequency of cache misses, but it was impossible to eliminate them. However, if the next request to be generated can be predicted, it is possible to issue a request to the main storage device in advance and hide the performance degradation due to a cache miss. Further, since the cache miss becomes inconspicuous, it becomes possible to reduce the capacity of the cache, which conventionally occupies a large area, and it is also useful for improving the machine clock and reducing the area of the LSI.

[0006] Improvements and ideas have been repeatedly made based on such ideas. For example, JP-A-6-5198
Japanese Patent Application Laid-Open Publication No. 2002-115873 describes a technique for predicting the next access address from a cache miss address using an arithmetic processing unit stopped during a cache miss.

[0007] The prediction of the access address according to the present invention has the advantage that it can flexibly cope with various systems by changing the handler code executed at the time of a cache miss, but within the time when data returns from the main memory. If the execution of the handler code is not completed, the processing time will be rather long.

In recent cache memory systems, a technique for reducing the idle time of an arithmetic processing unit itself due to a cache miss by adopting a non-blocking cache has become widespread. There is also a problem that free time cannot always be secured.

In Japanese Patent Application Laid-Open No. 4-52741,
A technique has been described in which data of an expected address is previously loaded into a cache memory by an instruction. According to the present invention, there is an advantage that since a program can instruct a data load of a necessary address in advance, a cache miss can be concealed by performing an appropriate program, and unnecessary cache load can be eliminated. On the other hand,
Since it is necessary to analyze a program and explicitly instruct an expected address to be cache-loaded, there is a disadvantage that tuning of the program is troublesome.

Japanese Patent Application Laid-Open No. 3-292548 describes a technique for checking whether a continuous cache block is registered in a cache due to a cache miss, and loading the cache block in advance if the cache block is not registered. I have. The present invention has an advantage that it has a very simple structure and can be easily introduced into an existing system. On the other hand, there is no guarantee that a block following a cache miss block is used, and there is access to an evicted cache block. In some cases, the performance may be degraded.

[0011]

The above-described conventional memory access method is common in that expected data is read from a main memory in advance, but the method of realizing the method requires rewriting of a program. There are many difficult points in introducing such as large side effects. Further, there is a point that some modification must be made to the entire processor including the cache memory.

In the field of HPC in recent years, there have been many cases where a system is constructed using an existing microprocessor, rather than developing a new system from a processor.
This means that the performance of the microprocessor is not inferior to that of the dedicated processor, the cost performance is excellent, and the like, but it also means that it is difficult to perform hardware tuning for the HPC field. .

An object of the present invention is to consider the above points, eliminate the need to rewrite a program, reduce side effects,
Another object of the present invention is to provide a memory access speed-up method and apparatus which can be applied to an existing microprocessor.

[0014]

[0015]

[0016]

According to the present invention, there is provided a memory access speed-up device , comprising: a first buffer for holding a past memory access address history; Means for calculating the distance between some or all of the address history that has been entered,
A second buffer for holding the distance and matches the number of the first address stored in the buffer and previous one or more addresses, stored in the addresses and the first buffer upon a new memory access Past memory
When the distance from one of the access addresses coincides with at least one of the distances corresponding to past memory accesses held in the second buffer, means for storing the number of matches corresponding to the combination of the accesses Means for issuing continuous access at the distance when the number of matches reaches a predetermined number.

Further, in the memory access speed-up device of the present invention, there is provided a means for stopping the continuous access when the continuously accessed data is not used.

Further, the memory access speed-up device of the present invention is configured such that data accessed continuously is stored in a temporary storage buffer and not directly stored in a cache memory.

Further, in the memory access speed-up device of the present invention, there is provided means for ignoring the exception even if an exception occurs during the continuous access.

That is, the present invention provides means for reading predicted data into a buffer in advance when accessing data on the main memory at regular intervals. Vector processing for accessing data on the main memory at equal intervals frequently appears in scientific and technical calculations. However, since data accesses at equal intervals are not continuously output as well as operand accesses, the regularity of addresses repeatedly output at the same interval is extracted from various noises with high accuracy.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the principle of the present invention. In the figure, the memory access speed-up device according to the present invention checks the regularity of the access address for the past four memory accesses. Registers D9 and E
9, F9 and G9 correspond to the first buffer of claim 3 and store past memory access addresses. In this example, each time the memory is accessed, the registers D9, E9, F
Since 9 and G9 are strobed, the immediately preceding access address is stored in the register D9 and the immediately preceding access address is stored in the register E9.

When a new memory access occurs, the address of the memory access and the registers D9, E9, F
9, G9, that is, the difference (distance) from the past memory access address is calculated by the subtracters D, E, F, and G. The calculation result is stored in registers D0, D1, D2, and D3 corresponding to a part of the second buffer according to claim 3, and is compared with the distance calculated at the time of past memory access.

For example, the distance between the register D9 and the current memory access address is determined by the registers D0, D1, D2, D
3 is compared with the distance calculated at the time of the last two-time memory access. If there is a matching distance, it means that memory access has been performed at equal intervals in the current and previous accesses and in the previous and last two accesses, and it is predicted that there is a high probability that the memory will be accessed at the same intervals next time.

When a distance match is detected, the count value of the match number buffer is incremented by one and stored in the corresponding buffer. Arithmetic units-0, 1, 2, and 3 shown in FIG. 2 realize this function.

FIG. 3 is an explanatory diagram showing the operation of the arithmetic unit-0. In the figure, a computing unit-0 includes comparators C0, C
1, a comparison result of C2 and C3 is input. If the distances of the memory access addresses do not match, the output of the comparator becomes "0". As a result, the value "1" is output from the arithmetic unit-0 and set in the register D4. In other words, as long as the data is recorded in the buffer, it means that no access has been made at the same memory access address distance.

When the distances of the memory access addresses match, the output of the comparator becomes "1". For example, the comparator C0
When the distances of the memory access addresses match, the count value of the match count buffer set in the register D4 is incremented by 1, and the result is set in the register D4. The original value of register D4 is copied to register E4.

When the value of the number of matches exceeds a predetermined number, a continuous memory access request is issued by a circuit (not shown).

The contents of the registers D0, D1, D2, and D3 are copied to the registers E0, E1, E2, and E3 at the same time that the distance of the latest memory access address is stored. At the same time, the values of registers E0, E1, E2, E3 are copied to registers F0, F1, F2, F3.
Registers F0, F1, F2, F3, G0, G1, G2
The same applies to G3.

By the above operation, the registers D0, D
1, D2 and D3 always store the distance of the memory access address corresponding to the register D9. Register E
0, E1, E2, E3, F0, F1, F2, F3, G
The same applies to 0, G1, G2, and G3.

FIG. 4A is an example of a simple program for accumulating the contents of a two-dimensional array and converting it into a primary array. The program is composed of a double D0 loop. In the inner loop, the range of J of B (J, I) from 1 to 10 is accumulated and substituted into A (I).

When this program is replaced with assembly language, the result is as shown in FIG. The innermost circumference of the loop is L
ABEL2 to END, during which the load instruction from the main memory to the register is given by the formulas (1) to (4).
Appears four times. Equation (1), Equation (2), Equation (4)
, The address on the main storage device does not change at the innermost circumference of the loop, but the address in Expression (3) changes every time.

In the case of a two-dimensional array, the addresses on the main memory are generally as shown in FIG. That is, B (1,
The address following 1) is B (1,2). If one element of the array is 8 bytes, B (2,1) becomes B (1,1).
10x8 Bytes away from In the program shown in FIG. 4, the access order of the array B (I, J) is the black position in FIG.
Access to a distant address will occur.

FIG. 6 shows how the register values of FIGS. 1 and 2 change every time the circuit goes around the innermost loop. The addresses in the main memory where the variables are stored are as follows: address 0 in the main memory of I, address 8 in the main memory of J, address 100 in the start address of A (I), B (J, It is assumed that the start address of I) is 200.

In the first loop (see FIG. 6A),
No special operation is performed because no history is recorded in the buffer. In the second loop (see FIG. 6B), the operation is slightly different from the first loop because the history of the previous loop remains. Following the address of B (1,1) (address 200), the address of A (1) (100
Since the address (address 0) and the address I (address 0) were accessed by skipping address 100, it is recorded that the third consecutive access was performed at a distance of -100. As described above, even if the access is not always regular, if the access intervals of the addresses become equal, a record remains on the buffer as an access at equal intervals.

In the third loop (see FIG. 6C),
B (J,
I) is recorded on the register as accesses at equal intervals. In the first loop, address 200 is accessed, in the second loop, address 280, and in the third loop, address 360, and regular access is made at address intervals of 80. At the fourth time in the loop (see FIG. 6D), the count value at which a match is detected indicates 3, and it is predicted that access will be repeated at the same interval.

As long as the address output from the processor is monitored, requests issued at the same distance are once in four times, and it is difficult to determine the regularity of the address of B (I, J) with a simple circuit. If the memory access speed-up method of the present invention is adopted, even in such a case, the regularity of the address to be accessed next can be determined from the regularity of the access address.

FIG. 7 is a block diagram showing an example of an information processing apparatus employing the high speed memory access method of the present invention. In the figure, a processor 1 is a cache memory 2
It is assumed that the contents of the cache cannot be rewritten by an external circuit because of the built-in control function.
For this reason. Based on the regularity of access, data read in advance from the main storage device 4 is stored in a temporary storage device called a buffer memory 3.

When a miss occurs in the cache memory 2, the buffer memory 3 is searched for the corresponding data. If the data exists in the buffer memory, the data is not read from the main memory 4.
From the cache memory to the cache memory. Since reading data from the main storage device generally requires a considerably long time, this method of reading data in the buffer memory in advance has an effect of speeding up.

The bus between the processor 1 and the cache memory 2 is monitored by an address monitoring circuit 5 corresponding to the circuit shown in FIG. When regularity is detected in the monitored address, the request generation circuit 6 generates a pre-read request for the main storage device 4.

If the data read earlier is not used for a certain period of time, it is determined that the prediction of the access regularity is wrong, and the request generation circuit 7 interrupts the generation of the request. When the data read from the storage device is actually used by the processor, the generation of the request is continued.

It is conceivable that a request issued to the main storage device may cause an exception based on the prediction of the access regularity. If it is a memory access exception accompanying a request from the processor, it is necessary to interrupt the processor and perform the exception processing, but if the request is output to the main storage device based on the prediction of access regularity, an exception occurs should not be done. As described above, the circuit that suppresses the storage access exception according to the request source is the memory exception invalidation circuit 8.

[0043]

According to the present invention, since the address of memory access can be predicted with high accuracy, even if a program handles large-scale data that cannot be stored in the cache memory, the cache hit rate is reduced. The performance of the MPU can be brought out to the full without the need.

That is, in a program that handles large-scale data, data on an array is often accessed continuously according to a certain rule (distance). The access interval of the continuous access can be easily known by rewriting the software, but it is not easy to perform machine-specific tuning when porting a distribution application operating on a commercially available MPU. If higher performance than other machines using the same MPU can be achieved without software tuning, this can be a powerful means of differentiation. The present invention can be expected to have a great effect in a system using a commercially available MPU in which such differentiation is difficult.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing one embodiment of the present invention (continued).

FIG. 3 is an explanatory diagram showing the logic of a computing unit.

FIG. 4 is an explanatory diagram showing an example of an application program.

FIG. 5 is an explanatory diagram showing a processing operation of a two-dimensional array.

FIG. 6 is an explanatory diagram showing an operation example of the present invention.

FIG. 7 is a block diagram illustrating an example of an information processing apparatus to which the present invention has been applied.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Processor 2 Cache memory 3 Buffer memory 4 Main storage device 5 Address monitoring circuit 6 Request generation circuit 7 Request cancellation circuit 8 Memory exception invalidation circuit C0-C9, CA-CF Comparator D0-D9, E0-E9, F0-F9 , G0 to G9
register

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-3-63852 (JP, A) JP-A-6-314241 (JP, A) JP-A-53-134335 (JP, A) JP-A-4- 369061 (JP, A) JP-A-6-51982 (JP, A) JP-A-8-161226 (JP, A) JP-A-7-64862 (JP, A) JP-A-6-342403 (JP, A) JP-A-5-181748 (JP, A) JP-A-8-212054 (JP, A) JP-A-6-28180 (JP, A) JP-A-3-102443 (JP, A) JP-A-2-18645 (JP, A) Special table Hei 7-506921 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 12/08-12/12 G06F 9/38 G06F 17/16 G06T 1 / 60

Claims (4)

(57) [Claims] 1. A first buffer for holding an address history of a past memory access, and a distance between the address and a part or all of the address history held in the first buffer at the time of memory access. Means for calculating
A second buffer for holding the distance and matches the number of the first address stored in the buffer and previous one or more addresses, stored in the addresses and the first buffer upon a new memory access Past memory
When the distance from one of the access addresses coincides with at least one of the distances corresponding to past memory accesses held in the second buffer, means for storing the number of matches corresponding to the combination of the accesses A means for issuing continuous access at the distance when the number of matches reaches a predetermined number. 2. The memory access speed-up device according to claim 1, further comprising means for stopping the continuous access when data accessed continuously is not used. 3. The memory access speed-up device according to claim 1, wherein the continuously accessed data is stored in a temporary storage buffer and not directly stored in a cache memory. 4. The memory access speed-up device according to claim 1, further comprising means for ignoring the exception even if an exception occurs at the time of continuous access. apparatus.