JP3078649B2 - Cell readout phase control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell readout phase control method, and more particularly to a cell readout phase control method for writing the same cell in each buffer of a multiplexing system and reading out the cell with the same phase. B-ISDN (Broadband-Integrated
So-called ATM that asynchronously transfers cells, which are a type of fixed-length packet, as the core technology of Services Digital Network
(Asynchronous Transfer Mode) technology is being developed. In an ATM network, transmission lines are multiplexed to improve reliability in the event of a failure. However, in order for the multiplexing system to function properly, each cell row of the working system and the protection system is always used. Must match.

[0002]

BACKGROUND OF THE INVENTION Figure 7 a view for explaining a cell read phase in a conventional duplex systems, in FIG., 7 _0, 7 ₁
Is a buffer circuit unit, 3 is a selector (SEL) for switching between the active system and the standby system, and 4 is a cell read control unit. ATM
In the interface portion of the network comprises a buffer circuit 7 _0, 7 ₁ for the purpose of clock signal crossover. Buffer circuit 7 _0, 7 _1, but those capable of storing more than respectively one cell, the cell reading control unit 4 before storing the data of one cell
When the data is read from the memory cell, an empty data cell (empty cell) is generated.

[0003] In such a configuration, the cell A~E arriving to IN of the transmission path is working and protection of the buffer circuit 7 _0, 7 ₁
Are written sequentially. Meanwhile, the cell reading control unit 4 and the cell A~E buffer circuit 7 _0, 7 ₁ sequentially and is read out at the same time, captures the current system buffer circuit 7 ₀ of the read cell of them. And if when the bit error rate of the read cell in the active system is such an increase switches the connection of the selector 3 to b-c side by the control signal C, then the buffer circuit ₇₁ and the current system Such control is performed.

[0004] However, there may be different from the distance from the distance and the IN from IN such transmission line to the buffer circuit 7 ₀ to the buffer circuit _71, when the cell writing for this, among them of one buffer circuit 7 ₀ by the write delay difference it has been already completed the writing of the cell C, and occurs state as not finished writing the other buffer circuit 7 _1, yet cell C.

[0005] Moreover, when the cell reading control unit 4, such as by multiplying the read buffer circuit 7 ₀ and 7 ₁ in such timing, but the cell C is read from the buffer circuit 7 _0, buffer thus read is empty cell from the circuit unit _71. For this reason, conventionally, the read cell columns of the active system and the standby system do not coincide with each other, and there has been a problem that cells are duplicated or lost by switching the redundant system.

[0006]

As described above, in the conventional cell readout system, the readout cell columns of the active system and the standby system do not match, and cells are duplicated or lost by switching the redundant system. Inconvenience. An object of the present invention is to provide a cell read phase control method in which the read cell columns of the active system and the standby system always match.

[0007]

The above-mentioned problem is solved by the structure shown in FIG. That is, in the cell readout phase control method of the present invention, in the cell readout phase control method in which the same cell is written in each buffer of the multiplexing system and the cell is read out at the same phase, the buffer units 10 ₀ and 1 capable of storing one or more cells are provided. ₁ and
And a control section 2 _0, 2 ₁ perform cell reading control of the buffer section 1 _0, 1 _1, the control unit 2 _0, 2 ₁ buffer 1
_0, when 1 ₁ of the cell of at least one system during read buffer section 1 ₀ or 1 ₁ does not store more than one cell and outputs an empty cell.

The above-mentioned problem is solved by the structure shown in FIG. That is, in the cell readout phase control method of the present invention, in the cell readout phase control method in which the same cell is written in each buffer of the multiplexing system and the cell is read out in the same phase, one or more cells can be stored and the one or more cells can be stored. when receiving the read when not store the buffer circuit section 5 _0, 5 ₁ outputs an empty cell, the buffer circuit section 5 _0, 5 buffer 1 ₀ connected in series to the ₁ ', 1 _1' met Te, and it can store more than one cell, the buffer section 1 ₀ ', 1 _1' controller 6 ₀ perform cell reading control, 6 comprises a ₁ and the control section 6 _0, 6 ₁ at least during cell read If the buffer unit 1 ₀ ′ or 1 ₁ ′ of the system stores an empty cell, the empty cell is output.

[0009]

[Action] In FIG. 1, cell A~D arriving to IN of the transmission line is sequentially written into the buffer section 1 _0, 1 ₁ of the working and standby systems. Meanwhile, the cell reading control unit 4 to the buffer section 1 _0, 1 ₁ and read sequentially and simultaneously writing cells to the buffer unit 1 at the time the cell reading control unit 4 starts the cell read _0, 1 ₁ when the writing of the cell a had ended together, the control unit 2 _0, 2 ₁ reads the respective cell a from the buffer section 1 _0, 1 _1. In the example of FIG. 1, the same applies to the cell B.

However, the cell read control unit 4 reads the cell C
Is started, the buffer unit 1 ₀, 1₁Cell book to
Buffer section 1₀Of cell C to
Has been completed, but the buffer unit 1₁Write cell C to
Has not been completed yet. Heel
Control unit 2₀Is the data knot ready signal N
RDY₀Is not output, but the control unit 2₁Is data notre
Dee signal NRDY₁And outputs the output signal NRDY₁
Pull-up resistor by energizing the inverter circuit
Data knot ready for common line biased with R
The signal NRDY is set to the LOW level. That is, the control unit 2₁
Is the buffer 1₁Not remembering more than one cell
Report to control unit 2₀Inform

[0011] As a result, since the control unit 2 ₁ is originally not be read cell C from the buffer section 1 _1, and outputs an empty cell from the buffer section 1 ₁ instead. On the other hand, the control section 2 ₀ although the read out cell C from the buffer section 1 ₀ would otherwise, data of the common line Not Ready signal N
When RDY is true (LOW level), an empty cell is output instead. Thus, both empty cell from the buffer section 1 _0, 1 ₁ in the cell reading phase is output.

At the time of reading the next cell, the buffer unit 1
_0, 1 writing of the cell C to ₁ are terminated together. Accordingly, the control section 2 _0, 2 ₁ can read both the cell C from the buffer section 1 _0, 1 _1, thus, so that each read cell column of the working and standby systems will coincide at all times. Preferably, the control units 2 ₀ and 2 ₁ include their own buffer units 1 ₀ and 1 _1.
Outputs a predetermined cell pattern signal instead autologous read data buffer 1 _0, 1 ₁ fixes the read counter the de-energized or constant level or read data.

Preferably, the control unit 2₀, 2₁Is indigenous
Buffer part 1₀, 1₁The read counter of 1 cell back
And read out and own buffer unit 1₀, 1₁Readout data
Data is deactivated or set to a fixed level or replaced with read data.
And outputs a predetermined cell pattern signal. Also in Figure 2
Thus, cells A to C arriving at IN on the transmission line are
Standby buffer circuit section 5₀, 5₁Are sequentially written to
You. On the other hand, the cell read control unit 4₀´, 1₁
'Are sequentially and simultaneously read out from the write cells.
Buffer circuit section 5 in conjunction with reading₀, 5₁Of the write cell
Read out, buffer unit 1 ₀´, 1₁Written on ´
You.

In this state, the buffer circuit unit 5₀, 5₁
Can store one or more cells each, and if
When the above is not stored, the control unit 6₀, 6₁Cell reading from
When receiving the output control, an empty cell is output. this
In the example of FIG. 2, the buffer circuit unit 5₀, 5₁Write
At the time when the reading of the buffer B is performed, the buffer circuit unit 5₀Is
Read buffer B, but the buffer circuit unit 5₁Is empty
Has occurred. As a result, the cell read control unit 4
Fa part 1₀´, 1₁Read these cells from ´
Buffering, buffer unit 1₀'From cell B
Buffer part 1 ₁Empty cells are read from '
Will be.

[0015] If such a control unit 6 ₀ buffer 1 ₀ ', but does not output the empty cell storage signal BS _0, the control unit ₆₁ includes a buffer part 1 _1' empty cell storage signal BS ₁ of
To output, output signals BS ₁ is by energizing the inverter circuit, the empty cell storage signal BS of the common line which is biased by pull-up resistor R to LOW level. That is, the control unit ₆₁ informs the information to the effect that the buffer unit 1 ₁ 'are storing empty cell to the controller 6 _0.

As a result, in this reading phase, the control unit 6
₁Is the buffer 1₁The empty cell stored in ´
Read as is. On the other hand, the control unit 6₀Is a buffer
Part 1 ₀'Can read cell B from the common line.
Empty cell storage signal BS is true (LOW level)
Output an empty cell instead. That is, this read
Buffer unit 1 in phase₀´, 1₁Empty cells together from ´
Is output.

At the time of reading the next cell, the buffer unit 1
_{Both 0} 'and 1 ₁ ' store cell B. Accordingly, the control unit 6 _0, 6 ₁ buffer 1 ₀ ', 1 _1' can be read both cell B than, thus, so that each read cell column of the working and standby systems will coincide at all times.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments according to the present invention will be described below in detail with reference to the accompanying drawings. Note that the same reference numerals indicate the same or corresponding parts throughout the drawings. Figure 3 is a diagram showing a configuration of the cell read phase control method of the first embodiment, 1 _0, 1 ₁ the buffer unit in Fig, Elastica tics memory 11 consisting of DPRAM, etc. (EM), 12 a write counter (W
C) and 13 are read counters (RC), 14 is a comparator (CMP), 15 is an addition circuit, 16 is a subtraction circuit, 17
Is a comparator (CMP), 18 is an AND gate circuit,
2 _0, 2 ₁ control unit, 21 _0, 21 ₁ D-type flip-flop (FF), 22 _0, 22 _1, for example open-collector type inverter circuit, 23 _0, 23 ₁ and 24 _0, 24 ₁ An AND gate circuit 3 is a selector (SEL) for switching the duplex system, and 4 is a cell read control unit.

[0019] Focusing on the buffer section 1 _0, write counter 12 is output to the write address WA of eM11,
When write pulse WP external than the cell enters, it writes write data WD ₀ at that time to eM11, write counter 12 is incremented. On the other hand, the read counter 13
Output the read address RA of EM11. The subtraction circuit 16 performs the operation of D = WA-RA to obtain EM11.
, And the comparator 17 compares the calculated number D of accumulated data with the number SL of data for one cell. If D ≧ SL, a signal of logic 1 level is output because data of one cell or more is stored in EM11.

The write counter 12 returns to "0" when counting the buffer size BL of the EM 11.
Comparator 14 has detected this condition, and if WA
<When the state of RA is detected, the AND gate circuit 18 is activated. As a result, the addition circuit 15 performs the operation of WA + BL, and as a result, the subtraction circuit 16 calculates D = (WA + BL) -R
The calculation of A is performed to determine the number D of accumulated data.
The same applies to the buffer unit 1 _1.

On the other hand, when the cell read control unit 4 outputs the cell read start pulse signal PRP, if the buffer unit 1
_0, if 1 ₁ is in the state of D ≧ SL Both flip-flops 21 _0, 21 ₁ are both set, the control unit 2
_0, 2 ₁ are both data Not Ready signal NRDY _0,
Does not output NRDY ₁ . Therefore, the pull-up resistor R data Not Ready signal NRDY common lines being biased by the false (HIGH level), thereby the control unit 2 _0, 2 ₁ of AND gate circuit 23 _0, 24 ₀
And an AND gate circuit 23 _1, 24 ₁ is energized.

[0022] As a result, the control section 2 _0, read counter 13 of the buffer unit 1 ₀ is incremented by the read pulse signal RP, and input to the selector 3 via the read cell AND gate circuit 23 ₀ from the EM11 I do. Again the control unit 2 _1, read counter 13 of the buffer section 1 ₁ is incremented by the read pulse signal RP, and is input to the selector 3 via the read cell AND gate circuit 23 ₁ from the eM11. That is, in this case, the same cell is read out at the same phase.

Further, when the cell reading control unit 4 at the time of outputting the read start pulse signal PRP, for example, the buffer portion 1 ₁ of the standby system is in a state not the D ≧ SL, the control section 2 ₀ of flip-flop 21 ₀ is set and does not output the data knot ready signal NRDY ₀ ,
_{The 1} flip-flop 21 ₁ is reset and outputs the data knot ready signal NRDY ₁ . The data Not Ready signal NRDY true (LOW level) of the common line by the output signal NRDY _1, thereby AND gate circuit 23 _0, 24 ₀ and an AND gate circuit 23 _1, 24 ₁ is de-energized.

[0024] As a result, the control section 2 _0, read counter 13 of the buffer section 1 ₀ without incrementing, and generates an empty cell as a result since the reading level is also de-energized for the eM11. Again the control unit 2 _1, buffer 1
_Since the read counter 13 of ₁ does not increment and the read level of the EM 11 is also deactivated, an empty cell is generated as a result. That is, in this case, empty cells are generated in the same phase, and thus, all the read cell columns of the active system and the standby system match.

In the first embodiment, as a result of using the AND gate circuits 23 ₀ and 23 ₁ , the empty cell pattern signal has a fixed pattern of all bits “0”. Therefore, these AND gate circuits 23 ₀ and 23 ₁ are replaced with, for example, OR gate circuits, and the data knot ready signal NR of the common line is connected to one input terminal of each OR gate circuit.
If an inversion signal of DY is added, the empty cell pattern signal can be a fixed pattern of all bits “1”.

FIG. 4 is an operation timing chart of the cell readout phase control method of the first embodiment. In the figure, the cell write data WD ₀ of the working system (system 0) are written without delay buffer 1 ₀ for all cells A-E. on the other hand,
The cell write data WD ₁ of the standby system (system 1) has a slight delay when the cell C arrives, so that the buffer unit 1 ₁ is still at the time when the read start pulse signal PRP for the cell C is generated. The writing of the cell C into the cell has not been completed. As a result, in the read phase are both empty cell is generated from the buffer unit 1 _0, 1 _1. Further, at the time when the next read start pulse signal PRP is generated, the cell C to the buffer portion 1 ₁
Has been completed. As a result, in the reading phase both cell C is read from the buffer section 1 _0, 1 _1.

FIG. 5 is a diagram showing a configuration of the cell read phase control method of the second embodiment, 1 _0, 1 ₁ the buffer portion of the second embodiment in FIG, 19 is a subtraction circuit, 2 _0, 2 ₁ The control unit of the second embodiment, 25 ₀ , 25 ₁ is a pattern generator (P
G), 26 ₀ , 26 ₁ are selectors (SEL), 27 ₀ ,
27 ₁ is an inverter circuit, and 28 ₀ and 28 ₁ are AND gate circuits.

[0028] With attention to the control section 2 _0, when the data Not Ready signal NRDY fake common line (HIGH level), the output of the inverter circuit 27 ₀ becomes LOW level, the AND gate circuit 28 ₀ is deenergized And
And the selector 26 ₀ selects the input terminal a side. When the read pulse signal RP is input in this state, EM
11 data of one cell is read out from, this is read out to the outside via the selector 26 _0.

On the other hand, when the data Not Ready signal NRDY the common line is true (LOW level), the output of the inverter circuit 27 ₀ becomes HIGH level, thereby A
ND gate circuit 28 ₀ is energized and selector 26 ₀
Selects the input terminal b side. When the read start pulse signal PRP is input in this state, the AND gate circuit 2
8 ₀ outputs a load signal L, thereby reading the counter 13 loads the read address of one cell before the present time by a predetermined clock signal. When subsequently inputted read pulse signal RP, but dummy data from read address of one cell before the EM11 is read, which is blocked by the selector 26 _0. On the other hand, the pattern generator 25 ₀ is generated a predetermined cell pattern signal (e.g., an empty cell pattern signal) in accordance with a read pulse signal RP, which is read out to the outside via the selector 26 _0. The same applies to the control section 2 _1. Therefore, according to the second embodiment, there is an advantage that the pattern signal of the empty cell can be set freely.

FIG. 6 is a diagram showing a configuration of the cell read phase control method of the third embodiment, 5 _0, 5 ₁ buffer circuit in FIG, 1 _0, 1 ₁ buffer that can store one or more cells , 51 ₀ , 51 ₁ are D-type flip-flops (F
F), 52 _0, 52 ₁ and 53 _0, 53 ₁ AND gate circuit, 6 _0, 6 ₁ controller, 1 ₀ ', 1 _1' buffer unit for storing one cell, 61 _0, 61 ₁ D-type flip-flop (FF) is 62 _0, 62 ₁ OR gate circuit, 63 _0, 63 ₁ to 65 _0, 65 ₁ AND gate circuit, 66 _0, 66 _1, for example in an inverter circuit of an open collector type is there.

Cells arriving at IN on the transmission path are buffered.
Part 1₀, 1₁Are written sequentially. On the other hand, cell read control
Unit 4 is buffer unit 1₀´, 1₁Write cells to ´ sequentially
When reading is performed normally at the same time,
AND gate circuit 63₀, 63₁Output read pulse R
P₀, RP₁Is the buffer circuit 5₀, 5₁Supplied to
At that time, the AND gate circuit 53₀, 53₁Is energized
Buffer section 1 ₀, 1₁Write cell to read
These are the buffer 1₀´, 1₁Written on ´
You.

[0032] With attention to the buffer circuit section 5 _0, when receiving a read starting pulse PRP ₀ when the buffer unit 1 ₀ is stored more than one cell, the flip-flop 51 ₀
Are set, and as a result, AND gate circuits 52 ₀ , 53
₀ is energized, reading one cell in the buffer portion 1 ₀ continue the read pulse RP ₀ is sent. On the other hand, when receiving the read start pulse PRP ₀ when the buffer section 1 ₀ does not store more than one cell, the flip-flop 51
₀ is reset, which causes AND gate circuits 52 ₀ ,
53 ₀ is de-energized, so that the buffer circuit section 5 ₀ generates an empty cell. The same applies to the buffer circuit section 5 _1.

On the other hand, the control unit 6₀Note that the buffer
Circuit part 5₀Flip-flop 51 ₀And control unit 6₀No
Lip flop 61₀Are connected like a shift register
Control unit 6₀Is the buffer unit 1₀´ writing data
When reading data from the buffer circuit,
Part 5₀Has read normal 1-cell data, or
Information as to whether or not an empty cell has been generated is stored in the flip-flop 61.₀
Will be transferred to

Therefore, the flip-flop 61₀Set
The buffer unit 1 ₀´ arrives on the transmission line
When one cell is stored, if the data
The ready signal NRDY is false (high level).
Then, the AND gate circuit 65 ₀Is activated and the pull
The buffer unit 1 is operated by the read pulse signal RP sent subsequently.
₀', Cell data for one cell is read. one
On the other hand, the data knot ready signal NRDY of the common line is true.
(LOW level), the AND gate circuit 65₀
Is deactivated, and as a result, the control unit 6₀Leaves empty cells
Live.

The flip-flop 61₀Reset
The buffer unit 1 ₀´ indicates an empty cell
When remembering, the OR gate circuit 62₀Is unconditionally attached
Control unit 6₀Is the buffer 1₀´
From the empty cell. Control unit 6₁The same applies to
is there. Therefore, the control unit 6₀, 6₁In the output of
It is possible to always match the read cell rows of the
Wear.

According to the third embodiment, even when using a buffer circuit 7 _0, 7 ₁ as is conventionally employed as the buffer circuit section 5 _0, 5 ₁ duplexing systems, third embodiment in this Example Buffer units 1 ₀ ′ and 1 ₁ ′ and control unit 6
_0, by adding a buffer circuit portion composed of 6 _1, it is possible to easily match the entire cell row of the active system and a standby system at all times.

[0037] The buffer unit 1 ₀ In this third embodiment
Although the storage capacity of ', 1 ₁ ' is set to one cell, it is not limited to this. Buffer 1 ₀ ', 1 _1' storage capacity is capable to two cells or more, in this case if connected ₀ 2 or more flip-flops 61, ₆₁ respectively shift register to , The storage information of each flip-flop group and each storage information of the buffer units 1 ₀ ′ and 1 ₁ ′ can be associated with each other.

Further, the control unit 6 in the third embodiment _0, 6 ₁ has a configuration using the AND gate circuit 64 _0, 64 _1, as the selector 26 of the second embodiment _0, using 26 ₁ configuration instead Is also good. In the above embodiment, an example of application to a duplex system has been described. However, it is apparent that the present invention can be applied to, for example, a triple system or a higher system that operates under the control of majority logic.

In the above embodiment, empty cells are output under certain conditions. However, any kind of generated cells other than normal cells sent from the transmission line is included in the concept of empty cells in the present invention. Things.

[0040]

As described above, according to the present invention, one cell
Buffer unit 1 capable of storing the above₀, 1 ₁And the buffer section
1₀, 1₁Control unit 2 that controls cell reading₀, 2₁And
Equipped, control unit 2₀, 2₁Is the buffer 1₀, 1₁Cell
At the time of reading, buffer unit 1 of at least one system₀Or 1
₁If no cell is stored, an empty cell is output.
The phase of the read cells in the entire system must always match.
Can be.

[0041] According to the present invention, the buffer circuit section 5 ₀ for outputting idle cells when receiving a read when not stored above said one cell with can store more than one cell, 5
_1, buffer 1 ₀ connected in series to the buffer circuit section 5 _0, 5 ₁ ', 1 _1' a, and those that can store more than one cell, the buffer section 1 ₀ ', 1 _1' cell reading controller 6 ₀ for controlling, 6 ₁ a, the control unit 6 _0, 6 ₁ if the buffer portion of the at least one system during the cell read 1 ₀ 'or the 1 _1' stores a vacant cell since outputs an empty cell, it is possible to match the phase of easily entire system read cell even when using a buffer circuit 7 _0, 7 ₁ as is conventionally employed as the buffer circuit section 5 _0, 5 ₁ always .

[Brief description of the drawings]

FIG. 1 is a diagram showing the basic configuration of the present invention.

FIG. 2 is a diagram showing the basic configuration of the present invention.

FIG. 3 is a diagram showing a configuration of a cell readout phase control method according to the first embodiment.

FIG. 4 is an operation timing chart of the cell readout phase control method of the first embodiment.

FIG. 5 is a diagram showing a configuration of a cell readout phase control system according to a second embodiment.

FIG. 6 is a diagram showing a configuration of a cell readout phase control method according to a third embodiment.

FIG. 7 is a diagram illustrating a cell readout phase in a conventional duplex system.

[Explanation of symbols]

1 _0, 1 ₁ buffer section 2 _0, 2 ₁ control unit 3 selector 4 cell read controller 5 _0, 5 ₁ buffer circuit 1 ₀ ', 1 _1' buffer 6 _0, 6 ₁ controller

Continued on the front page (72) Inventor Haruo Yamashita 1015 Uedanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Yuji Takizawa 1015 Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited (72) Invention Person Kazuyuki Tajima 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Satomi Ikeda 1015 Kamikodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Hiroshi Ota Inventor Hiroshi Ota Uchisaiwai-cho, Chiyoda-ku, Tokyo 1-6, Nippon Telegraph and Telephone Corporation (72) Inventor Hiromi Ueda 1-1-6, Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (56) References JP-A-5-227196 (JP, A) JP-A-5-227191 (JP, A) JP-A-4-222138 (JP, A) JP-A-4-346538 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) ) H04L 12/28 H04L 12/56 H04L 1/22

Claims (4)

(57) [Claims] 1. A cell reading phase control system for writing the same cell to each buffer of a multiplexing system and reading the cell at the same phase, a buffer unit (1 ₀ , 1 ₁ ) capable of storing one or more cells, and a buffer unit And a control unit (2 ₀ , 2 ₁ ) for performing cell reading control of (1 ₀ , 1 ₁ ). The control unit (2 ₀ , 2 ₁ ) includes at least a buffer unit (1 ₀ , 1 ₁ ) for reading cells. A cell readout phase control method characterized by outputting an empty cell when the buffer unit (1 ₀ or 1 ₁ ) of one system does not store one or more cells. Wherein the control unit read data (2 _0, 2 ₁₎ autologous buffer section (1 _0, 1 ₁₎ autologous buffer section fixes the read counter (1 _0, 1 ₁₎ 2. The cell readout phase control method according to claim 1, wherein a predetermined cell pattern signal is output to be deactivated or set to a constant level or in place of readout data. Wherein the control unit (2 _0, 2 ₁₎ the buffer portion of the self-system (1 _0, 1 ₁₎ autologous buffer section reads back one cell read counter (1 _0, 1 ₁₎ 2. The cell readout phase control method according to claim 1, wherein said readout data is deactivated or set to a fixed level or a predetermined cell pattern signal is output in place of said readout data. 4. The same cell is written in each buffer of the multiplexing system.
Cell read phase control method for reading out the cells with the same phase
In the formula, one or more cells can be stored and the one or more cells can be stored
If a read is received when there is no
Fa circuit (5₀, 5₁) And the buffer circuit (5₀, 5₁B) connected in series to
Key (1₀´, 1₁´), where one or more cells are stored
And the buffer section (1₀´, 1₁´) Cell reading control
Gobe (6₀, 6₁) And the control unit (6₀, 6₁) Indicates that at least 1
System buffer (1 ₀´ or 1₁´) indicates an empty cell
The feature is to output empty cells when remembering
Cell read phase control method.