JP3076293B2 - Semiconductor device characteristic test apparatus and test method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device characteristic test apparatus and a test method thereof, and more particularly to a semiconductor device characteristic test apparatus capable of switching a plurality of measurement systems and a test method thereof.

[0002]

2. Description of the Related Art A conventional semiconductor device characteristic test apparatus is disclosed in Japanese Utility Model Laid-Open No. 62-116546 (first known example).
There are the following. As shown in FIG. 5, this characteristic test apparatus is a block diagram schematically showing a connection relationship between a semiconductor device measuring section A and an IC tester 9. In the figure, reference numeral 10 denotes a performance board for connecting the IC tester 9 and each device of the measuring section A, and 11 denotes a parallel board provided in the measuring section A.
This is a measurement board for measuring simultaneously and alternately. Since this characteristic test apparatus performs measurements alternately, the operation of the left portion B of the measurement section A will be described.

When a characteristic test of a semiconductor device is performed, the semiconductor device is supplied to the first and second measurement systems 13a and 13b at the same time, and the semiconductor device installed in the first measurement system 13a is measured. The semiconductor device of the second measurement system 13b is not connected, and the characteristic test is not performed.
When the measurement of the semiconductor device of the first measurement system 13a is completed, the contact is released, the semiconductor device of the second measurement system 13b is contacted, and the measurement of the second measurement system 13b is started. In addition, the first measurement system 1 where this measurement is completed
The semiconductor device 3a is taken out of the socket 12, and the next semiconductor device is set in the first measurement system 13a. However, no contact is made until the measurement of the semiconductor device of the second measurement system 13b is completed.

As described above, by alternately or sequentially measuring the plurality of measurement systems 13a and 13b, the time required for the semiconductor device to be handled from the supply unit to the measurement unit to the storage unit, that is, in a single measurement system, This is a measurement method in which the time during which the IC tester does not perform the measurement can reduce the time during which operation loss occurs.

As another known example, there is a method disclosed in Japanese Utility Model Laid-Open No. 62-67270 as another known example of the method of switching the measurement depending on whether or not the semiconductor device is in contact with the semiconductor device shown in FIG. In this case, as shown in the block diagram of FIG. 6, a method of switching the measurement system using the multi-relay 14 is used. That is, the measurement heads 15 and 16 of the two measurement systems are switched by the multi-relay 14 and connected to the AC tester 17 or the DC tester 18.

[0006]

In the above-mentioned prior art, in the second known example, since the measuring heads 15 and 16 are switched by the multi-relay 14, there is a problem that the test apparatus becomes large. . There is an IC having several hundreds of external terminals with the increase in the degree of integration of a semiconductor device.
When using the test equipment, the test equipment becomes large due to the increase in the number of parts.

In the first known example, the measuring system 13a,
The problem is that the switching of 13b is performed by alternately contacting the semiconductor devices, and the measurement system is in an electrically connected state as shown in part D of FIG. 5 and is not independent. Therefore, when the measurement frequency is as high as several hundred MHz, the capacitance (capacitor component) between the signal line and the ground increases due to the influence of the wiring of the measurement system on the side where the measurement is not performed. In some cases, the measurement may not be performed properly due to, for example, the adhesion of conductive foreign matter between the measurement terminals of the IC socket on the side that is not touched.

[0008] The object of the present invention is to solve these problems,
It is an object of the present invention to provide a miniaturized semiconductor device characteristic test device which can be sequentially measured by a plurality of electrically independent measurement systems when performing a characteristic test of a semiconductor device.

[0009]

SUMMARY OF THE INVENTION A semiconductor device characteristic testing apparatus according to the present invention comprises a plurality of sockets for mounting semiconductor devices each having a large number of external connection terminals, and is connected to each of the plurality of sockets. Contact pads are shorter than the spacing between the sockets of each of the semiconductor devices.
A plurality of contact pins corresponding to the number of external terminals corresponding to one semiconductor device are arranged facing the wiring board portion mounted at every interval and facing the contact pad surface of the wiring board portion; A contact unit connected to a test apparatus via a DUT board, and a drive unit for sequentially moving each contact pin on the contact unit on the contact pad and switching each contact pad between the plurality of semiconductor devices. have a, before before
Note that each contact pad is one for each contact pin.
It is characterized by being concentratedly arranged at each location .

[0010] Further, each contact pad can be mounted on one surface of the wiring board portion, a plurality of sockets can be mounted on the other surface of the wiring board portion, and the contact pads and the contact pins are interchanged. The contact unit may be provided with the contact pads, and the wiring board portion may be provided with the contact pins. Further, two sets of contact pads or contact pins for a semiconductor device are shorter than a space between the two sets of semiconductor devices. And three sets of contact pads or contact pins for a semiconductor device can be arranged in a triangular shape at predetermined intervals.

Further, the method for testing semiconductor device characteristics according to the present invention comprises:
Each contact pad connected to a plurality of sockets connecting a plurality of semiconductor devices is connected to a socket of each semiconductor device.
A plurality of semiconductor devices having a large number of external connection terminals are mounted on each socket of the wiring board portion mounted at intervals shorter than the arrangement interval , and the semiconductor device faces the contact pad surface of the wiring board portion. A contact unit in which a plurality of contact pins corresponding to the number of one external terminal are provided, and these contact pins are connected to a test apparatus via a DUT board so as to face one set of the contact pins, and Socket spacing of each semiconductor device
The semiconductor devices are moved and connected at shorter intervals, and a test is performed on each of the semiconductor devices one by one.

According to the configuration of the semiconductor device characteristic testing apparatus of the present invention, the size of the switching part of the measuring system is determined by the diameter of the contact pad and the contact pin and the distance between the contact pad and the contact pin adjacent thereto. Since it is roughly determined, the size of the component / device can be reduced by reducing the diameter of the contact pad and the contact pin and reducing the distance between the adjacent contact pad and the contact pin.

[0013]

Embodiments of the present invention will now be described with reference to the drawings. 1A, 1B, and 1C are a block diagram showing a configuration of an embodiment of the present invention, a front view of a wiring board unit 1 thereof, and a perspective view of a contact pin unit thereof. The characteristic test apparatus of the present embodiment includes a contact pad 7
And a contact pin unit 2 provided with contact pins 8, a DUT board 4 connected to an IC tester, and a drive unit 3 for moving the contact pin unit 2 up, down, left and right.

In the socket / wiring board portion 1 provided with the contact pads 7, the test terminals of the plurality of IC sockets 5, 6 and the contact pads 7 on the back surface are electrically connected on the front surface. The contact pin unit 2 having the contact pins 8 includes a contact pin 8 and a DUT (D
The test terminals of the device under test board 4 are electrically connected.

As shown in FIG. 1B, in the socket / wiring board portion 1, the contact pads 7 on the back surface have IC sockets 5 and 6, ie, the number of contact pads 7 corresponding to the number of measurement systems. The contact pads 7 are arranged according to a specific rule, and the groups of the contact pads 7 are arranged by the number of external terminals of the semiconductor device. Here, when measuring the semiconductor device having n external terminals sequentially with m measurement systems, m × n contact pads 7 are arranged. For example, C1A, C1B, C2A, C2B... , CnB are contact pad numbers.

The contact pin unit 2 corresponds to FIG.
As shown in (c), when measuring a semiconductor device having n external terminals, n contact pins 8 are arranged on the surface of the contact pin unit 2, and P 1, P 1,
P2, Pn-1 and Pn are contact pin numbers. Note that the interval between P1 and P2 of the contact pin 8 is the same as the interval between C1A, C1B and 7 of the contact pad 7.

Next, the operation of this embodiment will be described with reference to the connection diagram of FIG. Driving unit 3 of this characteristic test device
As a result, the contact pin unit 2 operates to move up, down, left and right, and the contact pins 8 are connected to or disconnected from the contact pads 7 on the back surface of the socket / wiring board unit (hereinafter, referred to as the board unit) 1. FIG. 2 (a)
(B) is a schematic diagram and a circuit diagram showing the connection between the contact pad unit 2 and the surface of the contact pad 7 of the substrate unit 1 when the measurement system A is connected to the IC tester, and the contact pin P1 is used as the contact pad C1A. The contact state of the contact pin P2 to the contact pad C2A is shown in FIG.

Similarly, FIGS. 2C and 2D show that the measurement system B
FIG. 4 is a schematic diagram showing the connection between the contact pad unit 2 and the surface of the contact pad 7 of the substrate unit 1 when connected to the C tester, and a circuit diagram thereof, wherein the contact pin P1 is a contact pad C1B, Connected to C2B. Although FIG. 2 shows only two sets of contact pads 7 and contact pins 8,
When measuring a semiconductor device having n external terminals, n sets of contact pads 7 and contact pins 8 are connected at the same time. Also in this case, the driving unit 3
As a result, the contact pin unit 2 is
As shown in (b), these can be moved alternately to realize the alternate measurement of the measurement systems A and B.

The contact pin unit 2 can be downsized by reducing the distance between the adjacent contact pins 8 and the diameter of the contact pins 8, and each measuring system is electrically independent. Therefore, it is not affected by other measurement systems.

FIG. 3A is a block diagram showing the configuration of the second embodiment of the present invention, in which the contact pads 7 and the contact pins 8 of the first embodiment are replaced with each other. 1 is provided with a contact pin 8 on the back surface and a contact pad 7 on the front surface of the contact unit 2. In this case, the driving unit 3
However, this is performed by moving the lower part of the socket / wiring board part 1 instead of the contact unit 2, and the contact pads 7 and the contact pins 8 are turned upside down. The operation in this case is the same as in the first embodiment.

FIG. 3B is a connection diagram showing a configuration of the board unit 1 according to the third embodiment of the present invention. The socket / wiring board unit 1 according to the first embodiment includes two sets of measurement systems A. , B are replaced with three sets of measurement systems A, B, C. The contact pads C1A, C1B, C1C and the contact pads C2A, C2B, C2C of the three sets of measurement systems are respectively arranged in a triangular shape. The contact pins (8) P1 and P2 move between the contact pads 7 to switch the measurement system. The switching of the measurement system may be performed sequentially, for example, in the direction of the arrow.

[0022]

Next, an example of this embodiment will be described with reference to FIG.
The connection between the contact pad 7 and the contact pin 8 shown in FIGS. FIG.
(A) is a plan view of a contact pad surface of a substrate unit 1 of a test apparatus for measuring a semiconductor device having 100 external terminals, and 200 circular contact pads 7 are 3 m long.
FIG. 4B is a perspective view of the contact unit 2 in which 100 contact pins 8 are arranged at an interval of 6 mm. This test apparatus operates in the same manner as described with reference to FIGS. That is,
When there are two measurement systems A and B, these connection states are alternately repeated, and the measurement state is alternately switched by moving the contact unit 2 left and right by 3 mm, so that alternate measurement is possible. In this case, the height is 27 mm and the width is 54 m
100 contact pins 8 will fit in the area within m, which is a size that can be put to practical use.

[0023]

As described above, according to the structure of the present invention, the connection of the measuring system is switched by the movement of the contact pins and contact pads connected to each other, and the diameter and the interval of these contact pins and contact pads are changed. By reducing the size, the switching mechanism of the measurement system can be miniaturized, so that there is an excellent effect that the characteristic test apparatus for alternately measuring semiconductor devices having several hundred external terminals can be miniaturized. In addition, since the measurement system that is not in the measurement state is electrically disconnected, even in a characteristic test device having a plurality of measurement systems, the electrical influence of the measurement system other than the measurement system in the measurement state is removed. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a main block diagram showing an embodiment of the present invention, and a front view and a perspective view of a substrate portion thereof.

FIG. 2 is a connection diagram and a circuit diagram for explaining a relationship between a substrate unit 1 and a contact pin unit 2 in FIG.

FIG. 3 is a main block diagram showing a second embodiment of the present invention, and a connection diagram thereof.

FIGS. 4A and 4B are a front view and a perspective view illustrating a specific structure of a substrate unit 1 and a contact pin unit 2 of FIG.

FIG. 5 is a block diagram showing a configuration of a first conventional example.

FIG. 6 is a block diagram showing a configuration of a second conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate part 2 Contact pin unit 3 Driving part 4 DUT board 5, 6 IC socket 7 Contact pad 8 Contact pin 9 IC tester 10 Performance board 11 Measurement board 12 Socket 13a, b Measurement system 14 Multi-relay 15, 16 Measurement head 17 AC tester 18 DC tester

Claims (6)

(57) [Claims] A plurality of sockets for mounting semiconductor devices having a large number of external connection terminals are mounted, and contact pads respectively connected to the plurality of sockets are shorter than an arrangement interval of the sockets of each semiconductor device.
A wiring board portion mounted at every interval, and a plurality of contact pins corresponding to the number of external terminals for one semiconductor device are provided facing the contact pad surface of the wiring board portion, and these contact pins are provided. A contact unit connected to a test apparatus via a DUT board, and a drive unit for sequentially moving each contact pin on the contact unit on the contact pad and switching each contact pad between the plurality of semiconductor devices. Yes, and the call
One contact pad for each contact pin
A semiconductor device characteristic test apparatus characterized by being centrally arranged . 2. The semiconductor device characteristic test apparatus according to claim 1, wherein each contact pad is mounted on one surface of said wiring board portion, and a plurality of sockets are mounted on another surface of said wiring board portion. Wherein the said the contact pad interchanged with contact pins the contact pads provided on the contact unit, the semiconductor device characteristic test apparatus of claim 1, wherein providing the contact pins to the wiring substrate section. 4. A contact pad or contact pin for two sets of semiconductor devices is arranged at a distance between the two sets of semiconductor devices.
Claims 1 and 2 arranged in parallel at predetermined shorter intervals .
4. The semiconductor device characteristic test apparatus according to 2 or 3. 5. The semiconductor device characteristic testing apparatus according to claim 1 , wherein three sets of contact pads or contact pins for the semiconductor device are arranged in a triangular shape at predetermined intervals. 6. Each of the plurality of contact pads connected to a plurality of sockets for connecting the semiconductor device before Symbol respective semiconductor instrumentation
A plurality of semiconductor devices having a large number of external connection terminals are mounted on each socket of the wiring board portion mounted at intervals shorter than the arrangement interval of the sockets, and opposed to the contact pad surface of the wiring board portion. A contact unit in which a plurality of contact pins corresponding to the number of external terminals for one semiconductor device are arranged and these contact pins are connected to a test apparatus via a DUT board is opposed to one set of the contact pins. And the socket of each semiconductor device
A semiconductor device characteristic testing method, wherein the semiconductor devices are moved and connected at intervals shorter than the interval between the units, and the semiconductor devices are tested one by one.