JP3072761B2 - Memory access control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Table of Contents] Overview Industrial application field Conventional technology (Fig. 7) Problems to be solved by the invention Means for solving the problem (Fig. 1) Action Embodiment (a) One Description of Embodiment (FIGS. 2, 3, and 4) (b) Description of Another Embodiment (FIGS. 5 and 6) (c) Description of Another Embodiment Effect of the Invention [Overview] A memory access control device in which a data processing device accesses a memory device having a plurality of banks by independently designating a bank, and aims at shortening a memory cycle time. And a data processing device that accesses the memory device, wherein the data processing device specifies the plurality of banks and synchronizes the memory device with a synchronization clock. access In the memory access control device, the data processing device is connected to the processor and directly decodes bank designation information from the processor before outputting address information from the data processing device. A decoder for generating a start signal, and an interface line for transmitting the start signal of the decoder to the memory device;
The activation signal is output simultaneously with the address in synchronization with the synchronization clock, and the activation of the desired bank of the memory device is controlled by the activation signal via the interface line.

[Industrial applications]

The present invention relates to a memory access control device in which a data processing device accesses a memory device having a plurality of banks by independently designating a bank.

In many data processing systems, in order to avoid contention for access to the memory device, the memory device is divided into a plurality of banks, and measures are taken to improve the throughput by operating each bank independently. .

Therefore, a memory access control device that operates each bank efficiently and reliably is desired.

[Conventional technology]

 FIG. 7 is an explanatory diagram of the prior art.

The memory device 1 includes a data processing device 2 that accesses the memory device 1, an address bus, and a data bus (not shown).
And various control signal lines (all not shown).

The memory device 1 is divided into four banks 1a to 1d, and each bank operates independently.

The data processing device 2 includes a CPU 20 and an address register 2
1 and a memory start instruction FF (flip-flop) 22 are provided. The memory device 1 is provided with a decode circuit 14 for decoding bank designation information and generating a start signal. Each of the banks 1a to 1d is provided with a decode circuit 14. An AND circuit 10 as an activation control unit, an activation state holding FF11 that generates an activation state signal,
An AND circuit 12 and an address latch circuit 13 for latching a memory address are provided.

 In this example, each bank is activated as follows.

Of the 30-bit addresses CAB0 to CAB29, CAB2
8 bits and 29 bits are used as bank designation information, and the remaining 2 bits
8 bits are used as an address in the bank.

When the data processing device 2 accesses the memory device 1, the memory start instruction FF22 is set and the memory start signal ST
Simultaneously with turning on the ART, the address information is sent from the address register 21 to the address bus including the 2-bit bank information.

In the memory device 1, the 2-bit bank information is decoded by the decode circuit 14, and the activation signals of the corresponding banks 1a to 1d are decoded.
Open the START AND circuit 10.

The output of the AND circuit 10 is set to the activation state FF11,
A start signal is supplied to a memory control unit (not shown), and an AND circuit
12 outputs a latch enable signal to an address latch circuit 13 to latch a memory address and supply it to a memory element.

[Problems to be solved by the invention]

In the prior art, the address transmission delay τ1 and the decode delay τ
2. It takes a total time of Anddelay τ3.

That is, it is necessary to expect a time of (τ1 + τ2 + τ3) until the bank activation state holding FF11 is set.

Therefore, in a synchronous system in which the data processing device 2 and the memory device 1 operate synchronously with the same clock, one cycle time is determined by this value.
There has been a problem that one cycle time is long.

By the time the bank start instruction information is transmitted from the data processing device 2 to the memory device 1, there is a possibility that the address lines, the decode circuit, and the AND circuit may fail. If the bank is not activated,
Wrong bank is activated, wrong data is transferred,
There was another problem that the reliability was significantly reduced.

Accordingly, it is an object of the present invention to provide a memory access control device capable of shortening a memory cycle time.

Another object of the present invention is to provide a memory access control device capable of shortening the time of a memory cycle and monitoring the normality of a startup state.

[Means for solving the problem]

 FIG. 1 is a diagram illustrating the principle of the present invention.

As shown in FIG. 1, the present invention comprises a plurality of banks 1a to 1d.
And a data processing device 2 for accessing the memory device 1. The data processing device 2 accesses the memory device 1 by specifying one of the banks 1a to 1d. In the memory access control system, a decoder 23 for decoding bank designation information and generating a start signal for each bank is provided in the data processing device 2, and the desired bank 1a to 1d of the memory device 1 is started by the start signal. To control.

The present invention further includes a bank status monitoring unit 3 for monitoring the normality of the correspondence between the bank start signal and the bank designation information, in addition to the above configuration.

[Action]

In the present invention, since the decoder 23 is provided in the data processing device 2, a start signal for each bank can be transmitted on the interface.

Therefore, only the same interface delay τ1 as the address delay is required for the delay, so that the memory cycle is significantly shortened.

In addition, since the start signal for each bank is output on the interface, the normality of the start state can be monitored and the reliability is improved by the correspondence between the bank start signal and the bank designation information.

〔Example〕

 (A) Description of one embodiment FIG. 2 is a configuration diagram of one embodiment of the present invention.

In this data processing system, two or more data processing devices 2-0, 2-1...
.. And the bank status monitoring unit 3 via a bus 4.

The bus 4 includes an address bus 4a, a data bus 4b, a bank start signal line 4c, and another control line 4d. The data processing devices 2-0, 2-1 ... and the memory devices 1-0, 1-1 , ... are connected. The other control line 4d is connected to the address bus 4
a, the data bus 4b, and other control signal lines other than the bank activation signal line 4c are collectively displayed. For example, a signal line transmitted from the data processing device 2-1 to the memory device 1-1, and conversely, From the memory device 1-1 to the data processing device 2-1
There is a signal line to send out.

An address bus 4a and a bank activation signal line 4c are input to the bank status monitoring unit 3.

 FIG. 3 is a block diagram of one embodiment of the present invention.

In the figure, the same components as those shown in FIGS. 1, 2 and 7 are denoted by the same reference numerals, and 14 is a DRAM control unit, which responds to the activation holding signal BOCYC of the activation state holding FF11. hand,
A memory element section, which will be described later, is activated and resets the activation state holding FF11 after a memory cycle (3 cycles). Reference numeral 15 denotes a memory element section, which is constituted by a DRAM and is accessed by an address BOAL of an address latch circuit 13 Things.

24a is a start instruction FF, which holds the bank 0 select signal of the decoder 23 for one cycle in synchronization with the clock CLK,
A circuit for generating a start signal BNKU0 of bank 0, 25 is a timing circuit, and a start circuit BNKU0 and a memory address CAB00
26a and 26b are drivers, respectively, which control the output timings of ~ 29, the activation signal BNKU0, the memory address CAB00
Through 29 are output at the timing of the timing circuit 25.

Note that the banks 1b, 1c, and 1d also have the same configuration as the bank 1a.

 FIG. 4 is a time chart of one embodiment of the present invention.

30-bit address information CAB00 to
Of the 29 bits, the portion designating the bank is two bits of CABs 28 and 29, and the remaining 28 bits CAB00 to 27 are used as addresses in each bank.

CAB00 to CAB29 are set in the address register 21 from the CPU 20 at the start of memory access, and the CABs 28 and 29 for 2-bit bank designation pass through the decoder 23 and start instruction FF2
Entered in 4a.

The start instruction FF24a is provided for each of the banks 1a to 1d. When the decoder 23 specifies the bank 0 (1a),
Start instruction FF24a is set, and start signal BNKU0 is output.

The activation signal BNKU0 is a signal for instructing activation of the bank 0 (1a), and only one slot is turned on.

The timing circuit 25 sends the activation signal BNKU0 and address information SAB00 to SAB29 from the drivers 26a and 26b to the interface.

When the activation signal BNKU0 reaches the memory device 1, the activation state holding FF11 of the bank 1a is set, and at the same time, the AND circuit 12 is opened, the set clock of the address latch circuit 13 is enabled, and the transmitted addresses SAB00 to SAB00 are output. Latch 27.

The output BOCYC of the activation state holding FF activates the DRAM control unit 14 to generate a timing and control signal of the memory element unit 15 receiving the address BOAL of the address latch circuit 13.

The start instruction FF24a is, as shown in FIG.
Since the start signal BNKU0 only needs to be transmitted to the start slot, the start state hold FF11 holds the start state until the end of the third slot where the memory access ends, as shown in FIG.

Therefore, when three slots (three bus cycles) of the memory access cycle are completed, the DRAM control unit 14 generates an access end slot signal to reset the active state FF11 and the address latch circuit 13.

The same applies to the case of selecting banks 1b, 1c and 1d, and interleave control can be performed as shown in FIG.

In this manner, by generating and sending a start signal for each bank in the data processing device 2, the start signal can be transmitted to the memory device quickly, and a desired bank can be started with τ1 of the delay on the interface. .

Therefore, the bus cycle of the memory interface can be shortened, and the speed of the system can be improved.

It will be further described that the present invention can reduce the operation time as compared with the conventional one. Now, in FIG. 7, the Derei the address register 21 and tau _4, decoder 23 in FIG. 3
Is τ ₂ ′, the delay of the activation instruction FF24 is τ ₄ ′, the delay of the driver 26a is τ ₃ ′, and the delay of the interface is τ ₁ ′.

In the conventional example, as shown in Figure 8 (A), even short Derei tau ₄ of the address register 21, since the τ _{1 +} τ _{2 +} τ ₃ long, long combined clock cycles to the τ _{1 +} τ _{2 +} τ ₃ I had to do it. In FIG. 8 (A), an extra time is created in clock cycle 1,
In a system operating with a synchronous clock, in order to make each clock cycle the same time, the clock cycle time is pulled by the delay time of a long path. In the conventional example, τ ₁ + τ ₂
The path at + τ ₃ becomes the critical path, which determines the length of the clock cycle.

On the other hand, in the present invention, as shown in FIG.
₂ ′ + τ ₄ ′ and τ ₃ ′ + τ ₁ ′ are divided into different clock cycles, ie, clock cycle 1 ′ and clock cycle 2 ′, and τ ₂ ′ + τ ₄ ′ τ ₃ ′ + τ
_The clock cycle itself is shortened because it is distributed so as to be ₁ 'in a well-balanced manner and without a margin time (wasteful time) as in the conventional example. That is, clock cycle 2 ′ ≒ τ ₃ ′ + τ ₁ ′ ≪τ ₁ + τ ₂
+ Τ ₃ = clock cycle 2, and the critical path τ ₃ ′ + τ ₁ ′ that determines the clock cycle in the present invention is much smaller than the conventional critical path τ ₁ + τ ₂ + τ ₃ , thereby reducing the clock cycle. Can be shorter.

Clock cycle 1 ′ = τ ₃ ′ + τ ₄ ′> τ ₄ , but since τ ₂ ′ + τ ₄ ′ ≒ τ ₃ ′ + τ ₁ ′, clock cycle 1 ′ does not adversely affect clock cycle 2 ′. Absent. Conversely, in the conventional example, although τ ₄ itself is smaller than τ ₂ ′ + τ ₄ ′, the processing speed becomes slow because the clock cycle 2 is large.

(B) Description of Another Embodiment FIG. 5 is a configuration diagram of another embodiment of the present invention, showing the configuration of the bank state monitoring unit 3.

In the figure, reference numeral 30 denotes a bank designation information holding FF, which holds 2-bit bank designation information SABs 28 and 29 on the address bus 4a, and 31 denotes a decoder, which is a bank designation information holding FF30.
Is decoded to generate a select signal for each bank.

Reference numeral 32 denotes a bank start signal holding FF, which holds a bank start signal of the bank start signal line 4c. Reference numerals 33a to 33d denote exclusive inversion OR circuits (ENOR). An exclusive-OR of the bank start signals BNKU0D to BNKU3D of the bank start signal holding FF32 to detect a match or mismatch, 34 is an AND gate,
The logical AND of the outputs of the ENORs 33a to 33d is performed to output the normality of the bank start signal and the bank designation information.

35a to 35d are counters, each bank start signal BNKU0
Enable status signal B0AVL to B of each bank which becomes low for 3 slots which is a memory cycle due to the fall of ~ BNKU3
A generator for generating 3AVL, 36a to 36d are AND gates, and a logical AND between the bank enable signal B0AVL to B3AVL and the bank activation signals BNKU0 to BNKU3, 37a is an OR gate, and AND gates 36a to 36d 37b is a flip-flop, and OR gate 3
The output of 7a is held for one slot (cycle).

38a is a NAND gate and AND gate 34
Signal OK1 indicating the normality of the output of the flip-flop 37b
38b is an OR gate, and the bank start signal BNKU0D of the bank start signal holding FF32
The one that takes the logical OR of BNKU3D, 39 is an AND gate,
The logical product of the output of the NAND gate 38a and the output of the OR gate 38b is taken and an error signal is notified to the data processing device.

FIG. 6 is a time chart of another embodiment of the present invention. The operation of the configuration of FIG. 5 will be described with reference to FIGS.

The 2-bit addresses SAB 28 and 29 on the address bus 4a of the data processing device 2 are temporarily set in the holding FF 30, and then converted to a bank select signal by the decoder 31.

The input / output signal of the bank designation holding FF 30 and the output signal of the decoder 31 have a time chart as shown in FIG. SAB28, SAB29 in order of the input signal names of bank designation holding FF30
The output signal names are SAB28D and SAB29D in order from the top, and 29 is the lower weight in SAB28 / SAB28D and SAB29 / SAB29D.

Then, output signal names of the decoder 31 are DEC0,
DEC1, DEC2, DEC3. The input signals SAB28 and SAB29 of the bank designation holding FF30 are in a high-impedance state except for CLKY1 and CLKY2, but normally become "1" because they are pulled up by a resistor. Therefore, DEC3 output is CLKCY1 and CLKCY2
BNKU3D of the holding FF32 in FIG. 5 is “0”.
In this case, the ENOR33d output is set to "0" and has no effect on operation.

On the other hand, the bank start signals BNKU0 to BNKU3 sent from the data processing device 2 are temporarily held by the holding FF32 and input to the ENOR circuits 33a to 33d with a delay of one clock.

In the ENOR circuits 33a to 33d, the bank start signal of the holding FF32 is used.
It is determined whether BNKU0D to BNKU3D match the bank select signal from the decoder 31.

If all match, the bank start signal on the interface and the bank designation information match, and all
The outputs of the ENOR circuits 33a to 33d become "1", and the OK1 signal of the output of the subsequent AND circuit 34 becomes "1".

The bank activation signals BNKU0 to BNKU3 are stipulated that only one signal is turned on for one slot when each bank is in a usable state. Therefore, if this rule is violated, that is, two or more bank activation signals Occur simultaneously, the OK1 signal of the AND circuit 34 does not become "1".

In this way, the correspondence between the bank start signal on the interface and the bank designation information is checked.

On the other hand, the bank activation signals BNKU0 to BNKU3 are
AND operations with the bank available state signals B0AVL to B3AVL are performed at 36a to 36d.

The bank enable state signals B0AVL to B3AVL usually indicate "high" bank enable, and the bank activation signals BNKU0 to BNKUB
At the falling edge of NKU3, a bank in use state of "low" for three memory cycles, that is, a bank unusable state is shown.

Therefore, when any bank start signal is generated, the output of any one of the AND gates 36a to 36d becomes "1", and the OK2 signal is set to "1" for the next one cycle via the OR gate 37a.

When the bank activation signals BNKU0 to BNKU3 are output when the bank is not in the usable state, that is, when the bank activation signal is equal to or more than two slots or the bank activation of the already activated bank is output, the OK2 signal is output. Does not become “1”.

These are the bank start signals by AND gate 39.
At the next cycle in which BNKU0 to BNKU3 are turned on, that is, when the bank activation signals BNKU0D to BNKU3D in FIG. 6 are turned on, they are checked and output as error signals.

That is, the OK2 signal is a signal for confirming normality during a period in which the bank start signal is on.

Therefore, as shown in FIG. 4, when the bank start signal is normally output, no error signal is generated, and when the bank start signal of the bank which is already started is generated as shown in FIG. 6, the OK1 signal is output. An error signal is generated by the "1" and the OK2 signal "0".

In this way, the correspondence between the bank start signal and the bank designation information and the normality of the output period of the bank start signal are checked, and the address line 4a, the decode circuit 23, the bank start instruction
Failures of the FF 24a, the drivers 26a and 26b, the address register 21, and the like are detected, and the reliability of memory access is improved.

It should be noted that the bank start signal holding FF32 of FIG. 5, exclusive OR circuits 33a to 33d, AND gates 36a to 36d, and an OR gate
The output waveforms of 37a, FF 37b, NAND gate 38a, and OR gate 38b are shown in FIG. 4 (normal state) and FIG. 6 (abnormal state).

A. Normal case In FIG. 5, the bank activation signal holding FF32 contains the bank activation signals BNKU0 and BNKU1 sent from the data processing device 2.
However, as shown in FIG. 4, the clock cycles CLKCY1, CLKC
When input to Y2, these are temporarily held in the holding FF32 and output as bank start signals BNKU0D and BNKU1D. On the other hand, the addresses SAB28 and 29 from the data processing device 2
Is temporarily held in the bank designation information holding FF30,
The decoding is performed at 31 and the decoding signals are input to ENORs 33a to 33d.

Therefore, when the bank start signal BNKU0 and the bank 0 address are input to CLKCY1, "1" (not shown) is output from the decoder 31 to CLKCY2, and this is output to ENOR 33a together with BNKU0D. Accordingly, the two inputs of ENOR 33a are both "1" in CLKCY2, both are "0" in CLKCY3, and the output of ENOR 33a is "1" in CLKCY2,3. Similarly, this CLKCY2,
In 3, the outputs of the other ENORs 33b to 33d are also "1", and OK1 is also "1".

On the other hand, the counters 35a to 35d output the bank activation signals BNKU0 to BNKU
Since “0” is output for 3 slots at the falling of NKU3,
The outputs of the AND gates 36a to 36d are as shown in FIG. 4. As a result, OK2 also becomes "1" in CLKCY2 and CLK3, the output of the NAND gate 38a becomes "0", and an error signal is output from the AND gate 39. There is no.

B. Abnormal case As shown in FIG. 6, before the three memory access cycles are completed, a bank start signal is sent to the same bank 0, and the bank address 0 is output to the address bus. The case will be described.

In this case, the outputs of ENOR33a to 33d are CLKCY2 to CLKC
The state shown in Y4 is obtained, and the output OK1 of the AND gate 34 is also as shown in FIG.

The outputs of the AND gates 36a to 36d are as shown in FIG. 6, and the outputs of the OR gate 37a are as shown in FIG.
OK2 based on this is also as shown in FIG. Therefore these O
Based on K1 and OK2, the output of the NAND gate 38a is as shown in FIG.

The output of the OR gate 38b is based on the BNKU0D,
As shown in FIG. 6, the output of these 38a and 38b causes the AND gate 39 to output an error signal as shown in FIG.

(C) Description of Another Embodiment In the above-described embodiment, the number of banks is four. However, the number of banks may be two or more, and the monitoring of the bank status is performed only by the correspondence between the bank activation signal and the bank designation information. There may be.

Although the present invention has been described with reference to the embodiments, the present invention can be variously modified in accordance with the gist of the present invention, and these are not excluded from the present invention.

〔The invention's effect〕

As described above, according to the present invention, the following effects can be obtained.

A decoder directly connected to the processor and connected to the memory via the interface line is provided, and a start signal for each bank is transmitted almost simultaneously with the address information. Only requires a short memory cycle,
High-speed memory access can be realized.

Since the bank state monitoring unit is provided separately from the data processing device provided with the decoder, the normality of the activation state can be monitored, and the probability of failure together with the decoder is low, contributing to the improvement of reliability.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention, FIG. 2 is a block diagram of one embodiment of the present invention, FIG. 3 is a block diagram of one embodiment of the present invention, FIG. FIG. 5 is a block diagram of another embodiment of the present invention, FIG. 6 is a time chart of another embodiment of the present invention, and FIG. 7 is an explanatory diagram of the prior art. FIG. 8 is an explanatory view of a clock cycle of the conventional example and the present invention. FIG. 9 is a time chart for explaining the operation of the present invention. In the figure, 1... Memory device, 2... Data processing device, 1a to 1d... Bank, 23... Decoder, 3...

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Koichi Odawara 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Co., Ltd. 72) Inventor Noboru Yamazaki 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (56) References JP-A-59-185083 (JP, A) JP-A-49-60442 (JP, A) 56-94451 (JP, A) JP-A-55-38603 (JP, A) Magazine "Transistor Technology", June 1981, (CQ Publishing Company) P268-269

Claims (2)

(57) [Claims] 1. A memory device (1) having a plurality of banks (1a to 1d) including at least an address holding means (13) and a memory element section (15), and a data processing for accessing the memory device (1). Device (2), wherein the data processing device (2) includes the plurality of banks (1a to 1d).
To specify the memory device (1) as a synchronous clock (CL
K) A memory access control device that accesses in synchronization with K), wherein the data processing device (2) is directly connected to the processor and transmits bank designation information from the processor.
A decoder (23) for decoding before the address information is output from the data processing device (2) to generate a start signal for each bank, and a start signal for the decoder (23) to the memory device ( 1) providing an interface line for transmitting the start signal in synchronization with the synchronous clock (CLK) at the same time as the address; A memory access control device for controlling activation of the banks (1a to 1d). 2. A bank status monitoring unit (3) for monitoring the normality of a correspondence between a bank start signal via said interface line and said bank designation information via an address bus, said memory device (1) and said data processing device. The memory access control device according to claim 1, wherein the memory access control device is provided outside of (2).