JP3071608U - Printing device - Google Patents

Abstract

(57) [Summary] To improve the efficiency by shortening the processing time when there is an interrupt to the CPU. An ASIC (4) is provided with a first register (20) that stores events that occur in a plurality of groups and a second register (21) that stores individual events included in each group for each group. When an interrupt is issued from the ASIC 4 to the CPU 5, the CPU 5 refers to the first register 20 and determines to which group the generated event belongs. Then, the event is determined by referring to the register corresponding to the group among the registers 22 to 25.

Description

[Detailed description of the invention]

[0001]

[Technical field to which the invention belongs]

 The present invention relates to a printing device such as an ink jet printer, and more particularly to a printing device capable of efficiently performing interrupt processing for a CPU.

[0002]

[Prior art]

 FIG. 7 is a block diagram illustrating an electrical configuration of the inkjet printer. In the figure, 1 is an inkjet printer (hereinafter simply referred to as a printer) as an example of a printing device, and 2 is a host device (hereinafter simply referred to as a host) including a personal computer or the like as an upper device connected to the printer 1. 3 is a control unit that sends and receives data to and from the host 2 and controls the printing operation, 4 is an ASIC (Application Specific IC) connected to the host 2, and 5 is based on an interrupt signal from the ASIC 4. A predetermined ROM, a CPU 6 for controlling the operation of the CPU 5, a ROM for temporarily storing data sent from the host 2, and a memory 7 for storing ink and the like. A carrier motor for transporting the carrier, 8 is a feed motor for transporting the paper, and 9 is ink from the print head of the ink cartridge. A printing unit 10 that prints on paper by ejecting an image is a display unit including an LED lamp and the like. As the control unit 3, an ASIC 4, a CPU 5, and a memory 6 which are integrated into one chip can be used.

The host 2 sends commands and data to the printer 1, and the control unit 3 starts and stops the carrier motor 7 and the feed motor 8 based on the commands and data, and prints on paper by the printing unit 9. Control to start / stop printing of. In this case, the ASIC 4 interrupts the CPU 5 when an event to be transmitted to the CPU 5 occurs. When receiving the interrupt signal from the ASIC 4, the CPU 5 determines what event the interrupt relates to, and executes a process corresponding to the event. For example, if the interrupt is related to the event of stopping the carrier motor, the CPU 5 controls the carrier motor 7 to stop. A printing apparatus in which the ASIC interrupts the CPU as described above is described in, for example, Japanese Patent Application Laid-Open No. 9-244823.

By the way, the above-mentioned interrupt signals are not individually prepared corresponding to each event, and the CPU 5 receives only one type of interrupt signal from the ASIC 4. Therefore, from the viewpoint of the CPU 5, it is known that a certain event has occurred due to the interrupt signal, but the content of the event cannot be understood only by the interrupt signal. For this reason, the ASIC 4 is provided with a register corresponding to the event that occurs, and the CPU 5 receiving the interrupt signal refers to this register to determine the content of the event that has occurred. I have.

FIG. 8 is a diagram showing a register provided in such an ASIC 4. Reference numeral 30 denotes an interrupt event register (hereinafter simply referred to as a register), which is a register having a predetermined number of bits, for example, 8 bits or 16 bits. Each bit 0, 1, 2,... Corresponds to each event. For example, bit 0 is print data write processing, bit 1 is carrier motor acceleration / deceleration data write processing, and bit 2 is feed motor write processing. Acceleration / deceleration data writing processing, bit 3 represents the end of printing, and bit 4 represents the event of stopping the carrier motor. If these bits are set to "1", it is determined that the event has occurred, and if "0" is set, it is determined that the event has not occurred.

When receiving the interrupt signal from the ASIC 4, the CPU 5 refers to the register 30 in order from bit 0 to the last bit, and searches for a bit in which “1” is set. Then, the bit in which "1" is set is read out, and processing corresponding to the bit is performed. For example, if "1" is set in the bit 4, the CPU 5 recognizes that the event of stopping the carrier motor has occurred, and controls the carrier motor 7 to stop. In this way, the CPU 5 can determine what event the interrupt relates to by referring to the register 30.

[0007]

[Problems to be solved by the invention]

 However, in the conventional printing apparatus, since the bits of the register 30 are provided corresponding to each of the occurrence events, the CPU 5 needs to refer to all the bits from the beginning to the end of the bits to determine the event. There is. Therefore, there is a problem in that the number of bits increases in accordance with the number of types of generated events, and it takes time to search the CPU 5 and the efficiency of interrupt processing is reduced.

In particular, when a small ASIC 4 is used for cost reduction, the load on the CPU 5 increases and the number of interrupts to the CPU 5 increases, resulting in an increase in the number of events and an increase in processing efficiency. Is remarkable.

The present invention solves the above-described problems, and an object of the present invention is to provide a printing apparatus in which the processing time when there is an interrupt to a CPU is shortened and the efficiency is improved.

[0010]

[Means for Solving the Problems]

 In order to solve the above-described problem, the present invention provides a first register that stores a group of events that occur and stores a plurality of events, and a second register that stores individual events included in each group for each group. It is a thing.

With this configuration, when an interrupt is issued to the CPU, first, the first register is referred to determine to which group the event that has occurred belongs. By referring to the second register, individual events belonging to the group are determined. Therefore, when referring to the second register, it is only necessary to search for the group determined by the first register, and it is not necessary to search the entire second register, so that the time required for the search is reduced. it can .

[0012]

[Embodiment of the invention]

 Hereinafter, an embodiment in which the present invention is applied to an ink jet printer will be described. Since the overall configuration of the printer is the same as the block diagram shown in FIG. 7, the description is omitted, and FIG. 7 is cited as an embodiment of the present invention.

FIG. 1 is a diagram showing a configuration of a main part of the present invention, and shows a register provided in the ASIC 4. The register includes a first register 20 composed of an interrupt Event Summary register and a second register 21 composed of a plurality of Event registers 22 to 25.

The first register 20 is a 4-bit register, and stores generated events in four types. That is, bit 0 is Data Write Event, which represents an event related to data writing. Bit 1 is a Motor Move End Event, which indicates an event related to the stop of the motor. Bit 2 is a Parallel Event, which represents an event related to data transmission / reception performed with the host 2 via the parallel port. Bit 3 is a Timer Event, which indicates an event relating to the timer operation. If "1" is set in these bits, the event has occurred, and if "0" is set, the event has not occurred.

On the other hand, the Event register constituting the second register 21 is composed of four registers corresponding to the four types of groups in the first register. That is, reference numeral 22 denotes a Data Write Event register, which corresponds to the group of bit 0 of the first register 20, and represents three types of events included in the group by bits 0 to 2. Reference numeral 23 denotes a Motor Move End Event register, which corresponds to the group of bit 1 of the first register 20, and represents three types of events included in the group by bits 0 to 2. Reference numeral 24 denotes a parallel event register, which corresponds to the group of bit 2 of the first register 20, and represents two types of events included in the group by bits 0 to 1. Reference numeral 25 denotes a Timer Event register, which corresponds to the group of bit 3 of the first register 20, and represents two types of events included in the group by bits 0 to 1.

Next, details of each of the Event registers 22 to 25 will be described. The Data Write Event register 22 is a 3-bit register, and the event of bit 0 is Print Data Write, which is an event representing the writing of print data. The event of bit 1 is Carrier Ramp Data Write, which is an event representing the writing of acceleration / deceleration data of the carrier motor 7. The event of bit 2 is Feed Ramp Data Write, which is an event indicating the writing of the acceleration / deceleration data of the feed motor 8.

The Motor Move End Event register 23 is also a 3-bit register, and the event of bit 0 is Carrier Print End, which is an event indicating the end of printing. The event of bit 1 is Carrier Move End, which is an event indicating that the carrier motor 7 has stopped. The event of bit 2 is Feed Move End, which is an event indicating that the feed motor 8 is stopped.

The parallel event register 24 is a 2-bit register, and the event of bit 0 is a command event, which is an event representing a command transmission from the host 2 to the printer 1. The event of bit 1 is a Parallel Line Event, which is an event representing data transmission from the printer 1 to the host 2.

The Timer Event register 25 is also a two-bit register, and the event of bit 0 is Timer 1 Event, which is an event indicating that the interrupt has a time interval of, for example, 1 msec. The event of bit 1 is a Timer 2 Event, which is an event indicating that the interrupt has a time interval of, for example, 25 msec. Timer 1 Event is an interrupt for sampling for detecting a key operation or a sensor output, for example, and Timer 2 Event is an interrupt for blinking an LED lamp of the display unit 10, for example.

The second register is configured as described above. As in the first register 20, if a bit is set to “1” in each of the event registers 22 to 25, the event occurs. If "0" is set, it is determined that the event has not occurred.

FIGS. 2 to 6 are flowcharts showing the interrupt processing of the printer 1 having the above configuration. Hereinafter, the operation of the interrupt processing will be described with reference to this flowchart. In FIG. 2, the CPU 5 monitors whether or not there is an interrupt from the ASIC 4 (step S1). When receiving an interrupt signal from the ASIC 4 (step S1 YES), the first register 20 of the ASIC 4 changes the bit 0 to the bit 3 (Step S2), and it is searched whether or not an event has occurred, that is, whether or not there is a bit in which "1" is set (Step S3). If all bits are “0” (step S3NO), the process ends without doing anything. If there is a bit with “1” set (step S3YES), the type of event is determined based on the bit. It is determined (steps S4 to S6).

If “1” is set in bit 0, it is determined that the event is a Data Write Event (step S4 YES), and the process proceeds to step S11 in FIG. If “1” is not set in bit 0 (NO in step S4), it is next determined whether or not the event is a Motor Move End Event (step S5). If "1" is set in bit 1, it is determined that the event is a Motor Move End Event (step S5YES), and the process proceeds to step S21 in FIG. If "1" is not set in bit 1 (step S5 NO), it is next determined whether or not the event is a Parallel Event (step S6). If "1" is set in bit 2, it is determined that the event is a parallel event (step S6 YES), and the process proceeds to step S31 in FIG. If the determination result in step S6 is not Parallel Event (NO in step S6), it is determined that the event is a Timer Event, and the process proceeds to step S41 in FIG.

As described above, when there is an interrupt from the ASIC 4, the CPU 5 first refers to the first register 20 to search for a group of events that have occurred. Then, if the group is known, the event is searched for by referring to the Event registers 22 to 25 of the second register 21 corresponding to the group in accordance with the procedure of FIGS. 3 to 6 described below.

In step S 4 of FIG. 2, if the group of the occurred event is the Data Write Event, the process proceeds to step S 11 of FIG. 3, and the Data Write Event register 22 in the second register 21 is referred to (step S 11). It is searched whether or not an event has occurred, that is, whether or not there is a bit in which "1" is set (step S12). If all bits are "0" (NO in step S12), the process returns to step S3. If there is a bit in which "1" is set (YES in step S12), an event is determined based on the bit (step S13). , S15).

If “0” is set in bit 0, it is determined that the event is Print Data Write (step S 13 YES), and print data writing processing is performed (step S 14). Is reset (step S18), and the process returns to step S3. If the event is not Print Data Write (step S13: NO), then it is determined whether or not it is Carrier Ramp Data Write (step S15). If "1" is set in bit 1, it is determined that the event is Carrier Ramp Data Write (step S15 YES), and the acceleration / deceleration data write processing of carrier motor 7 is executed (step S16). Thereafter, bit 1 is reset (step S18), and the process returns to step S3. If it is determined in step S15 that the event is not Carrier Ramp Data Write, the event is determined to be Feed Ramp Data Write (step S15NO), and the acceleration / deceleration data writing process of the feed motor 8 is executed (step S15). (Step S17) After that, the bit 2 is reset (Step S18), and the process returns to Step S3. Note that bit 0 of the first register 20 is also reset in conjunction with the reset of bits 0 to 2.

As described above, when the group of the generated event is the Data Write Event, the CPU 5 only needs to refer to the Data Write Event register 22 corresponding to the group, and refer to the other Event registers 23 to 25. do not have to. Therefore, it is possible to efficiently search for the occurred event in a short time.

Next, in step S 5 in FIG. 2, if the group of the occurred event is Motor Move End Event, the process proceeds to step S 21 in FIG. 4, and refer to the Motor Move End Event register 23 in the second register 21. Then, whether or not an event has occurred, that is, whether or not there is a bit in which "1" is set is searched (step S22). If all bits are "0" (step S22NO), the process returns to step S3, and if there is a bit in which "1" is set (step S22YES), an event is determined based on the bit (step S23, S25).

If “0” is set in bit 0, it is determined that the event is Carrier Print End (step S 23 YES), a print end process is performed (step S 24), and then bit 0 is reset. Then (step S28), the process returns to step S3. If the event is not Carrier Print End (step S23 NO), it is next determined whether or not it is Carrier Move End (step S25). If "1" is set in bit 1, it is determined that the event is Carrier Move End (step S25ES), and the stop process of the carrier motor 7 is executed (step S26). Is reset (step S28), and the process returns to step S3. If it is determined in step S25 that the event is not Carrier Move End, the event is determined to be Feed Move End (step S25 NO), and the stop process of the feed motor 8 is executed (step S27). Is reset (step S28), and the process returns to step S3. Note that bit 1 of the first register 20 is also reset in conjunction with the reset of bits 0 to 2.

As described above, when the group of the generated event is the Motor Move End Event, the CPU 5 only needs to refer to the Motor Move End Event register 23 corresponding to the group, and the other Event registers 22 and 24 , 25 need not be referred to. Therefore, it is possible to efficiently search for the occurred event in a short time.

Next, in step S 6 of FIG. 2, if the group of the occurred event is Parallel Event, the process proceeds to step S 31 of FIG. 5, and the parallel event register 24 in the second register 21 is referred to (step S 6). S31), whether or not an event has occurred, that is, whether or not there is a bit in which "1" is set is searched (step S32). If all the bits are "0" (step S32 NO), the process returns to step S3, and if there is a bit with "1" set (step S32 YES), an event is determined based on the bit (step S33). .

If “1” is set in bit 0, it is determined that the event is a Command Event (step S33 YES), and a command is received from the host 2 (step S34). Is reset (step S36), and the process returns to step S3. If the event is not a Command Event, it is determined that the event is a Parallel Line Event (step S33 NO), data transmission to the host 2 is executed (step S35), and then bit 1 is reset (step S36). Then, the process returns to step S3. Note that, in conjunction with the reset of the bit 0 and the bit 1, the bit 2 of the first register 20 is also reset.

As described above, when the group of the occurred event is the Parallel Event, the CPU 5 only needs to refer to the Parallel Event register 24 corresponding to the group, and refer to the other Event registers 22, 23, and 25. do not have to. Therefore, it is possible to efficiently search for the occurred event in a short time.

Next, in step S 6 of FIG. 2, if the group of the occurred event is not Parallel Event, the process proceeds to step S 41 of FIG. 6, and the timer event register 25 in the second register 21 is referred to (step S 6). S41), whether or not an event has occurred, that is, whether or not there is a bit in which "1" is set is searched (step S42). If all the bits are "0" (NO in step S42), the process returns to step S3, and if there is a bit in which "1" is set (step S42 YES), an event is determined based on the bit (step S43). .

If “0” is set in bit 0, it is determined that the event is a Timer 1 event (step S43 YES), and interrupt processing is executed, for example, every 1 msec (step S44). 0 is reset (step S46), and the process returns to step S3. If the event is not a Timer 1 Event, it is determined that the event is a Timer 2 Event (NO in step S43), and an interrupt process is performed, for example, every 25 msec (step S45), and then bit 1 is reset. (Step S46), returning to step S3. Note that, in conjunction with the reset of the bit 0 and the bit 1, the bit 3 of the first register 20 is also reset.

As described above, when the group of the occurred event is the Timer Event, the CPU 5 only needs to refer to the Timer Event register 25 corresponding to the group, and need not refer to the other Event registers 22 to 24. Absent. Therefore, it is possible to efficiently search for the occurred event in a short time.

In the above embodiment, an ink jet printer has been described as an example of a printing device. However, the present invention is not limited to this, and can be applied to various printing devices such as a laser printer and an ink ribbon printer. is there.

[0037]

[Effect of the invention]

 According to the present invention, by grouping events that occur, it is only necessary to search for individual events by focusing on the group.Therefore, it is not necessary to refer to the entire area of the register, and the search time is reduced and processing is performed. Efficiency can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a main part of the present invention.

FIG. 2 is a flowchart showing the operation of the present invention.

FIG. 3 is a flowchart showing the operation of the present invention.

FIG. 4 is a flowchart showing the operation of the present invention.

FIG. 5 is a flowchart showing the operation of the present invention.

FIG. 6 is a flowchart showing the operation of the present invention.

FIG. 7 is a block diagram illustrating an electrical configuration of the printer.

FIG. 8 is a diagram illustrating an interrupt process in a conventional example.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 printer (printing device) 2 host 3 control unit 4 ASIC 5 CPU 6 memory 7 carrier motor 8 feed motor 9 printing unit 10 display unit 20 first register 21 second register 22 Data Write Event register 23 Motor Move End Event register 24 Parallel Event register 25 Timer Event register

Claims (4)

[Utility model registration claims] 1. A printing apparatus having a control unit for transmitting and receiving data to and from a higher-level device, wherein the control unit controls a printing operation. The control unit includes a CPU and an interrupt event for the CPU. A first register that stores a group of events that occur, and a second register that stores individual events included in each group for each group. A printing device characterized by the above-mentioned. 2. The method according to claim 1, wherein the CPU is configured to perform a first
The printing apparatus according to claim 1, wherein the group of the generated event is determined by referring to the register of the second register, and the content of the generated event is determined by referring to the register of the group corresponding to the group among the second registers. 3. The printing apparatus according to claim 2, further comprising an ASIC for transmitting / receiving data to / from a higher-level device and interrupting a CPU, wherein said first and second registers are provided in said ASIC. apparatus. 4. The first group of registers includes a group of events relating to data writing, a group of events relating to motor stoppage, a group of events relating to data transmission / reception with the host, and an event relating to timer operation. 4. The printing apparatus according to claim 1, further comprising a group.