JP3070755B2 - Transmission circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]

The present invention relates to a switch for a broadband ISDN, particularly an ATM (Asynchronous
ous Transfer Mode) In connection with the transmission path between devices, such as a communication path device of an exchange of a system, between devices, for example, between frames, between shelves, between boards, etc., especially, the number of wiring of transmission lines in the devices and between devices is minimized. The present invention relates to a transmission circuit suitable for performing stable data transfer by absorbing a phase shift between transmission and reception.

[Prior art]

A communication path device of an ATM exchange often processes ATM cells (fixed-length packets in the ATM system) in the device with low-speed parallel signals. When the ATM cells are transmitted as parallel signals within the device or between the devices, the number of wires increases in proportion to the circuit switching capability, and therefore, a device for reducing the number of wires is required. In response to this request, a promising method is to convert the parallel signal ATM cell into a serial signal and include the clock signal and frame synchronization signal components in the ATM cell, thereby reducing the number of wires on the transmission line. is there. For example, the transmission circuit shown in the paper "IEICE Technical Report / Switching System Study Group SSE89-123" Development of LSI for ATM Cell Transfer "" is one example. FIG. 15 shows a functional block diagram thereof. This example is a transmission circuit that transmits an ATM cell by using an optical fiber and an electric wire cable as a transmission path in a transmission between devices or between devices. The transmitting side sends the parallel signal AT from the cell data input terminal.
An ATM cell synchronization signal is input from the M cell and cell synchronization signal terminals, and a parallel signal side clock signal is input from the clock input terminal. The encoder encodes ATM cells to enable AC coupling, which is a characteristic of optical transmission required for transmission over an optical fiber, and to suppress DC components. Synchronization pattern insertion
A synchronization pattern is generated using the encoding violation and attached to the ATM cell. The multiplying PLL generates a serial signal side clock signal from the parallel signal side clock signal, and converts the parallel signal ATM cell into a serial signal by parallel-serial conversion. The ATM cell is connected to an externally added driving circuit by an ECL level through line driving, and converts an electric signal to an optical signal by an electro-optical conversion element,
Send to optical fiber. On the receiving side, the optical signal input from the optical fiber is converted into an electric signal by an opto-electric conversion element added to the outside, the signal is amplified by an amplifier circuit, and input to the ECL level for waveform shaping.
The clock extraction PLL generates a serial signal side clock signal based on the serial signal ATM cell, and converts the serial signal ATM cell via waveform reproduction into a parallel signal by serial-parallel conversion. Synchronization pattern detection detects the synchronization pattern from the ATM cell, determines the cell synchronization of the ATM cell,
Determine the beginning of the cell. The decoder returns the ATM cells encoded on the transmission side to the original state and writes the ATM cells in the FIFO. The FIFO outputs a synchronization signal of an ATM cell from a cell data output terminal and a synchronization signal of an ATM cell from a cell synchronization signal terminal in synchronization with a clock signal input from a read clock terminal. Also,
In this example, elements for converting electrical signals and optical signals are added to the outside of the transmission circuit chip, and furthermore, analog circuits such as waveform shaping and clock extraction PLL and processing of ATM cells in the same chip. Is a configuration in which digital circuits for performing the above are mixed.

[Problems to be solved by the invention]

In the above prior art, in transmitting ATM cells in a device or between devices, a transmission path between transmission circuits is performed by optical transmission, so an electro-optical conversion element, a driving circuit, a photoelectric conversion element, and an amplification circuit are added to the outside. Therefore, there is a problem that the number of circuit components is large, the mounting area of the components is large, and it is not suitable for downsizing the entire transmission circuit. In optical transmission, an encoder is used to encode an original signal and generate a synchronization pattern by encoding violation.
Since the decoder is used, there is a problem that the scale of the transmission circuit becomes large. In addition, since the high-speed transmission between the drive circuit, amplification circuit, and transmission circuit added to the outside was coupled by the ECL level, the power consumption of the transmission circuit increased, making it difficult to save power. is there. In addition, since the clock extraction PLL and the waveform shaping are configured by analog circuits, the digital circuit and the analog circuit are mixed and there is a problem that the transmission circuit cannot be easily integrated into one chip. In addition, there is no function of transmitting and receiving a control signal between devices via a transmission circuit, so that there is a problem that a control signal cannot be transmitted and received. The present invention realizes high-speed ATM cell transmission of serial signals in and between devices, and realizes one or more pairs of transmitting / receiving circuits on one chip without the need for external additional components, and achieves low power consumption. The purpose is to do.

[Means for Solving the Problems]

In order to achieve the above object, the transmission circuit includes a bit phase synchronization circuit, a serial / parallel conversion circuit, a byte synchronization circuit, a cell synchronization circuit, an elastic store memory circuit for reception, a synchronous pattern insertion circuit, and an elastic store memory circuit for transmission. , A circuit such as a parallel-serial conversion circuit, a transmission drive element, and a reception element are configured on the same chip. In order to make the transmission circuit a simple configuration, transmission by optical fiber was abolished, encoders and decoders for encoding were deleted, and only electrical transmission by electric wires and cables was possible. Instead of generating a synchronization pattern by encoding violation, a fixed-length synchronization pattern is inserted. Further, in order to facilitate the integration of the transmission circuit into one chip, the clock extraction PLL circuit and the analog circuit such as the waveform generation are deleted, and the transmission circuit is constituted only by the digital circuit in which the analog circuit and the digital circuit are not mixed. In addition, in order to save the power of the transmission circuit chip, the high-speed portion based on the ECL level on the transmission line side and the entire transmission circuit are configured by low power consumption CMOS elements. Further, in order to absorb a phase shift between the transmission line side and the device side and perform accurate data transfer, an elastic store memory for transmission and reception is mounted on the same chip. Furthermore, in order to transmit and receive control signals between the devices, the transmitting side inserts and transfers the control signal into an empty area of the additional byte of the ATM cell, and the receiving side extracts and receives the control signal. Is enabled.

[Action]

The cell synchronization of the ATM cell can be performed by inserting an arbitrary fixed-length synchronization pattern into the ATM cell and detecting it on the receiving side. In this case, a malfunction may occur if the same pattern as the synchronization pattern is included in the ATM cell. Therefore, malfunctions such as bit errors can be prevented by providing several stages of protection functions in the synchronization pattern mismatch detection sequence during synchronization determination and the synchronization pattern match detection sequence during synchronization determination. In addition, by operating the transmission circuit of the transmission apparatus and the transmission path circuit of the transmission circuit of the reception apparatus with clock signals from the same clock source, transmission can be performed without providing a clock extraction circuit for each transmission circuit. Accurate data transfer can be realized by adjusting the phase of the clock signal and the received data on the receiving side of the circuit. Further, by digitizing the transmission circuit and configuring the transmission drive element and the reception element by CMOS elements, the entire transmission circuit can be formed into one chip using a CMOS-LSI gate array or the like. In addition, the means for temporarily storing ATM cells input from the transmission path side and reading the ATM cells with a slight delay on the device side can absorb the phase shift, so that data transfer can be performed correctly. It is possible to follow within a range of phase variation due to variation in delay of elements in the chip, power supply fluctuation during operation, temperature fluctuation, and the like. In addition, by transmitting a device control signal to an empty area of an additional byte of an ATM cell and transmitting / receiving the ATM cell, a control signal can be transmitted / received without adding a new signal line.

【Example】

An embodiment of the present invention will be described below with reference to FIGS. 1 to 14. FIG. 1 shows the inside of an apparatus according to an embodiment of the present invention;
FIG. 14 is a configuration diagram of a transmission circuit between devices and the like, and FIG. 14 is a diagram showing a use form of a transmission circuit in a communication path device of an ATM exchange. First, the use form of the transmission circuit in the communication path device of the ATM exchange will be described with reference to FIG. Fig. 14 (a) is an ATM
FIG. 14 (b) is a data structure diagram of the device side and the transmission line side, and FIG. 14 (c) is a diagram of the inside of the device;
FIG. 3 is a diagram illustrating a transmission form of an ATM cell between devices. The data handled between the ATM exchanges is a fixed-length packet ATM cell, which is used in the transmission circuit of the present embodiment.
The TM cell includes a header section including a synchronization pattern and routing information, and an information section for storing transfer data.
The cell length of the ATM cell is the cell length specified in the CCITT recommendation.
Although it is basically 53 bytes, it is 54 bytes because the synchronization pattern is added for 1 byte. Further, additional information necessary for processing in the apparatus may be added, and the number is not limited to 54 bytes. FIG. 14 (b) shows the data structure of the device and the transmission path. The ATM cell on the device side stores 8-bit parallel signal data (20
MH _z) and constituted by a frame sync signal and the clock signal, and only the data of the serial signal (160MH _z) is a transmission line side via a transmission circuit. Common clock signal on the transmission line side (160MH _z) are input to the transmission circuit of each device is used as a clock signal on the transmission line side. FIG. 14 (c) shows the transmission form of the ATM cell in the device and between the devices, the transmission a between the rack A and the rack B, the transmission b between the shelf 1 and the shelf 2 in the rack B, and the shelf of the rack B. 3 shows transmission c between the substrate 1 and the substrate 2. The transmission circuit is used in a transmission path in a device or between devices, for example, between frames, between shelves, between substrates, or the like. Next, a transmission circuit between devices according to an embodiment of the present invention will be described with reference to FIG. The transmission circuit includes a bit phase synchronization unit 1, a serial / parallel conversion unit 2, a byte synchronization unit 3, a cell synchronization unit 4, an elastic storage memory unit for reception 5, a synchronization pattern insertion unit 6, an elastic storage memory unit for transmission 7, It comprises a parallel-serial conversion unit 8.
The transmission line side data input signal (DIN) is input to the data input (DI) of the bit phase synchronization section 1
The data output (DO) is input to the data input (DI) of the serial / parallel conversion unit 2 and output as the transmission path side folded data output signal (DDOUT). The data output (DO) of the serial / parallel converter 2 is input to the data input (DI) of the byte synchronizer 3. The synchronization pattern match output (IOUT) of the byte synchronization unit 3 is input to the synchronization pattern match input (IIN) of the cell synchronization unit 4, and the synchronization pattern detection position output (ITOUT) of the cell synchronization unit 4 is Input to synchronous pattern detection position input (ITIN). The synchronization determination output (SO) of the cell synchronization unit 4 is output as a synchronization state output (SOUT), and the frame output (FO) of the cell synchronization unit 4 is a writing frame input (WF) of the reception elastic store memory unit 5.
I) is entered. Data output (DO) of byte synchronization unit 3
Is input to the write data input (WDI) of the elastic storage memory unit 5 for reception. The read data output (RDO) of the reception elastic store memory unit 5 is output as a device-side reception data output signal (RDOUT). The device-side received frame input signal (RFRMIN) is input to the read frame input (RFI) of the elastic storage memory unit 5 for reception. Device side receive clock input signal (RCKIN)
Is input to the read clock input (RCI) of the elastic storage memory unit 5 for reception. The device-side transmission data input signal (SDIN) is input to the data input (DI) of the synchronization pattern insertion unit 6, and the device-side transmission frame input signal (SFRM)
IN) is input to the frame input (FI) of the synchronization pattern insertion unit 6. Data output (DO) of synchronous pattern insertion unit 6
Is input to the write data input (WDI) of the transmission elastic store memory unit 7, and the read data output (RDO) of the transmission elastic store memory unit 7 is input to the data input (DI) of the parallel-serial conversion unit 8. The data output (DO) of the parallel-to-serial converter 8 is input to the transmission path side data output signal (DOUT). The device-side transmission clock input signal (SCKIN) is input to the clock input (CI) of the synchronization pattern insertion unit 6, and the synchronization pattern insertion unit 6
Is output to the write clock input (WCI) of the transmission elastic store memory unit 7. The transmission line side clock input signal (CKIN) is input to the clock input (CI) of the bit phase synchronization unit 1, and the clock output (CO) of the bit phase synchronization unit 1 is input to the clock input (CI) of the serial / parallel conversion unit 2. The clock output (CO) of the serial / parallel conversion unit 2 is input to the byte synchronization unit 3
And the clock input (CI) of the cell synchronization unit 4 and the clock output (C
O) is input to the write clock input (WCI) of the elastic storage memory unit 5 for reception. The transmission-side clock input (CKIN) is input to the clock input (CI) of the parallel-serial conversion unit 8, and the clock output (CO) of the parallel-serial conversion unit 8 is the read clock of the transmission elastic store memory unit 7. Input to input (RCI). This embodiment includes a CMOS circuit including the transmission circuit having the above-described configuration, the transmission drive element and the reception element on the transmission path side.
It is made into one chip by LSI. Next, a reception operation of inputting an ATM cell from the transmission path side and outputting the ATM cell to the apparatus side will be described. Transmission side data input (DIN)
The ATM cells of the serial signal input (160MH _z) input to the data input of a bit phase synchronization section 1 (DI) from the transmission line side clock input is a clock signal having different phases the same frequency (160MH _z) (CKIN) Capture data correctly. The bit phase synchronization unit 1 can be configured by the following conventional example and the like. One example is the 1986 International Zurich Seminar on Digital Communication, C4.1-C4.4 (1986 International Zurich S
eminar on Digital Communications Transactions C4.1−C4.
4) The bit phase synchronization circuit. Another example is Japanese Patent Application No. Sho 6
A “bit phase synchronization circuit” disclosed in Japanese Patent Application Laid-Open No. 3-560811 and a four-phase clock signal input thereto are input to a transmission line side clock input (CK)
IN) and a clock generation circuit or the like created by delaying by 90 degrees at a time. The signal line of the transmission line between the transmission circuits connects the transmission circuit and the reception circuit in a one-to-one manner for the purpose of preventing signal reflection and the like. However, in consideration of the connection of the reception input of a plurality of transmission circuits to the transmission output of one transmission circuit, the bit phase synchronizing unit 1 converts the bit-synchronized data output (DO) to the transmission path side folded data output signal (DO). DDOU
Output to T). By connecting this signal to the reception input of the next transmission circuit, the transmission output of one transmission circuit is connected to the reception input of a plurality of transmission circuits while the signal line of the transmission path is connected one-to-one. Is equivalently possible. Next the serial-parallel conversion unit 2 of the bit phase synchronization section 1, it is converted to independently 20MH _z 8-bit parallel signals ATM cells 160MH _z serial signal byte leading position. The clock input of 160MH _z a (CI) by dividing, and outputs to create a clock signal 20MH _z clock output (CO).
The byte synchronization unit 3 determines the byte head position by detecting an arbitrary fixed-length synchronization pattern from the header of the ATM cell, and switches back to the state before transmission. In this embodiment, the synchronization pattern is composed of 8 bits. The cell synchronization unit 4 determines the ATM cell start position based on the synchronization pattern detection position of the byte-synchronized ATM cell, and determines the cell synchronization. The ATM cell in which the cell synchronization has been determined is written into the elastic storage memory unit 5 for reception. afterwards,
The device-side read data output (RDOUT) is output at a timing delayed by several clocks. At this time, the reception elastic store memory unit 5 allows the communication between the transmission path side and the apparatus side.
Absorbs phase shifts in ATM cells and clock signals. Next, a transmission operation of inputting an ATM cell from the device side and outputting the ATM cell to the transmission path side will be described. Synchronization pattern insertion unit 6, apparatus in synchronization pattern insertion position of the ATM cell of the transmission data input signal 20MH _z 8-bit parallel signals input from (SDIN), byte synchronization section in any required to establish byte synchronization fixed Insert a long sync pattern. The ATM cell into which the synchronization pattern has been inserted is written into the transmission elastic store memory unit 7. Thereafter, data is read at a timing delayed by several clocks. Transmitting elastic store memory unit 7 includes a 20MH _z of the device-side transmission clock input signal (SCKIN), created by dividing by the parallel serial conversion unit 8 based on the transmission line side clock input signal (CKIN) of 160MH _z in order to absorb the phase shift caused by variations in the clock signal of the chip element for 20MH _z. ATM cells read out from the transmission elastic store memory section 7 converts the parallel signal 20MH _z in the parallel-serial converter 8 into a serial signal of 160MH _z, and outputs the transmission line side data output signal (DOUT). Next, the configuration and operation of the byte synchronization unit will be described with reference to FIGS. FIG. 2 is a detailed block diagram of the byte synchronization unit, and FIG. 3 is an operation timing chart of the byte synchronization unit. ATM converted by the serial-parallel conversion unit serial signal 160MH _z to 8-bit parallel signal 20MH _z
Cell entered from the data input (DI), in synchronization with the clock input of 20MH _z (CI), taken into the input register 301 and the next stage of the input register 302. Using the 7-bit output of the input register 301 and the 8-bit output of the input register 302, 15-bit width data is created and shifted by 1 bit to create eight types of 8-bit data. These are compared with sync patterns of an arbitrary fixed length by comparators 303 to 310. Since the synchronization pattern of the embodiment is 8 bits, the comparator 30
3 to 310 are constituted by 8-bit coincidence comparators. Comparator 303
Is eight bits of bits 15 to 8, and the comparator 304 is bits 14 to
7, the comparator 305 has 8 bits of bits 13 to 6, the comparator 306 has 8 bits of bits 12 to 5, and the comparator 307
Is 8 bits of bits 11 to 4, and the comparator 308 is
3, the comparator 309 examines the 8 bits of the bits 9 to 2, and the comparator 310 examines the 8 bits of the bits 8 to 1. If all the comparators do not match the synchronization pattern, the same comparison check is repeated for the next 15 bits after shifting by 8 bits. When any one of the comparators matches the synchronization pattern, for example, when the comparator 307 matches (see FIG. 3), the 11th bit which is the first bit of the detected byte position is set to the head of the byte. Determine the position. Based on this decision, the 15-bit width data is re-cut by the selector 314 into an 8-bit parallel signal, fetched into the output register 316, and output to the data output (DO). Further, the comparison signals of the comparators 307 to 310 are taken into the register 313, the output of the comparator 307 that matches the synchronization pattern is selected by the selector 315, taken into the register 317, and output to the synchronization pattern match output (IOUT). Comparators 303 to 310 are
Since it is not always the case that only one comparator outputs a coincidence signal, the priority is set using the priority control 311 and fixed to any one. The selection signal subjected to the priority control is taken into the register 312 at the timing of the synchronous pattern match detection position input (ITIN), and switches between the selector 314 and the selector 315. The synchronization pattern used in the byte synchronization unit is
It is also possible to use a synchronization pattern (HEC) generated by a header check sequence. The byte synchronization unit of this system includes an HEC detection circuit that detects a synchronization pattern,
The error correction circuit performs error correction of the header part, and the information part is composed of a descramble circuit for restoring data scrambled by a specific generator polynomial. Next, the configuration and operation of the cell synchronization unit will be described with reference to FIGS. 4, 5, and 6. FIG. FIG. 4 is a detailed block diagram of the cell synchronization unit. FIG. 5 (a) is an operation timing diagram when the synchronization of the cell synchronization unit is determined. FIG. 5 (b) is a synchronization diagram of the cell synchronization unit. It is an operation timing chart at the time of uncertainty. When the byte synchronization of the ATM cell is determined, the cell synchronization unit determines the ATM pattern based on the byte position of the ATM cell that has detected the synchronization pattern.
The cell synchronization position is determined by determining the cell head position of the cell. AT
A 54-base counter 402 and a timing generator 403 operating in synchronization with the M cell generate and output a synchronous pattern detection position output (ITOUT) and a frame output (FO). The cell synchronization unit
A backward protection function is provided to prevent cell synchronization from being determined by a synchronization pattern match signal at an incorrect synchronization pattern detection position. This function is to determine the cell synchronization when the cell synchronization is uncertain and the synchronization pattern coincidence signal is input several times continuously at the same synchronization pattern detection position (see FIG. 5 (a)). In addition, a forward protection function is provided to prevent loss of cell synchronization due to a bit error or the like that occurs during cell synchronization determination. This function is to make cell synchronization indefinite when cell synchronization is being determined and a synchronization pattern match signal has not been input several times continuously at the synchronization pattern detection position (see FIG. 5 (b)). The control of these cell synchronization units is controlled by a backward protection counter.
405, forward protection counter 406, backward protection threshold comparator 40
7. This is performed by a forward protection threshold comparator 408, a synchronization determination JK flip-flop 409, and a counter control 404 that controls the states of the backward protection counter and the forward protection counter. FIG. 6A is a truth table of the operation of the counter control 404, and FIG. 6B is a logic diagram of the counter control 404. A cell synchronization determination signal indicating that the cell synchronization of the ATM cell has been determined is output to a synchronization determination output (SO). Next, the configuration and operation of the elastic storage memory unit for reception will be described with reference to FIG. 7 and FIG. FIG. 7 is a detailed block diagram of the reception elastic store memory unit, and FIG. 8 is an operation timing chart of the reception elastic store memory unit. The elastic store memory is a phase shift absorbing circuit for correctly performing data transfer by means for slightly delaying the read timing with respect to the write timing. If the phases of the writing side and the reading side are shifted, normal data transfer is not performed. FIG. 7 is a block diagram of an elastic storage memory unit for reception when a register for temporarily storing transfer data is composed of six stages. Write data input (WDI)
Is input to the D terminal of the transfer data temporary storage registers 501 to 506, and is synchronized with the write clock input (WCI) according to the output (QA to QF) of the write enable counter 507 of the six-stage ring counter. To write sequentially.
On the other hand, the read side selects the output of the transfer data temporary storage registers 501 to 506 via the selector 508 according to the output (Q) of the read selection counter 509 of the six-stage ring counter, and inputs the read clock (RCI). ) In synchronization with the output register 510 and output it to the read data output (RDO) (see FIG. 8). The phase adjustment between the write side and the read side is performed by the write frame input (WFI) and the read frame input (RFI), and the delay from the write timing to the read timing is adjusted to a delay of 3 bytes. As a result, the read timing is ±
Even if the data is shifted by 3 bytes, the data transfer is normally performed. The elastic storage memory unit for reception can be constituted by a memory means such as a FIFO or a two-port RAM in addition to the multi-stage registers. Next, the configuration and operation of the synchronization pattern insertion unit on the transmission side will be described with reference to FIGS. 9 and 10. FIG. FIG. 9 is a detailed block diagram of the synchronization pattern insertion unit, and FIG. 10 is an operation timing diagram of the synchronization pattern insertion unit. The synchronization pattern insertion unit performs byte synchronization and cell synchronization by detecting a synchronization pattern in the byte synchronization unit and the cell synchronization unit on the receiving side in the ATM cell data of the parallel signal of 20 MHz input from the data input (DI). For this purpose, an arbitrary fixed-length synchronization pattern necessary for this purpose is inserted into the synchronization pattern insertion position. In this embodiment, the insertion position of the synchronization pattern is the sixth bit from the first bit of the ATM cell. Based on the frame input (FI) and the clock input (CI), the internal counter (54 base) of the timing generator 601 is used. And a decoder, and selects a synchronization pattern to be inserted into the ATM cell through the selector 602, synchronizes the clock with the clock input (CI) with the output register 603, and outputs it to the data output (DO) (see FIG. 10). ). The synchronization pattern insertion unit is, like the byte synchronization unit on the receiving side, compatible with a method of inserting a synchronization pattern (HEC) generated by a header check sequence. ,
The information section is composed of a scramble circuit or the like that scrubbles with a specific generator polynomial. Next, the configuration and operation of the transmission elastic store memory unit will be described with reference to FIGS. 11, 12, and 13. FIG. Eleventh
FIG. 12 is a detailed block diagram of the transmission elastic store memory unit, FIG. 12 is an operation timing diagram of the transmission elastic store memory unit, and FIG. 13 is a phase diagram of the transmission elastic store memory unit. FIG. 7 is an operation timing chart of a matching function. Transmitting elastic store memory unit, 20MH _z of the device-side transmission clock input signal (SCKIN)
Since the phase of 160MH _z transmission line side clock input signal (CKIN) a read clock input of the transmission elastic store memory portion 20MH _z created by dividing the parallel serial conversion unit based on the (RCI) is offset with If, when externally input clock signal of the clock signal and 20MH _z of 160MH _z on CMOS-LSI, a variation in the propagation delay of the internal gate element for phase shift occurs, in order to absorb their phase shift. FIG. 11 is a block diagram of a transmission elastic store memory unit when a transfer data temporary storage register is configured in four stages. The write side inputs the ATM cells input from the write data input (WDI) to the D terminals of the transfer data temporary storage registers 701 to 704, and according to the outputs (QA to QD) of the write enable counter 705 of the four-stage ring counter, Write sequentially in synchronization with the write clock input (WCI). On the other hand, the read side selects the output of the transfer data temporary storage registers 701 to 704 according to the output (Q) of the read selection counter 707 of the four-stage ring counter and selects the output of the selector 706.
And fetches it into the output register 711 in synchronization with the read clock input (RCI) and outputs it to the read data output (RDO) (see FIG. 12). The phase adjustment between the write side and the read side adjusts the timing between the write side and the read side by comparing the output state of the write enable counter 705 with the output state of the read select counter 707 because there is no read frame signal on the transmission line side. This is performed by a phase matching function. When the output of the write enable counter 705 and the output of the read selection counter 707 match in the state QD,
The output is initialized when the output of the gate 709 becomes H, the output Q of the JK flip-flop 708 becomes H, and the reset (R) of the read selection counter 707 becomes H. Thereafter, the initialization is released when the output of the write counter 705 becomes the state QB, that is, when the output Q of the JK flip-flop 708 becomes L and the reset (R) of the read selection counter 707 becomes L. By this means, it is possible to adjust the phase by shifting the timing on the writing side and the timing on the reading side by 2 bytes (see FIG. 13). Flip-flop 710
It is used to synchronize the outputs (QB, QD) of the write enable counter 705 with the read clock input (RCI). The above is the embodiment of the transmission circuit in the transmission path of the ATM cell within the communication path device of the ATM exchange and between the devices.

【The invention's effect】

According to the present invention, in the transmission of ATM cells in a device of a communication path device in an ATM exchange and between devices, by transmitting ATM cells as serial signals, it is possible to minimize the number of wirings on a transmission path. As a result, the exchange capacity of about several tens of lines can be configured on one board, and there is an effect that the size of the apparatus can be easily reduced. In addition, since the transmission circuit is unified with a digital circuit and integrated into a single chip with low power consumption CMOS elements, a transmission circuit with low power consumption can be made. This has the effect of reducing the power consumption of the device and reducing the size of the transmission circuit. . In addition, since the transmission circuit is formed into one chip for each line, it can be easily used by different devices, so that there is an effect of sharing the configuration of the transmission path between the devices. Further, by providing an elastic store memory function for transmission and reception in the transmission circuit, it is possible to absorb a phase shift between the transmission line side and the device side, so that there is an effect that data transfer can be performed reliably. In addition, a control signal is added to the vacant area of the additional bytes of the ATM cell on the transmitting side and transferred, and this is extracted on the receiving side, so that the control signal between devices can be added without adding a new wiring. There is an effect that can be delivered.

[Brief description of the drawings]

FIG. 1 is a functional block diagram of one embodiment of the present invention, FIG. 2 is a detailed block diagram of a byte synchronization unit in FIG. 1, and FIG.
FIG. 4 is a detailed block diagram of the cell synchronization unit in FIG. 1, FIG. 5 is an operation timing diagram in FIG.
6 is an explanatory diagram of the cell synchronization control of FIG. 4, FIG. 7 is a detailed block diagram of the receiving elastic store memory unit of FIG. 1, FIG. 8 is an operation timing diagram of FIG. FIG. 10 is a detailed block diagram of the synchronization pattern insertion unit of FIG. 1, FIG. 10 is an operation timing diagram of FIG. 9, FIG. 11 is a detailed block diagram of the transmission elastic store memory unit of FIG.
FIG. 11 is an operation timing diagram of FIG. 11, FIG. 13 is an operation timing diagram of the phase matching function of FIG. 11, FIG. 14 is a transmission form diagram of a transmission circuit, and FIG. 15 is a functional block diagram of a conventional example. . DESCRIPTION OF SYMBOLS 1... Bit phase synchronization section, 2... Serial-parallel conversion section, 3... Byte synchronization section, 4... Cell synchronization section, 5. Stick store memory unit, 7: Synchronous pattern insertion unit, 8: Elastic store memory unit for reception, 9 ...
... Parallel-serial converter.

Continuation of front page (72) Inventor Shinobu Gobara 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Totsuka Plant of Hitachi, Ltd. (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 12/28 H04L 12 / 56

Claims (9)

(57) [Claims] 1. A transmission circuit for transmitting ATM cells in a transmission path between communication path devices in an ATM exchange at high speed without transmitting a clock signal and a frame synchronization signal in parallel. A synchronization pattern insertion unit that adds an arbitrary fixed-length synchronization pattern detected by a synchronization circuit on the reception side to the ATM cell of the parallel signal processed by the device, and a transmission error that absorbs a phase shift between the device side and the transmission line side. It has a stick store memory unit and a parallel-to-serial conversion unit that converts a parallel signal into a serial signal and outputs the serial signal to the transmission line.The receiving side converts the ATM cells of the serial signal input from the transmission line into clocks of the same frequency with different phases. A bit phase synchronization unit for correctly capturing data with signals, a serial-parallel conversion unit for converting serial signals into parallel signals, and fixed-length synchronization inserted on the transmission side A byte synchronization unit that adjusts the byte start position of the ATM cell by detecting the turn from the ATM cell, a cell synchronization unit that adjusts the start position of the ATM cell, and a reception unit that absorbs the phase shift between the transmission line side and the device side A transmission circuit comprising: an elastic store memory unit. 2. The transmission circuit according to claim 1, wherein the synchronization pattern insertion section on the transmitting side has a function of inserting a synchronization pattern generated by a header check sequence and a function of scrambling data of the ATM cell by a specific generation polynomial. The byte synchronization unit of the reception unit has a function of detecting the synchronization pattern generated by the header check sequence from the ATM cell, a data error correction function of the header of the ATM cell, and a scrambled by a specific generation polynomial. ATMs
A transmission circuit having a function of descrambling cell data. 3. The transmission circuit according to claim 1, wherein the transmission elastic store memory unit and the reception elastic store memory unit are configured by multi-stage flip-flops. 4. A transmission circuit in an ATM exchange for transmitting an ATM cell at high speed without transmitting a clock signal and a frame synchronization signal in parallel, wherein a synchronization pattern for adding a fixed-length synchronization pattern to the ATM cell of a parallel signal. The insertion unit and the ATM cell of the parallel signal output from the synchronization pattern insertion unit are written in synchronization with the clock signal on the device side, read out in synchronization with the clock signal on the transmission line side, and the phase shift between the device side and the transmission line side is corrected. A transmission elastic storage memory unit to be absorbed, and a parallel-serial conversion unit that converts the ATM cell of the parallel signal read from the transmission elastic store memory into the ATM cell of the serial signal and outputs the ATM cell to the transmission path A transmission circuit characterized by the above. 5. The transmission circuit according to claim 4, wherein the synchronization pattern insertion section has a function of inserting a synchronization pattern generated by a header check sequence and a function of scrambling data of an ATM cell with a specific generation polynomial. A transmission circuit, comprising: 6. The transmission circuit according to claim 4, wherein said transmission elastic store memory section is constituted by multi-stage flip-flops. 7. A transmission circuit in an ATM exchange for transmitting an ATM cell at high speed without transmitting a clock signal and a frame synchronization signal at the same time, wherein an ATM cell of a serial signal input from the transmission line is transmitted to the transmission line side. A bit phase synchronizing unit to be captured by a clock signal
ATM of serial signal captured by the above bit phase synchronization unit
A serial-to-parallel conversion unit that converts a cell into a parallel signal ATM cell, and a fixed-length synchronization pattern from among the parallel signal ATM cells output from the serial-parallel conversion unit detects the byte start position of the ATM cell. A byte synchronizing unit that adjusts the start position of the ATM cell, and an ATM cell of a parallel signal output from the cell synchronizing unit is written in synchronization with the clock signal on the transmission line side, and is written into the clock signal on the device side. A transmission circuit comprising: a reception elastic store memory unit that reads out in synchronization and absorbs a phase shift between a transmission path side and a device side. 8. The transmission circuit according to claim 7, wherein said byte synchronization unit has a function of detecting a synchronization pattern generated by a header check sequence from an ATM cell, a function of correcting a data error of a header portion of the ATM cell, A transmission circuit having a function of descrambling data of an ATM cell scrambled by a specific generator polynomial. 9. The transmission circuit according to claim 7, wherein said reception elastic store memory section is constituted by multi-stage flip-flops.