JP3069724U - PLL circuit and its peripheral circuit - Google Patents

Abstract

(57) [Problem] To provide a PLL circuit capable of stably holding a lock voltage even when a hold time is long. An A / D converter that converts a lock voltage into digital data in a PLL circuit that holds the voltage when the voltage is locked by controlling the oscillation frequency of VC0, and digital data of the A / D converter And a D / A converter for latching and converting to an analog voltage.

Description

[Detailed description of the invention]

[0001]

[Technical field to which the invention belongs]

 The present invention relates to a PLL circuit that can stably hold a lock voltage for a long time.

[0002]

[Prior art]

 The configuration and operation of a conventional PLL circuit example will be described with reference to FIG. As shown in FIG. 6, one example of a conventional PLL circuit includes a VCO 10, an adder 20, a ramp generator 21, a switch S2, a sample and hold circuit 100, a loop filter 110, and a frequency divider 130. , A comparator 140 and an oscillator 90.

The VCO 10 is a voltage-controlled broadband oscillator, and changes the oscillation frequency using the added voltage added by the adder 20 as a control voltage.

The adder 20 adds and outputs the output voltage of the sample and hold circuit 100 and the output voltage of the ramp generator 21.

The ramp generator 21 generates a sawtooth ramp wave whose voltage increases linearly, and causes the VCO 10 to perform a sweep oscillation.

The oscillator 90 generates a frequency-stabilized reference frequency.

The frequency divider 130 sets the desired frequency division ratio to be programmable, divides the frequency, and outputs the frequency. For example, in order to set the reference frequency of the oscillator 90 to 10 MHz and lock at the oscillation frequency of the VCO 10 of 100 MHz, the frequency division ratio of the frequency divider 130 is 1/10.

The comparator 140 compares the phase of the frequency obtained by dividing the oscillation frequency of the VCO 10 by 1 / N with the frequency divider 130 and the reference oscillation frequency of the oscillator 90, and outputs an error signal obtained by the comparison. .

The loop filter 110 outputs a DC voltage by averaging the error signal of the comparator 140.

The sample-and-hold circuit 100 forms a feedback loop in a closed sample state by turning on the switch S 1, and the frequency division frequency of the frequency divider 130 matches the reference frequency of the oscillator 90 in the comparator 140. The capacitor C1 is charged with the lock voltage at this time, and the switch S1 is turned off and held in the open state.

Next, an outline of the configuration and operation will be described using a specific example in which the PLL circuit shown in FIG. 6 is used as a local oscillator of a spectrum analyzer.

For example, as shown in FIG. 5, a fundamental block of the spectrum analyzer includes a ramp wave generator 21, a VCO 10, a mixer 26, an IF filter 27, a detector 28, and a display unit 29. Make up. However, parts other than the VCO 10 and the ramp generator 21 of the PLL circuit shown in FIG. 6 are omitted for simplification of the drawing.

The input RF signal is mixed with the local frequency of the VCO 10 by the mixer 26 and converted into a sum and difference IF frequency. As the IF frequency, the sum or difference frequency is selected by the IF filter 27, detected by the detector 28, and becomes the X-axis signal level of the display unit 29.

On the other hand, the output voltage of the ramp generator 21 becomes the local frequency of the VCO 10 and the frequency span of the display unit 29 on the Y axis.

Next, the operation of the spectrum analyzer will be described using specific numerical examples. For example, as shown in FIG. 4, it is assumed that the center frequency is Fc = 100 MHz, the span is 200 kHz, and a 100 MHz RF signal is displayed in the center of the screen. At this time, the frequency at the left end of the screen is 99.9 MHz, and the frequency at the right end is 100.1 MHz.

In the PLL circuit shown in FIG. 6, the oscillation frequency of the VCO 10 is locked at a frequency where the frequency at the left end of the screen is 99.9 MHz, and the sample voltage at that time is used as the lock voltage and the sample / hold circuit 100 And the switch S1 is OFF. Then, the switch S2 is turned on, the ramp signal is added from the ramp generator 21 with the hold voltage as a starting point, and the VCO 10 sweeps 200 kHz and oscillates free.

Here, as shown in FIG. 3, the ramp output of the ramp generator 21 is defined as a sweep time Ts and a blanking time Tb.

For example, if the sweep time Ts = 100 ms and the blanking time Tb = 80 ms, the PLL circuit locks at the blanking time Tb of 80 ms, and the VCO 10 sweeps with the sweep frequency Ts100 ms starting from the lock frequency. Free oscillation. Then, the PLL circuit is locked again at the blanking time Tb of 80 ms, and the VCO 10 repeatedly oscillates free at the sweep time Ts of 100 ms starting from the frequency.

Meanwhile, when it is desired to narrow the measurement resolution (RBW) and perform measurement with high resolution as in the case of EMC measurement, it is necessary to increase the sweep time Ts in order to prevent an error from occurring in the signal level. For example, if the sweep time Ts is increased to 100 s, the PLL circuit is locked at the blanking time Tb of 80 ms, and the VCO 10 sweeps 100 s by free oscillation starting from the lock frequency.

However, the free oscillation of the VCO 10 for as long as 100 s causes the hold voltage of the capacitor C1 of the sample-and-hold circuit 100 to fluctuate under the influence of leak current and external noise due to the long hold time. . Therefore, as shown in FIG. 4, the RF signal of the signal under measurement is displayed with a deviation of Δf from the center of the display screen, resulting in measurement error.

Therefore, in the sample and hold circuit 100, a component having a small leak is selected, or a guard ring is provided around the capacitor C1 for holding the lock voltage so that the sample and hold circuit 100 is not affected by the power supply line pattern. I have. However, conventional countermeasures against leakage current and external noise were not sufficient when the sweep time was long.

The above problem also occurs when a PLL circuit is used as a signal source.

[0023]

[Problems to be solved by the invention]

 As described above, when a PLL circuit that holds the lock voltage of the VCO with a capacitor is used, if the hold time is long, a measurement error occurs due to the influence of leak current, external noise, and the like. There was a problem. Accordingly, the present invention has been made in view of such a problem, and an object of the present invention is to provide a PLL circuit that can stably hold a lock voltage even when a hold time is long.

[0024]

[Means for Solving the Problems]

 That is, the first of the present invention made to achieve the above object is to control the oscillation frequency of VC0 to hold the voltage at the time of locking by a PLL circuit, and to latch the lock voltage of VCO as digital data. And hold.

In order to achieve the above object, a second aspect of the present invention is to provide a PLL circuit for controlling the oscillation frequency of VC0 to hold the voltage at the time of locking. A PLL circuit is characterized by comprising: an A / D converter for converting; and a D / A converter for latching digital data of the A / D converter and converting the data into an analog voltage.

A third aspect of the present invention, which has been made to achieve the above object, is that the oscillation output of the VCO of the PLL circuit is mixed by a mixer and used as a local frequency for converting to an IF frequency. Of the PLL circuit described in (1).

[0027]

[Embodiment of the invention]

 Embodiments of the present invention will be described in the following examples.

[0028]

【Example】

 First Embodiment The configuration and operation of a PLL circuit according to a first embodiment of the present invention will be described with reference to FIG. As shown in FIG. 1, the PLL circuit of the present invention includes a VCO 10, an adder 20, a ramp generator 21, a loop filter 110, a frequency divider 130, a comparator 140, an oscillator 90, It comprises an A / D converter 22, a D / A converter 23, a control circuit 24, and switches S2, S3, S4. That is, the sample / hold circuit 100 is deleted from the conventional configuration, and the A / D converter 22, the D / A converter 23, the control circuit 24, and the switches S3 and S4 are added.

Therefore, the operation of the VCO 10, the adder 20, the ramp generator 21, the loop filter 110, the frequency divider 130, the comparator 140, and the oscillator 90 will be described in the prior art. It is omitted here.

The A / D converter 22 is a converter which reads a voltage when the closed PLL circuit is locked by turning on the switch S3 by a control signal and converts the voltage into digital data.

The D / A converter 23 is a converter that receives digital data output from the A / D converter 22, latches the digital data with a control signal, and converts the digital data into an analog voltage.

The control circuit 24 controls the A / D converter 22, the D / A converter 23, and the switches S 2, S 3, and S 4 by a control signal supplied from a CPU or the like to control the operation of the PLL circuit. is there.

Next, the operation when the PLL circuit of the first embodiment is used as a local oscillator of a spectrum analyzer as shown in FIG. However, parts other than the VCO 10 and the ramp generator 21 of the PLL circuit are omitted for simplification of the drawing. Further, as shown in FIG. 4, it is assumed that the measurement conditions are set with the center frequency set to Fc = 100 MHz and the span set to 200 kHz, and the 100 MHz RF signal of the signal under measurement is displayed in the center of the screen.

(1) During the blanking time of the ramp generator 21, while the switches S2 and S4 are off, the switch S3 is turned on and the PLL circuit operates as a closed loop.

(2) The oscillation frequency of the VCO 10 is locked at a frequency where the frequency at the left end of the screen is 99.9 MHz, and the lock voltage V1 at that time is read by the A / D converter 22 using a control signal, and the digital data is read. And output.

(3) The digital data output of the A / D converter 22 is latched by the D / A converter 23 according to the control signal, and the analog voltage V2 is converted and output. Here, the resistance of the voltage control sensitivity is set to R3 = R6 and V1 = V2.

(4) After the lock voltage is latched by the D / A converter 23, the switch S3 is turned off and the switch S4 is turned on.

(5) Immediately after the switch S4 is turned on and V2 is applied to the adder 20, the switch S2 is turned on and the ramp signal from the ramp generator 21 is added starting from the hold voltage, The VCO 10 sweeps and oscillates free.

Therefore, in the spectrum analyzer using the PLL circuit of the first embodiment, the lock voltage of the VCO 10 is latched by the D / A converter 23 and stable even when the sweep time is lengthened. No measurement error due to fluctuation.

Second Embodiment Next, an example in which the PLL circuit of the present invention is used as a pretuned PLL circuit of a sampler PLL circuit will be described with reference to FIG.

It should be noted that as to the above-mentioned prior art, as already disclosed in a published patent application (Japanese Patent Laid-Open No. 9-219641) and already filed by the same inventor in Japanese Patent Application No. 11-5460, In the PLL circuit of the sampler system, the lock voltage of the VCO 10 is held by pre-tuning by a pre-tune PLL circuit in advance near the frequency to which the phase lock is applied.

First, an outline of the configuration and operation when the first PLL circuit is a sampler PLL circuit will be described. The sampler PLL circuit includes a VCO 10, an adder 20, a switch S5, a positive / negative electrode selection circuit 31, a loop filter 30, a frequency variable synthesizer 40, a comparator 50, a sampler 60, and a crystal oscillator 70. Make up.

Here, the VCO 10 and the adder 20 are blocks common to the pretuned PLL circuit, and the description is omitted.

The crystal oscillator 70 generates a frequency-stabilized reference frequency.

The sampler 60 mixes each frequency of the COM signal obtained by multiplying the oscillation frequency of the crystal oscillator 70 by M with the multiplier and the oscillation frequency of the VCO 10 by a mixer, and outputs an IF frequency.

The variable frequency synthesizer 40 generates a variable frequency-stabilized reference frequency.

The comparator 50 performs frequency comparison or phase comparison between the reference frequency of the frequency variable synthesizer 40 and the IF frequency of the sampler 60, and outputs an error signal.

The loop filter 30 averages the error signal of the comparator 50 and outputs a DC voltage.

The positive / negative selection circuit 31 selects a positive or negative polarity for the DC voltage averaged by the loop filter 30 to expand the variable range of the control voltage to both the positive electrode and the negative electrode.

Then, when the switch S5 is turned on, the sampler PLL circuit forms a feedback loop in the comparator 50 so that the reference frequency of the variable frequency synthesizer 40 and the IF frequency match, and locks.

However, in the sampler PLL circuit, it is not known whether the sampler PLL circuit is locked at a desired value of the multiple M of the sampler. Therefore, the oscillation frequency of the VCO 10 is locked in advance by a pretuned PLL circuit at a desired value of the multiplier M of the sampler.

The configuration and operation of the PLL circuit of the present invention used as a pretuned PLL circuit as the second PLL circuit have been described in the first embodiment and will not be described.

Next, the outline of the operation of the second embodiment will be described using specific numerical examples. For example, it is assumed that the VCO 10 is locked at the oscillation frequency f1 = 1882 MHz under the following conditions. Reference frequency f4 of oscillator 90 = 10 MHz Oscillation frequency f2 of crystal oscillator 70 = 100 MHz Oscillation frequency f3 of variable frequency synthesizer 40 = 50 to 100 MHz

F1 = M · f2 ± f3 (1) For example, an example for oscillating under the above conditions is represented by the following equation (2). 1882 MHz = 18 × 100 MHz + 82 MHz (2) On the other hand, the pretuned PLL circuit is locked in units of 10 MHz of the reference frequency. By latching the lock voltage in the D / A converter 23 as digital data, a stable operation can be performed without any loss of lock.

Therefore, by using the PLL circuit of the present invention as a pretuned PLL circuit, the PLL circuit operates stably.

Although the first PLL circuit has been described as a sampler type PLL circuit, the first PLL circuit can be similarly implemented by a general PLL circuit.

[0057]

[Effect of the invention]

 The present invention is implemented in the form described above, and has the following effects. That is, since the lock voltage of the PLL circuit of the present invention can be latched as digital data, it can be stably held for a long time without being affected by external noise or leak current. In addition, when the PLL circuit of the present invention is used as a local oscillator such as a spectrum analyzer, the lock voltage can be stably held even if the sweep time is long.

[Brief description of the drawings]

FIG. 1 is a block diagram of a PLL circuit according to a first embodiment of the present invention;

FIG. 2 is a block diagram of Embodiment 2 of the PLL circuit of the present invention.

FIG. 3 is a waveform diagram of a ramp wave.

FIG. 4 is a screen display diagram of a spectrum analyzer.

FIG. 5 is a block diagram of a spectrum analyzer.

FIG. 6 is a block diagram of a conventional PLL circuit.

[Explanation of symbols]

 Reference Signs List 10 VCO 20 Adder 21 Ramp generator 22 A / D converter 23 D / A converter 24 Control circuit 26 Mixer 27 IF filter 28 Detector 29 Display unit 30 Loop filter 31 Positive / negative electrode selection circuit 40 Frequency variable synthesizer 50 Comparator 60 Sampler 70 Crystal oscillator 90 Oscillator 100 Sample and hold circuit 110 Loop filter 130 Divider 140 Comparator

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[Procedure amendment]

[Submission date] February 9, 2000 (200.2.9)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Name of device

[Correction method] Change

[Correction contents]

[Name of device] PLL circuit and its peripheral circuit

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] Claims for utility model registration

[Correction method] Change

[Correction contents]

[Utility model registration claims]

Claims (3)

[Utility model registration claims] 1. A PLL circuit for voltage-controlling the oscillation frequency of VC0 to hold a locked voltage, wherein the PLL circuit latches and holds a lock voltage of a VCO as digital data. 2. An A / D converter for converting a lock voltage into digital data in a PLL circuit for controlling the oscillation frequency of VC0 to hold a voltage when the voltage is locked, And a D / A converter for latching data and converting the data to an analog voltage. 3. The PLL circuit according to claim 1, wherein the oscillation output of the VCO of the PLL circuit is mixed by a mixer to have a local frequency that is converted to an IF frequency.