JP3069127B2 - Speech synthesizer - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voice synthesizing apparatus for instructing an operating procedure to an operator using a voice in a conversational method of operating a machine, and more particularly to a voice synthesizing apparatus. The present invention relates to improvement of termination of utterance when interrupted.

[Prior Art] When operating an automated machine or the like by self-service having a speech synthesizer that sequentially describes the operation procedure of the machine by voice, it is not necessary for a person who is accustomed to the operation of the machine to give a voice explanation. Become. Therefore, depending on the machine,
A device that outputs voice guidance only when the next operation is not performed for a certain period of time is known. Therefore, when the operation is performed normally and continuously, the sound procedure is not output.

Further, there is also known an apparatus which outputs an explanation by voice only when an executed operation has an error. However, highly skilled users often know how to correct even when they make mistakes. In such a case, it is necessary to interrupt the voice guidance immediately when the user performs a correction operation even with the voice guidance output at the time of an incorrect operation, and shift to the next operation.

In addition, some users are unskilled but know the operation method to some extent. Even in the case of a user who has not completely mastered such operations, if it is not necessary to listen to the entire procedure, listen only to the cueing procedure and interrupt afterwards.
It is necessary to immediately shift to the next operation.

2. Description of the Related Art Conventionally, Japanese Patent Application Laid-Open No. 63-49898 discloses a speech synthesizer capable of producing a sentence such as a machine operation procedure.

The speech synthesizing apparatus according to the present invention inserts two or more end codes into the divided portions of the speech coded data, and when a speech end signal is input at an arbitrary position, in synchronization with the end signal. A control circuit for terminating the output of the sound is provided. According to the present invention, when an utterance end signal is input after the utterance start signal, an end code which appears after the control circuit receives the utterance end signal among the end codes pre-inserted in the middle of the speech coded data. By controlling so that the voice ends, the output of the voice naturally ends at the position of the desired end code.

[Problems to be Solved by the Invention] According to the apparatus of the invention described above, the end point is preset in the storage circuit, and in order to naturally turn off the audio output, the end code in the storage circuit is detected. Do. Therefore, the detection position of the end signal is limited between the storage circuit and the arithmetic circuit.

In addition, the machine does not determine whether or not the voice is actually uttered, since the end is not determined by detecting the actually uttered voice data.

Also, the end point cannot be ended at an arbitrary point only by selecting a predetermined point.

Therefore, a ROM containing audio data in which a plurality of end codes are inserted in advance is required. Further, in order to carry out the above-described known invention, the voice synthesis control unit always reads the contents of the data ROM, determines whether the read data is the end code, and even if the read code is the end code, If the utterance end signal has not been input, control is required to continue speech synthesis without ending. However, commercially available general-purpose speech synthesis controllers do not have such a function. In addition, some commercially available LSIs have a built-in data ROM.When these general-purpose LSIs or general-purpose speech synthesis controllers are used, the CPU only uses the BUSY signal to output audio signals. The above-mentioned known technique cannot be implemented using these general-purpose off-the-shelf products because of the configuration that cannot be known. Therefore, there is a method of forcibly stopping the sound in the middle of the output of the sound in response to the reset signal. However, in this case, the sound is interrupted unnaturally.

[Means for Solving the Problems] As shown in FIG. 1, the audio signal 17 is fed back to the CPU via the audio detection circuit 13 of the feedback circuits 11, 12, and 18, and the CPU returns the feedback signal. , A silent section having a length equal to or longer than a predetermined period is detected, and the output of the sound is stopped at that position, whereby the output of the sound is naturally interrupted at an arbitrary point desired by the operator.

[Operation] When the CPU 1 of this block diagram writes a sentence for which speech is desired to be output to a specified register of the speech synthesis controller 5 in a designated sentence code, the controller outputs the sentence selected by the code as speech data. Read out from the memory 6, convert the digital signal into an analog audio signal 17, and output it. The analog audio signal 17 output from the controller 5 is output from the speaker 10 via the filter 8 and the amplifier 9. The output of the filter 8 or the output of the amplifier 9 detects the presence or absence of the amplitude of the audio waveform in the audio detection circuit 13 having a high input impedance that does not affect the audio waveform, and replaces it with digital data. Notify CPU1 as back signal 15. CP
U1 detects the absence of amplitude in the audio output by detecting both the BUSY signal 7 and the feedback signal 15 of the audio detection circuit 13, and detects a period or a terminator or an end according to the length of each silence period. Identify silent sections other than.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram for explaining an embodiment of a speech synthesizer according to the present invention. In FIG. 1, reference numeral 1 denotes a CPU, and reference numerals 2 and 3 denote a ROM and an R for storing a speech synthesis program.
In the AM, the CPU 1 is connected via a system bus 4 consisting of an address bus, a data bus, and various control signals.
Is controlled by 5 indicates a speech synthesis controller,
Numeral 6 stores various messages in which voice is parameterized in a voice data memory.

The speech synthesis controller 5 includes a selector, a decoder, and a DA converter (not shown).

A selector (not shown) built in the voice synthesis controller 5 selects and inputs voice data corresponding to the signal from an address designated by the program, and outputs a BUSY signal 7 to the CPU 1.

A decoder (not shown) built in the voice synthesis controller 5 decodes the read voice data, and then converts the data decoded by the DA converter (not shown) built in the controller 5 into an analog voice signal.
Convert to 17.

The filter 8 performs audio band conversion audible to humans, and the amplifier 9 amplifies and outputs as audio from the speaker 10. 11 shows an audio feedback circuit according to the present invention. Reference numeral 13 denotes a voice detection circuit, the output of which is a feedback signal 15
Is input to CPU1.

2 and 3 are diagrams showing the timing of each signal of the speech synthesizer of FIG. 1, FIG. 2 is a timing chart when no utterance end signal is input, and FIG. 3 is utterance. This shows the timing after the end signal is input.

 FIG. 4 shows an embodiment of the voice detection circuit 13.

In FIG. 4, in is the audio waveform input from the audio feedback circuit 11, 12 or 18 of (d) and (d ') on the timing charts shown in FIGS. f), feedback signal of (f ')
It is 15.

The case where the feedback circuit 12 is branched from between the filter 8 and the amplifier 9 is shown.

The feedback circuit 18 is a voice synthesis controller 5
And a case where the light is branched from the filter 8 and the filter 8. In this way, branch points are provided at a plurality of locations 11, 12, and 18, and these branch points are switched by a switch (not shown).

From the output of the filter 8 or the output of the amplifier 9 via the feedback circuit 11, 12 or 18, the presence or absence of the amplitude of the audio waveform in the audio detection circuit 13 having a high input impedance that does not affect the audio waveform Is detected, the presence or absence of the amplitude is converted into digital data, and the result is notified to the CPU 1 as a feedback signal 15.

By receiving both the BUSY signal 7 output from the voice synthesis controller 5 and the feedback signal 15 output from the voice detection circuit 13, the CPU 1 detects a silent section as a segment of a voice portion. Each silent section of the speech parameter of the text contained in the speech data memory 6 is identified as a reading point or a punctuation mark by the length of the silent section of the feedback signal 15 output by the speech detecting circuit 13.

When the utterance end signal 14 is received by the CPU 1 during the speech synthesis output, the CPU 1 monitors the feedback signal 15 output from the sound detection circuit 13 and reads the reading point or A silent section such as a period is detected, and the sound output is naturally terminated at the corresponding silent section. Therefore, audio output does not stop in the middle of a word. Further, even when a malfunction occurs such that sound is not output from the speaker 10, the failure point can be easily found by monitoring the feedback signal 15. That is, according to the present invention, the CPU 1 can sense data such as the time and punctuation of an audio signal output from the audio synthesis controller 5. Therefore, in the function diagnosis mode of the machine main body (not shown), a certain sentence code number is designated and a sound is output, and the continuous sounding time of the sentence of the sentence of the code number, the data of the position of the punctuation mark, and the feed By comparing with the feedback signal 15 input via the back circuit 11, 12, or 18, it is possible to know up to which block the sound is output.

The above control will be described with reference to the timing charts of FIGS.

FIG. 2 shows the timing when there is no utterance end signal 14.

(A) shows the timing at which the code number of a sentence to be output as a voice is sent from the CPU 1 to the voice synthesis controller 5 via the system bus 4.

The address of the audio data memory 6 is calculated from the sentence code number, and the desired encoded audio data is read. This sentence code number corresponds to ROM2, RA in Fig. 1.
The program is appropriately selected and designated according to various situations by a program stored in M3.

(B) shows the timing at which the CPU 1 selects the speech synthesis controller 5.

(C) shows the speech synthesis controller 5 from the CPU 1 shown in (a).
4 shows the timing at which the sentence code number transmitted via the system bus 4 is written into a register in the speech synthesis controller 5.

(D) is a speech waveform output from the speech synthesis controller 5, and a section having no waveform indicates a silent section.

(E) shows the timing of the BUSY signal 7 indicating that the voice synthesis output is being returned from the voice synthesis controller 5 to the CPU 1.

(F) shows the timing of the feedback signal 15 returned from the voice detection circuit 13 to the CPU 1, and is synchronized with the utterance waveform of (d).

FIG. 3 shows the timing when there is an utterance end signal.

(D ') shows an example in which a speech end signal is input in the middle of the speech waveform output from the speech synthesis controller 5 shown in (d) of FIG. 2 and the speech output is interrupted in a silent section to be detected next. Is shown.

(E ') is a BUSY signal 7 returned from the voice synthesis controller 5 to the CPU 1 and indicating that voice synthesis is being output.
Indicates the timing of interruption in the silent section to be detected next.

(F ') shows the timing of the feedback signal 15 returned from the voice detection circuit 13 to the CPU 1, and the CPU 1 detects a silent section in synchronization with (d').

 (G) shows the timing of the utterance end signal 14.

(H) shows a reset signal 16 for interrupting speech synthesis in response to the utterance end signal 14.

[Effects] As described above, even if a commercially available inexpensive general-purpose speech synthesis controller is added to the speech synthesizer by adding the speech detection circuit according to the present invention, the controller itself or the content of the speech ROM can be changed. Without addition, the audio signal does not end at an unnatural place such as in the middle of a word. It is possible to stop at a good punctuation point such as a punctuation point or a terminating point of a sentence, and as a result, it is possible to improve the use efficiency of the machine.

Further, even if a mechanical failure occurs in which no sound is output from the speaker, the failure location can be detected only by the voice synthesizer without using any special inspection equipment.

[Brief description of the drawings]

FIG. 1 is a block diagram of a voice synthesizing apparatus showing an embodiment of the invention, FIG. 2 and FIG. 3 are timing charts of the apparatus of FIG. 1, and FIG. 4 shows an example of a voice detecting circuit. In the figure, 1 is a CPU, 2 is a program ROM, 3 is a program RA
M, 4 is a system bus, 5 is a speech synthesis controller, 6
Is the audio data memory, 7 is the BUSY signal, 8 is the filter,
9 is an amplifier, 10 is a speaker, 11, 12, and 18 are feedback circuits, 13 is a voice detection circuit, 14 is an utterance end signal, 15 is a feedback signal output from the voice detection circuit 13, and 16 is voice synthesis. A reset signal 17 for interruption is an audio signal.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Masashi Utsumi 1-1-10 Koiso, Oiso-cho, Naka-gun, Kanagawa Prefecture NRC Japan, Ltd. Oiso Development and Manufacturing Division (56) References JP-A-58- JP-A-63-188198 (JP, A) JP-A-63-65498 (JP, A) JP-B-59-50077 (JP, B2) JP-B-61-8703 (JP, B2) (58) Field surveyed (Int.Cl. ⁷ , DB name) G10L 11/00-13/08 G10L 19/00-21/06 G06F 3/16 330

Claims (1)

(57) [Claims] An input circuit for inputting a speech start signal, a sentence code, and a speech end signal from outside, a storage circuit for storing speech encoded data, and a speech from speech encoded data based on the inputted sentence code. A voice synthesis controller that outputs a voice signal obtained by synthesizing and converting the voice signal into an analog signal, a speaker that outputs the voice signal as voice, and a CPU that controls the input circuit and the voice synthesis controller. A feeder for feeding back the audio signal to the CPU between the controller and the speaker;
A feedback circuit, wherein the feedback circuit includes a voice detection circuit that outputs a digital signal obtained by converting the feedback voice signal into two digital values of a voice portion and a silent portion; and the CPU includes the feedback circuit. Based on the digital signal received from the audio detection circuit of the circuit, a silent section of the audio signal having a length equal to or longer than a predetermined period is detected, and an audio output is generated when the silent section is detected after receiving the utterance end signal. A voice synthesizing device, wherein the voice synthesizing controller is controlled so as to end.