JP3067794U - Bus interface device for semiconductor test equipment - Google Patents

Abstract

(57) Abstract: A bus interface system of a semiconductor test apparatus that performs a write / read operation under a complicated selection condition with a plurality of LSIs is provided. A control bus I / F unit and a plurality of n LSIs are interfaced in a serial bus form, and each time a write / read operation with the LSI is performed, a bus interface operation selection information and CS information are transferred to a 1-bit serial bus. Are sent in a predetermined order to the LSI side, and a plurality of n LSIs are provided with a corresponding serial bus control unit in the LSI.
The I serial bus control unit receives a predetermined plurality of bits of an ID code at an input terminal of the LSI, and obtains LS from the n-bit CS information serially received from the serial bus and the ID code.
A bus interface system in which I detects whether to enable the chip, and when asserted, the LSI performs a predetermined write / read operation based on bus interface operation selection information serially received from the serial bus.

Description

[Detailed description of the invention]

[0001]

[Technical field to which the invention belongs]

 This invention relates to a bus interface system of a semiconductor test device. In particular, when performing bus interface operations, a large amount of selection information is supplied to an LSI, and a write / read operation between the control CPU and a plurality of LSIs is performed based on the selection information. The present invention relates to a bus interface system of a semiconductor test apparatus capable of greatly reducing the number of signals to be transmitted.

[0002]

[Prior art]

 The prior art will be described below with reference to FIGS. First, the conceptual configuration of the semiconductor test apparatus shown in FIG. 5 will be briefly described. The main components include a pattern generator PG, a waveform shaper FC, a driver DR, a comparator CP, a logical comparator DC, a timing generator TG, a timing generation controller TGC, and the like. As is well known, each unit has hundreds to thousands of tester channels, and each channel is configured with the same functional circuit. For this reason, a predetermined number of the same dedicated LSI corresponding to the number of channels are mounted on the board of each unit and used. One dedicated LSI usually has several to several tens of channels of the same circuit, depending on the circuit scale.

[0005] Furthermore, the dedicated LSI includes many variable setting elements, for example, a large number of registers, register groups, and memories for storing test conditions and the like so that the operation can be controlled under various test conditions from a test program. I have. This element varies depending on the unit, but for example, the timing of the leading edge / trailing edge of the waveform applied to the device under test (DUT), the waveform mode, the variable delay element for adjusting the timing, the channel assignment condition, and the operation Modes, high / low voltage level conditions applied to the DUT, reading measurement data, etc.

Meanwhile, among the test modes of the DUT, there is a test mode in which test conditions such as a voltage and a waveform applied to the DUT are changed as needed during the execution of the test. The change of the test condition is performed via the tester bus TBUS, and during this change period, the device test is suspended. Here, since the tester bus TBUS is a bus connection configuration in which the units are connected in series with a cable of several meters, one access time takes several μ seconds. As a result, when a large number of accesses of several thousand to several hundred thousand times are performed, the throughput of the device test is reduced. For this reason, when the same data is set to a plurality of designated channels, a function that allows a single tester bus instruction to write data to a single or a plurality of channels in the LSI or to a plurality of LSIs at once. It has. For this purpose, as shown in FIG. 4, each LSI has a large number of input terminals for receiving bus interface operation selection information 130s, and complicated write / read operations are performed based on the selection conditions of the input terminals.

Next, a description will be given of a conventional main part configuration diagram of FIG. 4 in which a bus interface is performed between the LSI and the control bus I / F section by using a number of parallel control signals. 4 includes a control CPU, a tester bus TBUS, a control bus I / F unit 100, a parallel bus, and LSIs 301 to 30n. Here, although the example in which one control bus I / F unit 100 is provided in the unit, the control bus I / F unit 100 may be provided for each board. Here, the number of LSIs that interface with the tester bus TBUS varies depending on the units and the scale of integration of the dedicated LSIs, but the following description will be made on the assumption that n = 10, for example. It is assumed that all the LSIs are the same LSI. The control CPU is a device that can directly control the tester bus TBUS such as the test processors TP and PG. The tester bus TBUS is a dedicated bus interface used in a semiconductor test apparatus, and includes, for example, a time division bus for transmitting a 32-bit address and data in a time-division manner, a write / read control signal, and others. And a handshake signal.

The control bus I / F unit 100 is a bus interface that mediates between the control CPU and a plurality of LSIs, and includes a TBUS I / F unit 110, a selection register 130, and an internal bus I / F unit 120. . The TBUS I / F section 110 is for relaying between the control CPU and the internal bus I / F section 120, and controls writing / reading of setting data from the control CPU to the selection register 130.

The selection register 130 includes a plurality of mode registers having a predetermined bit width for selecting an internal operation condition of the LSI, and a 10-bit width enable register 132 for enabling a write / read operation for each LSI. is there. One mode register is a selection signal (bus interface operation selection information 130s) to be commonly supplied to each LSI. For example, in an LSI used for a TG / FC unit, a simultaneous edge write register Sil and an edge selection register EDGEsel are used. , A channel selection register CHsel, a child selection register CHILDsel, a bank selection register BANKsel, an LSI internal register selection register REGsel, and the like. The number S of signals in the bus interface operation selection information 130s may vary depending on the unit, but it is assumed that S = 20, for example. The other enable register 132 is a chip select information (CS information) CHIPsel having a 10-bit width. The CS signal 132s, which is an output signal, is a chip enable signal line individually connected to each of the ten LSIs. As a result, a plurality of LSIs can simultaneously perform the write operation by specifying the enable. If 64 LSIs are mounted, 64 chip enable signal lines are required.

The data bus line 120 s interfaced by the internal bus I / F section 120 is connected in parallel to each LSI, and includes, for example, a 16-bit data bus DATA, a write control signal WR, a read control signal RD, Other. There is no line corresponding to the address signal, and instead, the bus interface operation selection information 130s and the CS signal 132s are supplied.

On the other hand, each LSI includes an internal bus control unit 330. The input / output signal lines of the bus control unit 330 in the LSI are the above-described 20 bus interface operation selection information 130s, one of the CS signals 132s, and 18 or more data bus lines 120s. The total number of these is more than 39. The LSI performs a bus interface under the above-described complicated selection conditions using the large number of signal lines, and controls writing / reading with a large number of registers and memories provided therein. However, when the number of signals for bus interface is large, an LSI package having a large number of terminals is used, so that the package becomes larger. In addition, the board requires a wide area for wiring patterns to be connected to each LSI, which causes a problem that the mounting density on the board is reduced.

On the other hand, the control bus I / F section 100 requires a total of 49 or more terminals, and the number of LSIs varies depending on the system configuration, and the number of tester channels varies. The CS signal 132s also increases and decreases. The number of bus interface operation selection information 130s differs depending on the unit.

[0011]

[Problems to be solved by the invention]

 As described above, the conventional bus interface method has a disadvantage that the number of signal lines related to the bus interface increases in an LSI that needs to use a large number of signal lines to perform a bus interface under complicated selection conditions. . As a result, the package becomes larger, the mounting area on the board becomes larger, and a region for arranging a large number of wiring patterns is also required. This limits the number of LSIs to be mounted and is undesirable in terms of cost. . From these viewpoints, the prior art has practical difficulties. Therefore, a problem to be solved by the present invention is to supply a large number of selection information to an LSI, and to perform a write / read operation between the control CPU and a plurality of LSIs under complicated selection conditions based on the selection information. It is an object of the present invention to provide a bus interface system of a semiconductor test device which can reduce the number of signals connected to an LSI in the bus interface system.

[0012]

[Means for Solving the Problems]

 First, in order to solve the above-mentioned problem, a control bus I / F unit 100 is provided at an input / output unit of a unit or a board, and the control bus I / F unit 100 includes a predetermined number n of a plurality of control buses provided in a board. A predetermined interface is provided between the LSIs 301 to 30n and the control CPU, and a plurality of internal registers REG are provided therein. The internal registers REG are preset by the control CPU, and are connected to at least a plurality of n LSIs 301 to 30n. This is the selection information used at the time of the write / read operation, and is composed of bus interface operation selection information 130s and chip select information (CS information) CHIPsel. The n-bit CS information CHIPsel is a single or a plurality of specified LSIs. This signal enables (asserts) the write / read operation at the same time as the target. The bus interface operation selection information 130s is a selection signal commonly supplied to each LSI. In the bus interface system of the semiconductor test apparatus having the above-described configuration, the control bus I / F unit 100 and the plurality of n LSIs 301 To 30n are interfaced in a 1-bit serial bus form, and the above-mentioned selection information (bus interface operation selection information 130s and CS information CH IPsel) is predetermined on a 1-bit serial bus 150bus every time a write / read operation with the LSI is performed. A plurality of n LSIs 301 to 30n are provided with a corresponding serial bus control unit 310c in the LSI, and the serial bus control unit 310c in the LSI transmits a predetermined plurality of bits of an ID code 320 to the respective LSIs 301 to 30n. The serial bus 1 is received at the input terminal of the LSI. From the n-bit CS information CHIPsel received serially from 50 bus and the ID code 320, it is detected whether the LSI should be chip enable (asserted). When the assertion is detected, the LSI is connected to the serial bus. A bus interface system for a semiconductor test apparatus, characterized in that a predetermined write / read operation is performed based on the bus interface operation selection information 130s serially received from 150bus, and the above is provided. According to the above invention, in a bus interface system in which a large number of selection information is supplied to an LSI and a write / read operation is performed between the control CPU and a plurality of LSIs under complicated selection conditions based on the selection information, A bus interface method of a semiconductor test device that can significantly reduce the number of signals connected to the semiconductor device can be realized.

FIG. 2 shows a solution according to the present invention. Also, the ID code 320 having the predetermined plural bit width is a fixed individual code value based on a high level / low level based on a wiring pattern of a printed circuit board, or an individual code value variably set by a switch. There is a bus interface system of the semiconductor test device described above, which is supplied to an input terminal.

FIG. 3 shows a solution according to the present invention. The form of the serial bus 150bus is composed of four control lines including a bidirectional bus SDATA having a 1-bit width, a serial clock SCLK, a start signal STT, and a read enable signal VALID. The bus interface of the above-described semiconductor test device, wherein the bus interface is the position information indicating the beginning of the write / read operation, and the read valid signal VALID is period information indicating that the output of data read from the LSI is valid. There is a method.

FIG. 6 shows a solution according to the present invention. In addition, when there are a plurality of LSI mounting boards having the same circuit configuration for implementing the above-mentioned LSI, and when a single control bus I / F unit 100 performs a bus interface, a different board select for each of the above-mentioned LSI mounting boards is required. The signal BS2 is supplied from the outside to the board via the board connector, and the board select signal BS2 is supplied to the input terminal of the serial bus control section 310c in the LSI of all the LSIs of the board, and the ID code for identifying the LSI is provided. There is a bus interface system of the semiconductor test apparatus described above, which is used as a part of the 320.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail together with examples with reference to the drawings.

The present invention will be described below with reference to FIG. 1, FIG. 2, and FIG. Elements corresponding to the conventional configuration are denoted by the same reference numerals.

As shown in FIG. 1, a main part configuration according to the present application includes a control CPU, a tester bus TBUS, a control bus I / F unit 100, a serial bus 150bus, and LSIs 301 to 30n. The internal configuration of the control bus I / F unit 100 includes a TBUS I / F unit 110, a selection register 130, and a serial bus I / F unit 150. Each of the LSIs 301 to 30n includes a serial bus control unit 310c in the LSI and an individual ID code 320. In the above configuration, except for the serial bus 150bus, the serial bus I / F unit 150, and the serial bus control unit 310c in the LSI, the other elements are the same as the conventional ones, and thus need not be described.

Here, the serial bus 150bus shown in FIG. 1 will be described together with the timing chart of FIG. FIG. 3A is a timing chart of the write operation, and FIG. 3B is a timing chart of the read operation. In this example, the serial bus 150bus is composed of four control lines including a 1-bit bidirectional data bus SDATA, a serial clock SCLK, a start signal STT, and a read valid signal VALID. And each LSI are connected in parallel. The start signal STT is position information (see FIGS. 3A and 3D) indicating the head of the write / read operation. The write operation is performed when the WR mode bit of the bidirectional data bus SDATA at that timing is “0”, and “1”. Is the read operation.

The bus interface operation selection information 130s of a large number of predetermined bits is serially stored in a predetermined order immediately after the WR mode bit, for example, in this example, the edge simultaneous write register Sil, the edge selection register EDGEsel, and the channel selection register. The data is serially transmitted as serial selection information 135s (see FIG. 3H) in the order of the star CHsel, the child selection register CHILDsel, the bank selection register BANKsel, the chip selection information CHIPsel, and the LSI internal register selection register REGsel. Here, in the serially output 10-bit chip select information CHIPsel, CS1 at the beginning is an enable bit for an LSI having a code value of “0”, and CS2 is an enable bit for an LSI having a code value of “1”. In the same manner, the last is an enable bit for the LSI having the code value "9". The read valid signal VALID indicates that the output of the data read from the LSI is valid, and is period information indicating a period from the start to the end of the read (see FIG. 3F).

As shown in the timing chart of FIG. 3, the serial bus I / F section 150 shown in FIG. 1 uses the four control lines and bi-directionally transmits a serial data stream synchronized with the serial clock SCLK. This is a 1-bit width serial bus for exchanging data. The serial data string to be output includes, in a predetermined order, n = 10-bit CS information CHIPsel held by the enable register 132 and a multi-bit bus interface operation selection information 130s held by the other selection registers 130. It is transmitted from the serial bus 150bus as serial selection information 135s (see FIGS. 3H and 3K). As a result, a great advantage is obtained in that the number of signals supplied to the selection register 130 becomes unnecessary.

As shown in FIG. 2, the ID code 320 is code information for uniquely assigning and recognizing each LSI. Here, since it is a 4-bit example, 16 types of codes can be recognized, and up to 16 LSIs can be mounted. For example, in the case of the "LLLL" signal level shown in FIG. 2A, the code value is "0", and the "HHHH" signal level is the code value "15". This code information is supplied to the serial bus control unit 310c in the LSI. In addition, as shown in FIG. 2 (a), the code value is normally added in a form in which unique code information fixed by a high level / low level by a wiring pattern of a printed circuit board is added. Alternatively, as shown in FIG. 2B, a switch may be provided in which some or all bits are variably set. As a result, four IC terminals are used to identify each LSI. If up to 64 LSIs are identified, only six IC terminals are sufficient. In the case of an LSI having a built-in nonvolatile memory, the ID code 320 may be built in the nonvolatile memory to eliminate the four input terminals, if desired.

The in-LSI serial bus control unit 310c shown in FIG. 1 includes a reception register 315 and latches and holds a serial data string (WR bit, serial selection information 135s, write data WDATA, etc.) from the serial bus 150bus. . The latched serial selection information 135s is the same as the conventional bus interface operation selection information 130s, and is used for selection control at the time of write / read operation similarly to the conventional one based on this. Then, from the CS information CHIPsel of n = 10 bits in the serial data string from the serial bus 150bus and the ID code 320, it is detected whether or not the bit information of the chip enable signal for the LSI is a valid signal (assert). At the time of assertion, a predetermined write / read operation is performed on the LSI based on the latched serial selection information 135s. Here, the detection of the chip enable signal for the LSI means that the position of the enable bit for the LSI is obtained from the code value of the ID code 320, and whether the bit position is enabled is detected. For example, when the code value is "0", the head bit position of the CS information CHIPsel is the detection position of the enable bit, and when the code value is "9", the 10 bit position from the head of the CS information CHIPsel is the detection position of the enable bit. . As a result, write / read operations to a plurality of LSIs can be simultaneously enabled as in the conventional case. Accordingly, there is an advantage that a dedicated signal line for enabling each LSI as in the related art is not required.

By providing the above-described configuration, for example, a total of eight signal lines including four serial buses 150 bus and four individual ID codes 320 unique to each LSI are used, so that the same complicated selection as in the past can be achieved. Bus interface can be performed under conditions. As a result, there is obtained a great advantage that the number of connected signals can be significantly reduced.

The means for realizing the present invention is not limited to the above embodiment. For example, the plurality of LSIs is not limited to only the LSIs having the same circuit function, and may be mixedly mounted with the LSIs having different circuit functions by providing the above-described serial bus control unit 310c in the LSI. In the timing chart of FIG. 3, the serial selection information 135s has been described as a specific example in which the bit length is fixed, but if desired, the bit information of each selection register 130 is output to the serial bus in the serial bus I / F unit 150. The configuration may be such that a setting register that can change the bit length is additionally provided. In particular, the bit length of the chip select information CHIPsel that increases or decreases in proportion to the number of LSIs can be changed. As a result, a versatile serial bus I / F unit 150 can be flexibly applied to LSIs having different bit lengths of the serial selection information 135s. Further, as shown in FIG. 6, in the case of a board configuration in which a plurality of, for example, four, identical boards are mounted on a unit, a 6-bit ID code 320 is used, and 2 bits of the ID code 320 are different for each board. Is connected to the board select signal BS2 to which is attached. Thus, even in a unit configuration in which a plurality of identical boards are mounted, each LSI can be individually identified and used as a bus interface.

[0026]

[Effect of the invention]

 The present invention has the following effects from the above description. As described above, according to the present invention, the multi-bit bus interface operation selection information 130s and the multi-bit chip select information CHIPsel are put on the serial bus 150bus and serially interfaced, so that each LSI A great advantage is obtained that the number of signal connections for bus interface between the two can be greatly reduced. Accordingly, smaller LSI packages can be applied, the LSI mounting density on the board can be improved, and the advantages of further miniaturization of the unit can be obtained. In particular, the effect is great in a semiconductor test apparatus in which the number of tester pins having the same circuit configuration is several hundred to several thousand.

[Submission date] November 19, 1999 (November 19, 1999)

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction contents]

[0011]

As described above, in the bus interface device of the prior art, in an LSI in which it is necessary to perform bus interface under complicated selection conditions using a large number of signal lines, a signal related to the bus interface is used. There is a drawback that the number of lines increases. As a result, the package becomes larger, the mounting area on the board becomes larger, and a region for arranging a large number of wiring patterns is also required. This limits the number of LSIs to be mounted and is not preferable in terms of cost. From these viewpoints, the prior art has practical difficulties. Therefore, a problem to be solved by the present invention is to supply a large number of selection information to an LSI, and perform a write / read operation between the control CPU and a plurality of LSIs under complicated selection conditions based on the selection information. An object of the present invention is to provide a bus interface device of a semiconductor test device capable of reducing the number of signals connected to an LSI in the bus interface device .

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction contents]

[0012]

[Means for Solving the Problems]

 First, in order to solve the above-mentioned problem, a control bus I / F unit 100 is provided at an input / output unit of a unit or a board, and the control bus I / F unit 100 includes a predetermined number n of a plurality of control buses provided in a board. A predetermined interface is provided between the LSIs 301 to 30n and the control CPU, and a plurality of internal registers REG are provided therein. The internal registers REG are preset by the control CPU, and are connected to at least a plurality of n LSIs 301 to 30n. This is the selection information used at the time of the write / read operation, and is composed of bus interface operation selection information 130s and chip select information (CS information) CHIPsel. The n-bit CS information CHIPsel is a single or a plurality of specified LSIs. This signal enables (asserts) the write / read operation at the same time as the target. The bus interface operation selection information 1 30s is a selection signal commonly supplied to each LSI, the bus interface of the semiconductor testing device provided with the structureapparatusIn the above, the control bus I / F unit 100 and a plurality of n LSIs 301 to 30n are interfaced in a 1-bit serial bus form, and each time a write / read operation with the LSI is performed, the above-mentioned selection is made onto a 1-bit serial bus 150bus. Information (bus interface operation selection information 130s and CS information CH IPsel) in a predetermined order and sent to each LSI, and a plurality of n LSIs 301 to 30n are provided with a corresponding serial bus control unit 310c in the LSI. The internal serial bus control unit 310c receives a predetermined plurality of bits of an ID code 320 at an input terminal of the LSI, and determines the LSI based on the n-bit CS information CHIPsel and the ID code 320 received serially from the serial bus 150bus. Should be chip enable (assert) The LSI performs predetermined write / read operations based on the bus interface operation selection information 130s serially received from the serial bus 150bus when an assert is detected. Bus interface for semiconductor test equipment characterized by the following: apparatus It is. According to the invention, a bus interface that supplies a large number of selection information to an LSI and performs a write / read operation between the control CPU and a plurality of LSIs under complicated selection conditions based on the selection information.apparatus, A bus interface for semiconductor test equipment that can significantly reduce the number of signals connected to LSIapparatusCan be realized.

[Procedure amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction contents]

FIG. 2 shows a solution according to the present invention. Also, the ID code 320 having the predetermined plural bit width is a fixed individual code value based on a high level / low level based on a wiring pattern of a printed circuit board, or an individual code value variably set by a switch. There is a bus interface device of the semiconductor test device described above, which is supplied to an input terminal.

[Procedure amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Change

[Correction contents]

FIG. 3 shows a solution according to the present invention. The form of the serial bus 150bus is composed of four control lines including a bidirectional bus SDATA having a 1-bit width, a serial clock SCLK, a start signal STT, and a read enable signal VALID. The bus interface of the above-described semiconductor test device, wherein the bus interface is the position information indicating the beginning of the write / read operation, and the read valid signal VALID is period information indicating that the output of data read from the LSI is valid. There is a device .

[Procedure amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0015

[Correction method] Change

[Correction contents]

FIG. 6 shows a solution according to the present invention. In addition, when there are a plurality of LSI mounting boards having the same circuit configuration for implementing the above-mentioned LSI, and when a single control bus I / F unit 100 performs a bus interface, a different board select for each of the above-mentioned LSI mounting boards is required. The signal BS2 is supplied from the outside to the board via the board connector, and the board select signal BS2 is supplied to the input terminal of the serial bus control section 310c in the LSI of all the LSIs of the board, and the ID code for identifying the LSI is provided. There is a bus interface device of the semiconductor test device described above, which is used as a part of the 320.

[Brief description of the drawings]

FIG. 1 is a main configuration diagram of a serial interface bus interface between an LSI and a control bus I / F unit using four control signals according to the present invention.

FIG. 2 shows an example of an ID code assignment mode according to the present invention.

FIG. 3 is a timing chart for explaining the operation of the serial bus interface according to the present invention;

FIG. 4 is a main part configuration diagram of a conventional bus interface between a LSI and a control bus I / F section using a number of parallel control signals.

FIG. 5 is a conceptual configuration diagram of a semiconductor test apparatus.

FIG. 6 is a connection example of adding CS information in a unit configuration in which a plurality of the same boards are mounted according to the present invention.

[Explanation of symbols]

 Reference Signs List 100 control bus I / F unit 110 TBUS I / F unit 120 internal bus I / F unit 130 selection register 132 enable register 150 serial bus I / F unit 310c serial bus control unit in LSI 315 reception register 320 ID code 330 bus control in LSI Section TBUS tester bus DC logical comparator DUT device under test FC waveform shaper PG pattern generator TG timing generator

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[Procedure amendment]

[Submission date] November 19, 1999 (1999.11.
19)

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] Name of device

[Correction method] Change

[Correction contents]

[Name of device] Bus interface device for semiconductor test equipment

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] Claims for utility model registration

[Correction method] Change

[Correction contents]

[Utility model registration claims]

Claims (3)

[Utility model registration claims] 1. A control bus I / F section is provided at an input / output part of a unit or a board, and the control bus I / F is provided.
A predetermined number n of LSIs and a control CP
A predetermined interface is provided with a plurality of internal registers. The internal registers are preset by the control CPU, and include selection information used when writing / reading with a plurality of n LSIs. Yes, it consists of bus interface operation selection information and chip select information, that is, CS information.
The bit CS information is a single or a plurality of specified LSIs.
The bus interface operation selection information is a selection signal commonly supplied to each of the LSIs, and the bus interface operation selection information is a signal that is commonly supplied to each LSI. The bus I / F section and the plurality of n LSIs are interfaced in a 1-bit serial bus form, and each time a write / read operation with the LSI is performed, the selection information is placed on the 1-bit serial bus in a predetermined order. Each L
A plurality of n-side LSIs are provided with a corresponding serial bus control unit in the LSI, and the serial bus control unit in the LSI has a predetermined multiple-bit ID.
A code is received at an input terminal of the LSI, and it is detected whether the LSI should be chip-enabled, that is, asserted, from the n-bit CS information and the ID code serially received from the serial bus, and the assertion is detected. Wherein the LSI performs a predetermined write / read operation based on the bus interface operation selection information serially received from the serial bus, and comprises: a bus interface system for a semiconductor test apparatus. 2. An ID code for supplying a fixed individual code value at a high level / low level by a wiring pattern of a printed circuit board or an individual code value variably set by a switch to an input terminal of each LSI. 2. A bus interface system for a semiconductor test apparatus according to claim 1, wherein: 3. A serial bus configuration comprising four control lines including a bidirectional bus SDATA having a 1-bit width, a serial clock SCLK, a start signal STT, and a read enable signal VALID. Item 2. A bus interface system for a semiconductor test device according to item 1.