JP3066941U - Output buffer with low noise and high driving capability - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To provide an output buffer with low noise and high driving capability. The pull-up circuit includes a pull-up circuit and a push-down circuit, the pull-up circuit providing a start voltage to a pull-up terminal of a pull-up driver circuit for driving an output of an output buffer, and an output terminal source. A circuit loop that prevents the ability to produce a voltage from decaying in the latter half of the operation of the pull-up circuit, the push-down circuit also ensuring that the operating capacity does not decay in the latter half of the operation.

Description

[Detailed description of the invention]

[0001]

[Technical field to which the invention belongs]

 The present invention relates to an output buffer, and more particularly to an output buffer that operates quickly and has a reduced layout size and complexity.

[0002]

[Prior art]

 The output buffer 1 shown in FIG. 1 has a pull-up transistor 102 and a push-down transistor 104. The data input signal DI and the output enable signal OE control the turn-on and turn-off of the pull-up transistor 102 and the push-down transistor 104. When the pull-up transistor 102 is turned on, the push-down transistor 104 is turned off. . When the output enable signal OE is high and the data input signal DI is low, the pull-up transistor 102 is turned off and the push-down transistor 104 is turned on. A disadvantage of this circuit is that severe current spikes occur frequently when the pull-up transistor 102 (or push-down transistor 104) is turned on or off. This current spike flows through the impedance and inductance components of the power and ground wires. Therefore, noise was easily generated in the internal power supply and the ground fault voltage. Excessive noise could cause abnormal operation in the device, especially in the multi-output buffer.

In order to overcome the disadvantages of the output buffer 1 described above, another output buffer 2 as shown in FIG. 2 has already been developed. In the output buffer 2, a pull-up element 202 including three pull-up transistors 206, 208 and 210 connected in parallel, and a push-down element 204 including three push-down transistors 212, 214 and 216 connected in parallel. Having. The turn-on and turn-off of these transistors are sequence controlled, so the current spike is effectively controlled. In the VLSI, a desirable operation load is set to 10 PFs to 100 PFs with respect to an output terminal of a general output buffer. Therefore, the width of the pull-up and push-down transistors has become relatively large. In particular, in high-speed devices, the width of these transistors has reached hundreds of microns to thousands of microns. The pull-up device 202 and the push-down device 204 shown in FIG. 2 include six transistors 206, 208, 210, 212, 214, 216, each of which is one of the transistors 102 or 104 in FIG. / 3 width. While this conventional output buffer can reduce current spikes, the layout pattern is too complex and the layout area is too large.

In addition, after a certain charging time of the pull-in element, the gate voltage V _GS applied to the source and the drain voltage applied to the source gradually decrease, and as a result, the latter half of the charging time Slowed down. Thus, this type of output buffer circuit design, while improving the noise problem, was not satisfactory in terms of speed.

In the output buffer 3 shown in FIG. 3, the pull-up element 302 includes two pull-up transistors 306 and 308 in parallel, and the push-down element includes two push-down transistors 310 and 312 in parallel. The gate of pull-up transistor 306 is electrically connected to node 314 to receive a normal operating voltage. The gate of the pull-up transistor 308 is electrically connected to the bootstrap 316 so as to receive the delayed operation voltage. This circuit can improve the noise and increase the charge speed, but has the problem that the layout is complicated and the layout area is large because two pull-up transistors and two push-down transistors are used. Was.

[0006]

[Problems to be solved by the invention]

 It is an object of the present invention to provide a kind of output buffer in which when turned on or off, little or no current spike occurs, its layout pattern is not complicated, and its layout area is small.

Another object of the present invention is to provide a kind of output buffer in which the charge speed does not decrease in the latter half of the charge time.

[0008]

[Means for Solving the Problems]

 The invention according to claim 1 is a kind of output buffer having a voltage source, a ground terminal, and an output terminal, which is provided with a pull-up circuit and a push-down circuit. A pull-up driver circuit having a pull-up terminal and an output electrically connected to the output terminal, the pull-up driver circuit having the output terminal as a power supply voltage, and electrically connecting the input terminal to the input terminal. It has a control input connected thereto, and a voltage output electrically connected to the pull-up terminal, and includes a starting voltage circuit for providing a starting voltage to the pull-up terminal.

According to the invention of claim 2, the pull-up driver circuit has first, second, and control terminals, the first terminal being connected to the voltage source, and the second terminal being connected to the output. The control terminal is electrically connected to the pull-up terminal.

According to the invention of claim 3, the starting voltage circuit further comprises a voltage input and a first and second transistor, both of which are first, second and control. First, second and control terminals of the first transistor are electrically connected to the voltage source, the first terminal of the second transistor, and a reference voltage source, respectively. When the source is at a voltage not higher than the voltage source, the first, second and control terminals of the second transistor are connected to the voltage input, voltage output and control input of the starting voltage circuit, respectively. It is connected in a way.

According to the invention of claim 4, the starting voltage is not higher than the source voltage.

The invention of claim 5 is characterized in that the slope of the voltage increase at the pull-up terminal is the same as the slope of the voltage increase at the output after the pull-up terminal has reached the starting voltage. I have.

[0013] The invention of claim 6 is characterized in that the pull-up driver circuit has a high driving capability during the latter half of the operation period of the pull-up circuit.

According to the invention of claim 7, the inductance noise of the output buffer is not larger than 0.5V.

The invention according to claim 8 is characterized in that the voltage of the output terminal reaches 50% of the source voltage within 2 nanoseconds after the pull-up circuit is turned on.

[0016] The invention according to claim 9 is a reference voltage circuit having the starting voltage circuit, further having a voltage input, further having a reference voltage output, and providing a reference voltage to the reference voltage output, A voltage increasing circuit having a control input and a voltage output, wherein the voltage output is electrically connected to a voltage input of the starting voltage circuit, and the control input is connected to the input terminal; The voltage output is a control circuit having an input, a control terminal, and an output for increasing the voltage of the pull-up terminal from the start voltage to the start voltage circuit, wherein the input is the reference voltage circuit. The control terminal is electrically connected to the reference output of The output of the control circuit is electrically connected to the control input of the voltage increasing circuit, and the output of the control circuit is pulled up to the starting voltage circuit by the voltage increasing circuit. The degree to which the voltage of the terminal is increased is controlled, and the control circuit has a function corresponding to the voltage of the control terminal and has the above-mentioned.

In the invention according to claim 10, the voltage increasing circuit has a capacitor having first and second terminals, the first and second terminals being the control input and the voltage output of the voltage increasing circuit. Are electrically connected to each other.

The invention of claim 11 is characterized in that the slope of the voltage increase at the pull-up terminal is substantially the same as the voltage increase at the output terminal.

In the invention according to claim 12, the control circuit has a transistor having first, second and control terminals, and the first, second and control terminals are input, output, and output terminals of the control circuit. And the control terminal.

The invention of claim 13 is an apparatus having a voltage source, a ground and an output terminal, comprising a push-down circuit and a pull-up circuit, wherein the push-down circuit outputs a signal for turning on the push-down circuit. A push-down driver circuit having a receiving input terminal, a push-down terminal, and an output, wherein the output of the push-down driver circuit is electrically connected to the output terminal and reduces the voltage of the output terminal to ground voltage. A start voltage circuit having an output, wherein the output of the start voltage circuit is electrically connected to the push-down terminal and supplies a start voltage to the push-down terminal; It has a push-down terminal and is electrically connected to the output terminal. A push-down driver circuit having an output connected to the input terminal, a delay circuit having an input electrically connected to the input terminal, having an output, and delaying a signal to the input; and a first and second input. And a voltage increase circuit having an output, wherein a first input of the voltage increase circuit is electrically connected to the input terminal, and a second input of the voltage increase circuit is electrically connected to an output of the delay circuit. Connected, the output of the voltage increasing circuit being electrically connected to the push-down terminal, the voltage increasing circuit increasing the voltage on the push-down terminal in response to a signal on the first input of the voltage increasing circuit. And increasing the degree of voltage increase on the push-down terminal in response to a signal on a second input of the voltage increase circuit. It is set to.

In the invention according to claim 14, the push-down driver circuit includes first, second and control terminals, wherein the first, second and control terminals are electrically connected to the ground and the push-down terminal, respectively. It is connected to the output of the driver circuit and the push-down terminal.

According to the invention of claim 15, the starting voltage circuit has a control input and includes first and second transistors, both of which have first, second and control terminals. The first, second and control terminals of the first transistor are electrically connected to the voltage source, the first terminal of the second transistor and the reference voltage, respectively, and the second and control terminals of the second transistor are electrically connected to each other. And a control input of the starting voltage circuit is electrically connected to the input terminal, and a control terminal of the starting voltage circuit is electrically connected to the output and a control terminal of the starting voltage circuit.

According to the invention of claim 16, the voltage increasing circuit includes first and second transistors, each of which has first, second and control terminals, and The first, second and control terminals of one transistor are electrically connected to the voltage source, the first terminal of the second transistor and the first input of the voltage increasing circuit, respectively, and the second and control terminals of the second transistor are connected The output of the voltage increasing circuit and the second input of the voltage increasing circuit are electrically connected to each other.

The invention according to claim 17 is a delay buffer having an additional input, and a signal indicating whether the delay buffer is operated at a high voltage or a low voltage is sent to the additional input. In response to this signal, the delay buffer is to provide a long delay when operated at high voltage.

The invention according to claim 18 is an apparatus having a voltage source, a ground, and an output terminal, the apparatus including a pull-up circuit and a push-down circuit, wherein the pull-up circuit turns on the pull-up circuit. A pull-up driver circuit having a first input terminal for receiving a signal, a pull-up terminal and an output, wherein the output of the pull-up driver circuit is electrically connected to the output terminal, and the output terminal is connected to a source voltage. A first starting voltage circuit having a control input, a voltage input, and having a voltage output connected to the pull-up terminal, the first starting voltage circuit providing a first starting voltage to the pull-up terminal. A reference voltage circuit having a reference output, said reference voltage circuit providing a reference voltage on said reference output. A voltage increase circuit having a control input and a voltage output, wherein the voltage output of the voltage increase circuit is electrically connected to the voltage input of the first starting voltage circuit, and the control input Is connected to the first input terminal, and the voltage output of the voltage increasing circuit causes the starting voltage circuit to increase the voltage from the first starting voltage at the pull-up terminal; and an input, a control terminal, and an output. A control circuit having an input as the reference output of the reference voltage circuit, a control terminal of the control circuit electrically as the pull-up terminal, and an output of the control circuit as the voltage increase. Electrically connected to the control terminals of the circuit, The output of the roll circuit includes: a voltage increasing circuit that controls the degree of increase of the voltage at the pull-up terminal from the starting voltage, which leads to the starting voltage circuit; and the push-down circuit includes the push-down circuit. And a push-down driver circuit having a push-down terminal and an output, wherein the output of the push-down driver circuit is electrically connected to the output terminal, and A second start voltage circuit having an output provided for lowering the voltage of the terminal to the ground voltage, and an output of the second start voltage circuit electrically connected to the push-down terminal; Providing a second starting voltage to the push-down terminal; and a delay circuit having an input and an output. Wherein the input of the delay circuit is electrically connected to the second input terminal and has a function of delaying a signal to be supplied to an input of the delay circuit; and a first and a second input and an output. A second voltage increase circuit, wherein a first input of the second voltage increase circuit is electrically connected to the second input terminal, and a second input of the second voltage increase circuit is electrically connected to the delay circuit. The output of the second voltage increasing circuit is connected to the output, and the output of the second voltage increasing circuit is electrically connected to the push-down terminal, and the voltage on the push-down terminal is applied to the signal on the first input of the second voltage increasing circuit. And the degree of increase in the voltage on the push-down terminal is increased in response to the signal of the second input of the second voltage increasing circuit.

[0026]

[Embodiment of the invention]

 In one embodiment of the present invention, an output buffer having one pull-up circuit and one push-down circuit is provided. This pull-up circuit includes one pull-up driver circuit and one start voltage circuit. The starting voltage circuit provides a starting voltage to a set of pull-up terminals to reduce current spikes and noise during operation of the device. The starting voltage value is equal to or lower than the voltage source.

In another embodiment of the present invention, the reference voltage circuit for further increasing the voltage on the pull-up terminal and the degree to which the voltage increasing circuit increases the voltage provided to the pull-up terminal of the starting voltage circuit. And a control circuit for controlling the

In yet another embodiment of the present invention, the present invention is an output buffer having a pull-up and a push-down circuit, wherein the push-down circuit reduces a voltage at an output terminal of the device. A start voltage circuit for providing a start voltage to the push-down terminal of the push-down driver circuit; and a signal delay circuit for delaying the sent ON signal. The voltage increasing circuit increases the voltage of the push-down terminal in response to the ON signal, and increases the voltage increase in response to the delayed ON signal.

[0029]

【Example】

 In order to explain the present invention in more detail, two application examples will be described below. First, the case using a high-voltage power supply (5 V) and then the case using a low-voltage power supply (3.3 V) will be described.

When a high voltage power supply is applied to the present invention and the output signal IO is brought to a high state, the pull-up transistor 402 is therefore turned on and the push-down transistor is turned off, as shown in FIG. . When 5V is used as the power supply, the gate voltage LV 'of the PMOS transistor Q14 becomes high (logic level 1), and the transistor Q14 is turned off. Voltage VR is a DC voltage generated by a digital logic circuit and is at an appropriate level, and is usually equal to or less than the voltage source (2V ≦ VR ≦ 5V). Therefore, when the data input signal DI is high and the output enable signal OE is high, the transistors Q1, Q11, Q12, Q13 and Q16 are turned on and the pull-up terminal PU has two paths, namely Q10 , Q11 and Q12, Q16, VR-Vt is applied. (Vt is the threshold voltage of transistors Q11 and Q12). At the same time, the transistor Q13 is turned on, the voltage source V _CC is applied to the node N3, and the voltage of the node N3 rises from 0V. Then, the voltage of the node N7 is applied through the capacitor Q15. The voltage at the pull-up terminal PU increases due to the transistor Q16, and when the transistor Q13 is subsequently turned on, the voltage at the node N3 further increases. This positive loop causes the voltage at node N3 to rise continuously and dynamically until the voltage at drain D13 of transistor Q13 (which is equal to V _CC ) and the voltage at source 13 of transistor Q13 are equal. And the transistor is turned off. At this time, the voltage of the pull-up terminal PU reaches an expected value. FIG. 5 shows voltage-time diagrams of OE, PU, N3, N7 and IO when a high voltage power supply is employed and the output is '1'.

Next, a case where a high-voltage power supply is applied and the output signal IO is low will be described. At this time, the pull-up transistor 402 is turned off, and the push-down transistor 404 is turned on. A data input signal DI Gallo over state, if the output enable signal OE is at a high state, the push-down terminal PD VR-V _T, the transistors Q21 and Q22 is applied (V _T is Trang register Q21 threshold Voltage). Since the gate voltage of transistor Q26 is delayed by delay circuit BL1 and the gate voltage of transistor Q25 is not delayed by any delay circuit, as shown in FIG. The source Vcc is applied (because the transistor Q26 has not yet been turned on by the delay circuit BL1), and then the voltage is applied by the transistors Q25 and Q26. FIG. 6 also shows the OE, N3, N7, IO voltage-time diagrams when the high voltage source is employed and the output is '0'.

When the voltage source is at 5V, the input signal at the terminal LV 'goes high, and the transistor Q24 is turned off to obtain a longer delay time.

Further, in the push-down circuit, no bootstrap circuit is used. The reason is that the voltage from the gate to the source is always kept relatively large (since the push-down transistor 404 is grounded).

Next, an application example of a low-voltage power supply in which the output signal IO is in a high state will be described. Pull-up transistor 402 is turned on and push-down transistor 404 is turned off. Due to the small voltage source, the noise generated is less severe for the same circuit, and output speed is a primary consideration. In low voltage applications, terminal LV 'is tied to a low level voltage (typically ground). Therefore, when a high voltage data is read, the pull-up terminal PU of the pull-up transistor 40 2 VR-V _T is applied through the transistor Q16 (the threshold voltage of V _T is the transistor Q12), and at the same time, the transistor Q13 , And the voltage source Vcc is immediately applied to the node N3 (since the terminal LV 'is grounded and the transistor Q14 is turned on). Then, the voltage at the node N7 rises through the capacitor Q15, and the voltage at the node N7 is transferred to the pull-up terminal PU of the pull-up transistor 402 via Q16. FIG. 7 shows a state where the voltage is applied and the output signal becomes “1”.

Finally, an example of applying a low voltage when the output signal IO is in a low state will be described. Pull-up transistor 402 is turned off and push-down transistor 404 is turned on. FIG. 8 shows a voltage-time diagram of OE, PD, N3, N &, IO when a low voltage source is applied and the output is '0'. The operation of the circuit in this low voltage application is similar to the high voltage application except that transistor Q24 is turned on. The delay time of the delay circuit BL1 is reduced according to the width of the transistor Q24, and the voltage of the push-down terminal PD reaches the voltage source Vcc more quickly.

[0036]

[Effect of the invention]

Although the circuit of the present invention has many effects, first, the present invention has a first starting voltage circuit, and the starting voltage of the pull-up terminal PU (gate of the pull-up transistor) is smaller than or equal to the power source. It can be set to a value. Current spikes and noise are reduced. Further, the voltage of the pull-up terminal PU gradually increases during the pull-up operation, and the increasing gradient becomes almost the same as the source voltage of the pull-up transistor 402 (as in the output IO of the output buffer). The voltage V _GS applied from the gate to the source of the transistor is very small. In other words, the pull-up transistor 402 still has a high operation capability even in the later stage of the pull-up operation. On the other hand, during the pull-up operation, the gate voltage of the pull-up transistor of the conventional output buffer is constant, but the source voltage of the pull-up transistor of the conventional output buffer continuously increases. Then, the voltage VGS applied from the gate to the source gradually decreased, so that the operation capability of the conventional output buffer was not so good in the latter half of the pull-up operation. Noise is another factor that affects driving performance. The lower the noise, the higher the driving performance. The inductance noise of the output buffer of the present invention is very small, and therefore the operation capability of the present invention is better than that of the conventional one.

Another advantage of the present invention is that it can output faster than the conventional output buffer shown in FIGS. In the conventional output buffer shown in FIG. 3, the output capability is made faster by adjusting the delay time of the delay circuit, but there is another disadvantage. That is, it is difficult to control the delay time. If the delay time is too short, the problem of the current spike remains, and if the delay time is too long, the speed is too slow. In addition, the circuit of the present invention uses only the pull-up transistor and the push-down transistor, the layout area is minimal, the layout is not so complicated, and there is no need to increase the width of the pull-up transistor and the push-down transistor.

Finally, a unique feature of the present invention is that the output buffer of the present invention can be applied in two ways. That is, a high voltage application and a low voltage application. When a low voltage is applied, the gate voltage of the pull-up transistor quickly reaches the expected value, and the gate voltage of the push-down transistor quickly reaches the power supply voltage by using the transistor Q24. Thus, in low voltage applications, the output speed does not slow down.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram of a conventional output buffer.

FIG. 2 is an electric circuit diagram of another conventional output buffer.

FIG. 3 is an electric circuit diagram of still another conventional output buffer.

FIG. 4 is an electric circuit diagram of the output buffer of the present invention.

FIG. 5 is a voltage-time diagram of OE, PU, N3, N7, and IO curves when the power supply voltage is 5 V and the output is “1” according to the present invention.

FIG. 6 is a voltage-time diagram of OE, PD, N3, N7, and IO curves when the power supply voltage is 5 V and the output is '0' according to the present invention.

FIG. 7 is a voltage-time diagram of OE, PU, N3, N7, and IO curves when the power supply voltage is 3.3 V and the output is output '1' according to the present invention.

FIG. 8 is a voltage-time diagram of OE, PD, N3, N7, and IO curves when the power supply voltage is 3.3 V and the output is “1” according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Output buffer 102 ... Pull-up transistor 104 ... Push-down transistor D
I: Data input signal OE: Output permission signal 2
... Output buffers 206, 208, 210 ... Pull-up transistors 202 ... Pull-up elements
212, 214, 216: push-down transistor 204: push-down element 3: output buffer 302: pull-up element 306, 308: pull-up transistor 310, 312: push-down transistor 3
14 node 316 bootstrap 402 pull-up transistor 404 push-down transistor IO output signal PD
... Pushdown terminal BL1 ... Delay circuit P
U: Pull-up terminal

Claims (18)

[Utility model registration claims] 1. A type of output buffer having a voltage source, a ground terminal, and an output terminal, comprising a pull-up circuit and a push-down circuit, wherein the pull-up circuit turns on the input terminal, and a pull-up terminal. Having an output electrically connected to the output terminal, a pull-up drive circuit having the output terminal as a power supply voltage, a control input electrically connected to the input terminal, and the pull-up terminal An output buffer having a voltage output electrically connected to said output terminal and providing a starting voltage to said pull-up terminal. 2. The pull-up driver circuit according to claim 1, wherein
A second terminal and a control terminal, wherein the first terminal is electrically connected to the voltage source, the second terminal is electrically connected to the output, and the control terminal is electrically connected to the pull-up terminal. The output buffer according to claim 1, wherein the output buffer is connected to the output buffer. 3. The starting voltage circuit further includes a voltage input and first and second transistors, both of which are first and second transistors.
And a control terminal, wherein the first, second, and control terminals of the first transistor are electrically connected to the voltage source, the first terminal of the second transistor, and a reference voltage source, respectively. When the source is at a voltage not higher than the voltage source, the first, second and control terminals of the second transistor are respectively electrically connected to the voltage input, voltage output and control input of the starting voltage circuit. The output buffer according to claim 1, wherein: 4. The output buffer according to claim 1, wherein the starting voltage is not higher than a source voltage. 5. The method of claim 1, wherein the slope of the voltage increase at the pull-up terminal is the same as the slope of the voltage increase at the output after the pull-up terminal has reached the starting voltage. Output buffer. 6. The output buffer according to claim 1, wherein the pull-up driver circuit has a high driving capability during the latter half of the operation period of the pull-up circuit. 7. The output buffer according to claim 1, wherein the inductance noise is not more than 0.5V. 8. After the pull-up circuit is turned on,
Within 2 nanoseconds, the voltage at the output terminal is 5% of the source voltage.
Output buffer according to claim 1, characterized in that it reaches 0%. 9. The reference voltage circuit further having a voltage input and having a reference voltage output for providing a reference voltage to the reference voltage output, the control circuit further comprising a control input and a voltage output. A voltage increasing circuit having a voltage output electrically connected to a voltage input of the starting voltage circuit, a control input coupled to the input terminal, and a voltage output of the voltage increasing circuit having a pull-up terminal. A control circuit having an input, a control terminal, and an output, the input being electrically connected to a reference output of the reference voltage circuit. The control terminal is electrically connected to the pull-up terminal, and the control terminal The output of the roll circuit is electrically connected to the control input of the voltage increasing circuit, and the output of the control circuit controls the extent to which the voltage increasing circuit increases the voltage of the pull-up terminal to the starting voltage circuit, and The output buffer according to claim 1, wherein the control circuit responds to the voltage of the control terminal. 10. The voltage increasing circuit includes a capacitor having first and second terminals, the first and second terminals being electrically connected to the control input and a voltage output of the voltage increasing circuit, respectively. The output buffer according to claim 9, wherein: 11. The output buffer according to claim 9, wherein the slope of the voltage increase at the pull-up terminal is substantially equal to the voltage increase at the output terminal. 12. The control circuit according to claim 1, wherein said first and second control circuits are:
The output buffer according to claim 9, further comprising a transistor having a control terminal and a control terminal, wherein the first, second and control terminals are connected to the input, output and control terminals of the control circuit, respectively. . 13. An apparatus having a voltage source, ground and an output terminal, comprising: a push-down circuit and a pull-up circuit, the push-down circuit receiving an input signal for turning on the push-down circuit; A push-down driver circuit that is provided for lowering the voltage of the terminal to the ground voltage, has a push-down terminal, and has an output electrically connected to the output terminal; and a start voltage circuit having the output. The output of the starting voltage circuit is electrically connected to the push-down terminal and supplies a starting voltage to the push-down terminal, and has an input electrically connected to the input terminal, and has an output. A delay circuit for delaying a signal to the input, and a first and a second input and an output. A voltage increasing circuit having a first input electrically connected to the input terminal, a second input of the voltage increasing circuit electrically connected to an output of the delay circuit, The output of the voltage increase circuit is electrically connected to the pushdown terminal, the voltage increase circuit increasing the voltage on the pushdown terminal in response to a signal on a first input of the voltage increase circuit and increasing the voltage. An output buffer comprising: a voltage increasing circuit that increases a degree of a voltage increase on the push-down terminal in response to a signal on a second input of the circuit. 14. The push-down driver circuit,
A first, second, and control terminal are electrically connected to the ground, an output of the push-down driver circuit, and a push-down terminal, respectively. 14. The output buffer of claim 13. 15. The start voltage circuit has a control input and includes first and second transistors, both of which are first and second transistors.
And a control terminal, wherein the first, second and control terminals of the first transistor are electrically connected to a voltage source,
A second terminal electrically connected to a first terminal of the second transistor and a reference voltage, and a second and control terminal of the second transistor electrically connected to an output and a control terminal of the starting voltage circuit, respectively; 14. The output buffer according to claim 13, wherein a control input of the circuit is electrically connected to the input terminal. 16. The voltage increasing circuit includes first and second transistors, each of the first and second transistors having first, second and control terminals, wherein the first and second transistors have first and second control terminals. The second and control terminals are respectively an electrical voltage source, a first terminal of a second transistor,
And a second input terminal of the second transistor is electrically connected to an output of the voltage increasing circuit and a second input of the voltage increasing circuit. The output buffer according to claim 13, wherein 17. A delay buffer having an additional input, wherein a signal indicating whether the delay buffer is operated at a high voltage or a low voltage is sent to the additional input, and the delay buffer is responsive to the signal. 14. The output buffer of claim 13, wherein said delay buffer provides a long delay when operated at high voltage. 18. A device having a voltage source, a ground and an output terminal, comprising a pull-up circuit and a push-down circuit, wherein the pull-up circuit receives a signal for turning on the pull-up circuit.
An input terminal, a pull-up driver circuit having a pull-up terminal and an output, wherein an output of the pull-up driver circuit is electrically connected to the output terminal and causes the output terminal to reach a source voltage. A first start voltage circuit having a control input, a voltage input, and having a voltage output connected to the pull-up terminal, the first start voltage circuit providing a first start voltage to the pull-up terminal; and a reference output. A reference voltage circuit for providing a reference voltage on the reference output, and a voltage augmentation circuit having a control input and a voltage output, wherein the voltage output of the voltage augmentation circuit is electrical. Is connected to a voltage input of the first starting voltage circuit, and the control input is connected to the first input. The voltage output of the voltage increasing circuit is connected to a terminal, and the voltage output of the voltage increasing circuit causes the starting voltage circuit to increase the voltage from the first starting voltage at the pull-up terminal, and a control circuit having an input, a control terminal, and an output. The input of the control circuit is the reference output of the reference voltage circuit, the control terminal of the control circuit is electrically connected to the pull-up terminal, and the output of the control circuit is the control terminal of the voltage increasing circuit. Respectively electrically connected, the output of the control circuit comprising: a voltage-increasing circuit for controlling the degree of increase of the voltage at the pull-up terminal from the starting voltage to the starting voltage circuit; The down circuit is a signal that turns on the push-down circuit. A second input terminal for receiving, a push-down driver circuit having a push-down terminal and the output, the output of the push-down driver circuit electrically connected to said output terminal,
A second start voltage circuit having an output provided for lowering the voltage of the output terminal to the ground voltage; and an output of the second start voltage circuit electrically connected to the push-down terminal. And providing a second start voltage to the push-down terminal; and a delay circuit having an input and an output,
An input of the delay circuit electrically connected to the second input terminal for delaying a signal supplied on the input of the delay circuit; and a second voltage increasing circuit having first and second inputs and an output. Wherein a first input of the second voltage increasing circuit is electrically connected to the second input terminal, and a second input of the second voltage increasing circuit is electrically connected to an output of the delay circuit. An output of the second voltage increasing circuit is electrically connected to the push-down terminal to increase a voltage on the push-down terminal in response to a signal on a first input of the second voltage increasing circuit; Increasing the degree of voltage increase on the push-down terminal in response to a signal at the second input of the second voltage increase circuit.