JP3065181B2 - Multi-chip module - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip module in which a plurality of semiconductor devices are connected and mounted.

[0002]

2. Description of the Related Art Conventionally, a multi-chip module used for an optical sensor or the like is composed of a plurality of identical sensor chips 9101 to 9108, as shown in a schematic configuration diagram of FIG.

In the figure, reference numeral 9001 denotes a scanning circuit; 9003, a temporary storage capacitor (C _T ) for storing the output of an optical sensor;
Reference numeral 2 denotes a switch (SW) scanned by 9001 for performing capacitance division from the C _T 9003 to the input of the common output line 9006 in the chip and the input of the output amplifier 9004.

An output amplifier 9004 of the chip 9101 has an A-fold gain. Reference numeral 9009 denotes a chip output bonding pad, which is the output (901) of each chip.
9 is connected via an off-chip common output line 9201.

The operation of the conventional example is briefly described as follows.

(Read Operation) Optical Sensor (Photo Tr
(Transistor), Photo Di (diode) et
c. ) The signal output from 9060 is sampled and held in C _T 9003 corresponding to each bit.

(Output Operation) Thereafter, the scanning circuit 900
1 is operated, and the switch (SW) 9002 is sequentially turned on to sequentially input signals accumulated in the C _T 9003 in the chip 9101 to the amplifier 9004 via the common output line 9006 in the chip. At that time, S for chip output
W9007 is always conducting. Further, it is needless to say that it is necessary to reset the common output line 9006 in the chip by using other SW means before turning on the SW9002. In addition, S of another chip corresponding to SW9007
W9017 and the like are in a non-conductive state, and it goes without saying that the scanning circuit 9011 and the like corresponding to 9001 are not operating.

As described above, the signal output from the amplifier 9004 passes through the inter-chip bonding pad 9009 and the module output 92 via the common output line 9201.
02 is sequentially output. After the scanning circuit 9001 scans each SW 9002 in this manner, the adjacent chip 9
The scanning signal from the scanning circuit 9001 is passed to 102, and the scanning circuit 9011 of the next chip starts scanning.
At that time, the output switch 9007 of the chip 9101 is turned off, and
017 becomes conductive.

As described above, at the time of output from the multi-chip module, the signal on the common output line 9201 is amplified by amplifiers such as 9004, 9014...

[0010]

However, as described above, in the conventional multi-chip module,
Since the output line is driven using the built-in amplifier of each chip, the offset of the amplifier of each chip is shifted.

In particular, since the amplifier requires a high-impedance input, a MOS input amplifier is often used, and the noise level (offset variation) is eight.
This is about 0 mV, and there is a problem that the S / N of the multichip module is greatly deteriorated.

There are also two problems in terms of cost as described below.

Since a large capacitance (100 pF or more) is generated in the common output line 9201 in FIG. 5, the built-in amplifier needs to have a bipolar output, and the manufacturing process of such a semiconductor device is a process in which analog bipolar and MOS are mixed. And the process cost is high.

Since an amplifier is built in each chip, it is easy to reach the limit of chip size reduction, and it is difficult to reduce the cost per chip.

[0015]

According to the present invention, the above problems can be solved by the following means.

The amplifier built in each chip is removed.

The capacitance division is performed directly on the common output line from the temporary storage capacitance (C _T ).

The amplifier is mounted as another chip in the module, and the output of the common output line is amplified.

[0019]

By providing the above three points, it is possible to improve the following three points in the multi-chip module.

· Prevents deterioration of S / N due to offset variation, · CMOS + NPN which is simpler than bipolar-MOS mixed (analog bipolar + MOS) process
The process cost can be reduced, and the process cost can be reduced. By removing the built-in amplifier, the chip size can be easily reduced, and the chip unit cost can be reduced.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] FIG. 1 is a schematic diagram showing the best configuration of the present invention, and shows a multi-chip module of an optical sensor.

In the figure, reference numeral 1 101 denotes a scanning circuit of each chip (element), 2 102 denotes a temporary storage capacity of each chip, and 3 103 denotes a temporary storage capacity 2 102 of each chip. (Outside the element) MOSFET as a transfer switch (SW) to the common output line 1005, 4,104
Is a common output line (within the element) in each chip, and 1
005 and the same potential. Reference numerals 5 and 105 denote MOs for transferring SWs from the optical sensor of each chip to the temporary storage capacitor.
SFETs 6 and 106 are optical sensors (phototransistors and photodiodes) of each chip, 7 and 10
Reference numeral 7 denotes an output signal line of a scanning start signal of a scanning circuit of a chip next to each chip, and reference numerals 8 and 108 denote common output lines 4 and 104 and an external common output line 100 in each chip.
Reference numeral 9 denotes a bonding pad which is the output of each chip, and reference numeral 10 denotes a bonding pad which is an output of each chip.
01 is a clock for synchronizing each chip, 1002 is a synchronizing signal (SP) for synchronizing each chip, and 1003 is an amplifier for amplifying a signal output from each chip. , 1004 are fixed power supply lines for resetting the common output lines 4 and 104 in each chip.

2001, 2002, 2003, 2004
Is a semiconductor chip mainly constituting a multi-chip module.

Reference numeral 1005 denotes an external common output line for connecting the output of each chip, and reference numeral 1006 denotes a capacitance associated with 1005.

Next, the operation of the first embodiment will be described.

The signal corresponding to the charges accumulated in the photosensor 6,106 is charged into a temporary storage capacitor via the SW of 5,105 2,102 (hereinafter referred to as C _T). At this time, SW of 5 and 105 are simultaneously opened and closed at a timing uniquely determined by the synchronization signal 1002 and a clock 1001, the C _T, photosensor output of each bit at the same time is stored.

The operation of the scanning circuit is the same as that of the conventional one.
Scanning is sequentially performed from 1 to the final chip 2004, and accordingly, signals are sequentially transferred from C _T (temporary storage capacity) 2, 102 to common output lines 4, 104, and 1005 (hereinafter referred to as C _X ). Then, opening and closing of the transfer SWs 3 and 103 (hereinafter referred to as SW) are performed.

At this time, although the optical sensors 6 and 106 are optical sensors, other analog signal sources may be used.

Next, the S / N improvement of the present invention will be calculated.

[0030] Compared to prior art, since until C _T are identical output, comparing the C _T subsequent S / N.

In the present invention, N = 6 · √ (kT / C) · AN: random noise when resetting _CX

[0032]

(Equation 1) In the conventional example, N = offset · A ′ offset: input conversion offset of amplifier C _H : capacitance on common output line 9006 in chip in FIG. Here, the random noise PP value was assumed to be 6 · √ (kT / C).

[0033] Suppose that C _T = C _H = (1/30) C _X and C _T = 50p
Assuming that F, √ (kT / C _X ) = 5.3 μV, It can be seen that the S / N equivalent to that of the amplifier having the amplifier offset of 0.49 mV is achieved, and the effect of the improvement is extremely large. [Second Embodiment] FIG. 2 shows a second embodiment according to the present invention.

In the first embodiment, the output amplifier 10
03 is a gain enough to cover the signal attenuated by the capacitance division ratio C _T / (C _T + C _X ), that is, about 30 to 100.
It is necessary to use the one that is about 0 times.
When the gain becomes high because the GB product is constant in the amplifier, the speed of the amplifier becomes a problem.
It becomes about 5 V / μsec.

For this reason, the improvement in the scanning speed has leveled off, and when high-speed scanning is desired, it is necessary to mount an expensive OP-amplifier.

For this reason, it is possible to reduce C _X from C _T to C
_It is necessary to divide the capacity into _X.

For this purpose, in FIG. 2, SW10 is provided in the chip 2001 and SW110 is provided in the chip 2002. The SW10 is made conductive only during the operation of the chip 2001, and the SW110 is made conductive only during the operation of the chip 2002.

That is, C _T via the chip selection SW
In the second embodiment, the capacity is divided from Cx to _CX .

In the first embodiment, C _X is given by: C _X = (Junction capacitance of SW) × (bit number of one chip) × (number of chips) + (wiring capacitance of module) In the embodiment of the present invention, C _X = (junction capacitance of SW) × (bit number of one chip) + (wiring capacitance of module), and the greater the number of multi-chips connected to the common output line, the greater the improvement. Expected.

In FIG. 2, the other parts are the same as in FIG.
Illustration and description are omitted.

[Third Embodiment] FIG. 3 shows a third embodiment of the present invention.

In the first embodiment, when the capacitance is divided from C _T to C _X , the fixed power line 1 is
It is needless to say that the common output line is reset to the reset potential specified by 004.
03 also changes according to the reset potential. As described above, when the output amplifier has a high gain, the fixed power supply line 100
There is a high possibility that the potential of D.4 will be out of the D-range of the output amplifier, which may lead to unstable operation of the amplifier.

Therefore, by providing a sample and hold circuit at the input stage of the amplifier 1003 as shown by 1008 in FIG. 3, only the signal component is output, and the stable operation of the amplifier 1003 is realized.

The other parts in FIG. 3 are the same as those in FIG.

[Fourth Embodiment] FIG. 4 shows a fourth embodiment of the present invention.

As described in the third embodiment, the output amplifier 1
003 can be a very large gain. Therefore, the gain variation of the C _T for each chip capacitive division
An error may occur.

The capacitance value of C _T is in between the chips be uniform within the chip, is considered a variation of the process control value, deteriorating the S / N of the multi-chip module becomes a gain error of capacitance division.

[0048] Therefore MAX in common to each chip in the fourth embodiment, respectively applied to the C _T with the potential 1401 and 1402 of the MIN, by performing the same capacitance division and normal signal, to the common output line 1105,1205 M of each chip
The output of AX and MIN can be reflected, and by inputting it to the AGC amplifier, the gain of each chip is corrected. FIG. 4 will be briefly described below.

[Read Operation] The signal generated in the optical sensor 6 is temporarily stored in C _T 2 by turning on the switch SW5.

[0050] At the same time, MAX value on the C _T, MI
By making the SW value 45 and 55 conductive, the N value becomes MAX.
Potential line 1401 → bonding pad 46 → SW45 →
The capacitor 44 and the MIN potential line 1402 → bonding pad 56 → SW55 → capacitor 54 are sampled and held by the capacitor 44 (referred to as C _{T MAX} ) and the capacitor 54 (referred to as C _{T MIN} ).

Although this operation is performed simultaneously for each chip as described above, it may be performed any time before the chip is scanned.

[Output Operation] As described above, the output is performed by the scanning circuit 1. At the same time when the chip to be scanned starts its scanning, the SWs 43, 53 and 10, 4 are output.
1 and 51 are rendered conductive, C _{T MAX} than capacitors 41 and M
The AX output line 1105 is divided into capacitors. C _T
Similarly, for _MIN , capacitance division is performed on the capacitor 51 and the MIN output line 1205.

[0053] In this case, MAX output line from C capacitive division gain from _T to the common output line 1005, and C _{T MAX} 110
Capacitance division gain to 5 and C _{T MIN} to MIN output line 1
All of the capacitance division gains to 205 must be the same.

Therefore, for example, C _T = C _{T MAX} = C _{T
When MIN} is set, the capacitance associated with the output line 4 in the chip = C42
= C52, and the capacity of the common output line 1005 = the capacity of the MAX output line 1105 = the capacity of the MIN output line 1205.

Thereafter, the sample and hold circuits 1106 and 1206 use the MA after the capacitance division of the chip.
Sample and hold the X value and MIN value, and
After the gain is corrected by the GC amplifier, it is amplified by the output amplifier 1003 and output.

In FIG. 4, the other parts are the same as in FIG.
Illustration and description are omitted.

[0057]

As described above, the present invention in the multi-chip module has the following effects.

Improvement of output S / N The noise level is improved by one digit or more by eliminating the output amplifier of each chip, eliminating the deterioration of the noise level due to the offset of each chip, and adopting the output form by simple capacitance division. It is possible to improve S / N.

Realization of low cost -1 The process is changed from (analog + CMOS) to (CM
By shifting to (OS + NPN), the number of masks can be reduced, the process steps can be simplified, and the process cost can be reduced.

-2 By eliminating components such as amplifiers from the chip, the chip area can be easily reduced, and the chip price can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a schematic configuration diagram showing a second embodiment of the present invention.

FIG. 3 is a schematic configuration diagram showing a third embodiment of the present invention.

FIG. 4 is a schematic configuration diagram showing a fourth embodiment of the present invention.

FIG. 5 is a schematic configuration diagram showing a conventional example.

[Explanation of symbols]

1,101 Scanning circuit of each chip, 2,102 Temporary storage capacity of each chip, 3,103 MOSFET as transfer switch (SW) from temporary storage capacity 2,102 of each chip to common output line 1005 4,104 Common output line of each chip (within the element) 5,105 MOSFET which is a SW for transferring from the optical sensor of each chip to the temporary storage capacitor, 6,106 Optical sensor (phototransistor of each chip) 7, 107) An output signal line of a scanning start signal of a scanning circuit of a chip next to each chip, 8, 107 A switch SW for resetting common output lines 4, 104, and 1005 of each chip, 8, 9, 109 Bonding pad at the output of each chip, 1001 Clock for synchronizing with each chip 1002, a synchronization signal (SP) for synchronizing each chip; 1003, an amplifier for amplifying a signal output from each chip; 1004, a fixed power supply line for resetting a common output line 4, 104 of each chip. 1005 common output line (outside the element) of each chip; 1006 capacitance associated with common output line 1005 of each chip; 2001, 2002, 2003, 2004 semiconductor chips mainly constituting a multi-chip module;

Claims (4)

(57) [Claims] 1. A multi-chip module in which a plurality of semiconductor elements are connected and mounted, wherein each of the plurality of semiconductor elements includes a plurality of optical sensors.
And a plurality of cells for holding signals from the plurality of optical sensors.
And capacitors signal storage capacitor, and the element in the common output line to which a signal is output from the plurality of sensors signal storage capacitor, said plurality of
A signal from the sensor signal storage capacitor is output to the common output line within the element.
And a scanning circuit for outputting to the device in a common output line and connected to elements outside the cell of the plurality of semiconductor elements
Multichip module comprising: the capacitors signal common output line, and a amplifier element for amplifying enter the signal of the first element out of the sensor signal common output line. 2. The semiconductor device according to claim 1, further comprising: switch means for selecting an output of the plurality of semiconductor elements, wherein only the active elements are connected to the first semiconductor element .
The multi-chip module according to claim 1, wherein the multi-chip module is connected to a common output line outside the element. 3. The multi-chip module according to claim 1, further comprising a sample- and- hold circuit preceding said amplifier element, wherein only a signal component is input to said amplifier means. 4. A first potential and a first potential applied to each element.
A potential supply means for supplying a second potential different from the potential, and a potential supply means provided by the potential supply means included in each element.
A first storage capacitor charged by the first potential
When the contained in each element, the supply of the said potential supplying means
Second storage capacitor charged by the second potential
And the second signal from which the charged signal of the first storage capacitor is read out.
A first external signal common output line and a second signal from which the charged signal of the second storage capacitor is read.
2 and the potential of the first external signal common output line and the second element common output line.
The amplification factor determined by the potential of the external signal common output line
AGC that amplifies the signal on the common output line for sensor signal outside the element
Further comprising an amplifier, wherein the amplifier element child amplifies the output of the AGC amplifier
The multi-chip module according to claim 1, wherein
Le.