JP3064029B2 - Pulse width measurement circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse width measuring circuit, and more particularly to a pulse width measuring circuit for continuously measuring one cycle width of a measured input pulse. In recent years, various devices for detecting a certain detected value (for example, a physical quantity) by replacing the detected value with a pulse width of a pulse signal have been disclosed. This type of device is variously controlled based on a microcomputer, and a reduction in size and weight of this device is also desired. Therefore, there is a demand for a smaller IC chip and a smaller program amount.

[0002]

2. Description of the Related Art Conventionally, when a pulse width of one cycle (from the rising edge to the next rising edge or from the falling edge to the next falling edge) is continuously measured, the timing of the end of the pulse width measurement is determined. Since the next pulse measurement starts at the same time,
It is very difficult to control the timing for clearing the counter, the timing for transferring the count value (measured value) to the data buffer, and the like. Therefore, as shown in FIG.
A pulse width measurement circuit provided with two counters has been proposed.

In this pulse width measuring circuit, as shown in FIG. 9, an edge detecting circuit 60 receives a measured input pulse signal PS, detects a rising edge of the measured input pulse signal PS, and counts the detected edge signal. Output to the hook generation circuit 61 and the CPU 62. The count clock generation circuit 61 receives the basic clock signal CLK, and inputs the clock signal CLK to one of the counters 63 and 64 based on the edge detection signal. The CPU 62 controls the counters 63 and 64 by program. The CPU 62 alternately counts the counters 63 and 64 to which the clock signal CLK is input based on the edge detection signal from the edge detection circuit 60.
As shown in (1), the counter that has performed the counting operation of the pulse width for one cycle of the input pulse signal under measurement PS is terminated, and the counter for the next one cycle of the input pulse signal under measurement PS is stopped with respect to the other counter. Start counting the pulse width. Then, the pulse width of one cycle of the measured input pulse signal PS is continuously measured by reading the values CONT1 and CONT2 counted by the counters 63 and 64 alternately.

[0004]

However, in the conventional pulse width measuring circuit, the counters 63 and 64 have two counters.
This requires a large number of devices, which causes a problem of an increase in circuit scale. In addition, the CPU 62 determines that these two counters 63, 6
Thus, the control program amount is increased by the amount corresponding to the control of No. 4, and a heavy load is imposed on the control by software.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problem, and an object of the present invention is to enable a single counter to continuously measure the pulse width of one cycle, thereby reducing the circuit scale. It is another object of the present invention to provide a pulse width measuring circuit capable of reducing the burden of control by software.

[0006]

FIG. 1 is a principle diagram for explaining the principle of the present invention. An edge detection circuit 1 receives two-phase basic clock signals φ1 and φ2 and receives an input pulse PS under test PS1. Enter Two-phase basic clock φ1,
As shown in FIG. 2, φ2 is a clock signal having the same cycle shorter than the cycle of the input pulse signal under test PS, and the phases are shifted so as not to overlap each other. The edge detection circuit 1 outputs a one-shot pulse signal A when detecting the rising of the input pulse under test PS with the rising signal of the clock pulse φ1, and detects the rising of the input pulse PS under test with the clock pulse φ2. When detected, a one-shot pulse signal B is output.

The counter control circuit 2 is constituted by a flip-flop circuit and receives timing signals A and B output from the edge detection circuit 1. Counter control circuit 2
Outputs a count enable signal CE that falls from the H level to the L level based on the rising of the timing signal A and rises from the L level to the H level based on the rising signal of the timing signal B as a counter control signal.

The counter circuit 3 inputs the count enable signal CE and the count clock signal CLK, and when the count enable signal CE rises to the H level,
The contents are reset, and the count clock signal CLK is counted while the signal CE is at the H level. When the count enable signal CE falls to the L level, the counter circuit 3 stops counting the count clock signal CLK and outputs the count value CONT at that time.

[0009]

Each time the input pulse under test PS rises, the edge detection circuit 1 generates two pulse signals A and B having different phases and shifted in phase in response to the rise of the pulse PS. Then, the counter control circuit 2 uses the two pulse signals A and B each time the input pulse under measurement PS rises (each cycle of the input pulse under measurement) from the H level for a certain period, that is, the timing signals A and B.
The count enable signal CE which falls to the L level by the phase difference of B and rises to the H level again is output.

The counter circuit 3 stops the counting operation while the count enable signal CE is at the L level, outputs the count value CONT of the pulse width of the input pulse PS to be measured in one cycle this time, and resets it. In preparation for the counting operation of the pulse width of the input pulse under measurement PS in the next one cycle. Therefore, the counter circuit 3 can continuously count the pulse width of one cycle in the input pulse under measurement PS.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the pulse width measuring circuit according to the present invention will be described below with reference to the drawings. FIG. 3 is a block diagram illustrating the outline of the pulse width measurement circuit. The edge detection circuit 10 includes basic clock signals φ1 and φ2 whose phases do not overlap each other and whose phases are shifted from each other, and their complementary signals (hereinafter referred to as inverted basic clock signals). ) Input φ1X and φ2X, and input the input pulse PS to be measured. As shown in FIG. 4, the edge detection circuit 10 includes five clocked latch circuits 11 to 15 connected in series, and an input pulse P to be measured is applied to a data input terminal D of a first-stage clocked latch circuit 11.
S is input. The first-stage, third-stage, and last-stage clocked latch circuits 11, 13, and 15 are configured such that one of the basic clock signals φ1 is input to a clock input terminal C, and the inverted basic clock signal φ1X is input to an inverted clock input terminal CX. It has become. On the other hand, the second and fourth clocked latch circuits 12 and 14 are configured such that the other basic clock signal φ2 is input to the clock input terminal C and the inverted basic clock signal φ2X is input to the inverted clock input terminal CX. I have.

The first-stage clocked latch circuit 11 inverts the input pulse under test PS from L level to H level and changes the basic clock signal φ1 at that time from H level or L level to H level (inverted basic clock signal φ1X Is L
Level or from the H level to the L level), output an H level output signal Q1 from the output terminal Q,
The output signal Q1 at the H level is held unless the input pulse under measurement PS is inverted to the L level. The second-stage clocked latch circuit 12 latches the H level of the input pulse under test PS and outputs the output signal Q of the first-stage clocked latch circuit 11.
1 is inverted from the L level to the H level, and when the other basic clock signal φ2 changes from the H level or the L level to the H level after the basic clock signal φ1 at that time (when the inverted basic clock signal φ2X is the L level or the H level). Output signal Q2 from the output terminal Q, and the output signal Q
2 is held unless the output signal Q1 is inverted to L level.

When the output signal Q2 is inverted to H level, the third stage clocked latch circuit 13 outputs the H level output signal Q3 from the output terminal Q when the basic clock signal φ1 at that time is inverted to H level or H level. At the same time, the output signal Q3 at the H level is held unless the output signal Q2 is inverted to the L level. When the output signal Q3 is inverted to H level and the basic clock signal φ2 at that time is inverted to H level or H level, the fourth stage clocked latch circuit 14 outputs an H level output signal Q4 from the output terminal Q and , Its H level output signal Q4
As long as the output signal Q3 is not inverted to the L level. When the output signal Q4 is inverted to H level, the final stage clocked latch circuit 15 outputs an H level output signal Q5 from the output terminal Q when the basic clock signal φ1 at that time is inverted to H level or H level. At the same time, the output signal Q5 at the H level is held unless the output signal Q4 is inverted to the L level.

Therefore, as shown in FIG. 5, the output signal Q1 of the first-stage clocked latch circuit 11 is
On the other hand, the output signals Q2 to Q5 of the clocked latch circuits 12 to 15 each have an output waveform with a predetermined phase delay with respect to the output signal of the preceding stage. And the third stage, 4
Output signals Q3 to Q5 of the first and last stage clocked latch circuits 13 to 15 are output to the logic gate circuit. The logic gate circuit includes four knot circuits 16 to 19, two NAND circuits 20 and 21, and two NOR circuits 22 and 23.

The NAND circuit 20 outputs the output signal Q
3 and an output signal Q4 via a knot circuit 16. Therefore, the output signal A of the NAND circuit 20 is the output signal Q
3 is at the L level only from when the signal 3 is inverted to the H level until the output signal Q4 is inverted to the H level. The other NAND circuit 21 receives the output signal Q4 and the output signal Q5 via the knot circuit 17. Therefore, the output signal B of the NAND circuit 21 is at the L level only from when the output signal Q4 is inverted to the H level to when the output signal Q5 is inverted to the H level.

On the other hand, the NOR circuit 22 outputs the output signal Q3
And the output signal Q4 is input via the knot circuit 16, and the output signal is output to the knot circuit 18 in the next stage. Therefore, the output signal C output from the knot circuit 18 is at the L level only from when the output signal Q3 is inverted to the L level to when the output signal Q4 is inverted to the L level. The other NOR circuit 23 outputs the output signal Q4 and the knot circuit 17
, And outputs the output signal to the knot circuit 19 at the next stage. Therefore, this knot circuit 1
The output signal D of No. 9 is at the L level only from when the output signal Q4 is inverted to the L level until the output signal Q5 is inverted to the L level.

Accordingly, the output signal A of the NAND circuit 20
Outputs an L-level signal in response to the rising edge of the measured input pulse PS, although there is a phase delay with respect to the measured input pulse PS. Also, the NAND circuit 21
The output signal B outputs an L level signal at the same time as the output signal A rises from the L level to the H level. That is, the edge detection circuit 10 detects the rising of the input pulse PS to be measured at each time by the two output signals A and B having different phases.

On the other hand, although the output signal C of the NOR circuit 22 also has a phase delay with respect to the measured input pulse PS, it outputs an L-level signal in response to the falling edge of the measured input pulse PS. The output signal D of the NOR circuit 23 outputs an L level signal at the same time when the output signal C rises from the L level to the H level. That is, in the edge detection circuit 10, the input pulse PS to be measured at each time is output by the two output signals C and D having different phases.
Is detected.

The output signals A to A of the edge detection circuit 10
D is output to the selection circuit 30. As shown in FIG. 6, the selection circuit 30 includes an exclusive NOR circuit 31, two knot circuits 32, 33, four AND circuits 34 to 37,
NOR circuits 38, 39 and two NAND circuits 30a,
30b. The exclusive NOR circuit 31 receives 2-bit mode selection signals W0 and W1. The mode selection signals W0 and W1 are output signals A and B that respond to the rise of the input pulse under test PS or the output signals C and C that respond to the fall among the output signals A to D.
A signal for selecting one of the groups D.
When the mode selection signals W0 and W1 are "L, H", the output signals A and B become code signals for selecting the output signals C and D when the mode selection signals W0 and W1 are "H, H". I have.

The AND circuit 34 receives the output signal D and the mode selection signal W0 and outputs the output signal to the NOR circuit 3.
8 is output. The AND circuit 35 outputs the output signal B
And a mode selection signal W0 via the NOT circuit 32, and outputs its output to the NOR circuit 38. Therefore, when the mode selection signal W0 is "H", the output signal D is selected,
An L-level output signal D responsive to the rising edge of the input pulse under test PS is output. Conversely, when the mode selection signal W0 is "L", the output signal B is selected, and an L-level output signal B responsive to the falling edge of the measured input pulse PS is output.

The AND circuit 36 receives the output signal C and an output signal from the exclusive NOR circuit 31, and
The output signal is output to the NOR circuit 39. The AND circuit 37 receives the output signal A and the output signal from the exclusive NOR circuit 31 via the NOT circuit 33 and outputs the output to the NOR circuit 39. Therefore, when the mode selection signals W0 and W1 are "H, H", the output signal C is selected, and the L-level output signal C is output in response to the rise of the input pulse PS to be measured. Conversely, when the mode selection signals W0 and W1 are "L, H", the output signal A is selected, and the L-level output signal A is output in response to the falling edge of the input pulse PS to be measured. The signal (output signal B or output signal D) output from the NOR circuit 38 of the selection circuit 30 is output to the NAND circuit 30a. The NAND circuit 30a receives the basic clock signal φ2, and when the basic clock signal φ2 is at the H level,
Only when the signal output from the NOR circuit 38 is at an H level, an L-level start signal STX is output to a flip-flop circuit 40 as a control circuit at the next stage. The signal (output signal A or output signal C) output from the NOR circuit 39 is output to the NAND circuit 30b. NAND circuit 30
b is be adapted to enter the basic clock signal .phi.1, next basic clock signal .phi.1 is H level, an end signal ENX of L level only when the signal output from the NOR circuit 39 is at H level It outputs to the flip-flop circuit 40 as the counter control circuit of the stage. That is,
In the NAND circuits 30a and 30b, the basic clock signals φ1 and φ2 are added to slightly shorten the active pulse width so as to avoid competition between the set signal and the reset signal of the flip-flop circuit 40 in the next stage.

As shown in FIG. 7, a flip-flop circuit 40 as a counter control circuit has two NAND circuits 41,
42 and one knot circuit 43. The NAND circuit 41 receives the output of the other NAND circuit 42 and the start signal STX. The other NAND circuit 42 receives the output of one NAND circuit 41 and the end signal ENX. Also,
The output of the NAND circuit 42 is output to a NOT circuit 43, and the output of the NOT circuit 43 is output as a count enable signal CE. Then, the NAND circuit 41 outputs L
When the level start signal STX (output signal B or output signal D) is input, the flip-flop circuit 40 is set, and the count enable signal CE goes high.
Then, the L-level end signal ENX is supplied to the NAND circuit 42.
When (the output signal A or the output signal D) is input, the flip-flop circuit 40 is reset, and the count enable signal CE changes from the H level to the L level. Accordingly, the count enable signal CE outputs an H level signal only from the time when the start signal STX falls to the L level to the time when the end signal ENX falls, that is, the flip-flop circuit 40 outputs the same signal as the measured input pulse PS. H in the cycle
A level count enable signal CE is output.

The count enable signal CE of the flip-flop circuit 40 is output to the count clock generation circuit 50. The count clock generation circuit 50 receives the basic clock signal φ1 and its inverted basic clock signal φ1X, and receives the count enable signal CE. When the count enable signal CE is at the H level, the basic clock signal φ1 is frequency-divided, and based on the frequency-divided signal, non-overlapping non-overlapping count clock signals C1 and C2 which are not overlapped with each other are generated. To the counter 51.
Conversely, when the count enable signal CE is at the L level, the generation of the count clock signals C1 and C2 is stopped, and the output to the counter 51 at the next stage is stopped.

The counter 51 is a synchronous down counter, and counts down the count clock signals C1 and C2 based on the count enable signal CE and the count clock signals C1 and C2. The counter 51 is shown in FIG.
When the count enable signal CE falls to the L level, the count operation is stopped and the count value CONT at that time is output to the next-stage measured value storage memory 52, and the count enable signal CE changes from the L level to the H level. When the count value CONT is set to "FF (B
CD code) "to enable the subtraction operation. Then, the counter 51 outputs the count enable signal C
When E is at the H level, the count clock signal C1 is input to perform a subtraction operation, and the operation result (count value CONT) is stored in a buffer provided inside the counter circuit 51 based on the next input count clock signal C2. Forward.
Accordingly, the counter 51 decrements the count value CONT by "1" in accordance with the two count clock signals C1 and C2 which do not overlap with each other and whose phases are shifted.

Next, the operation of the pulse width measuring circuit configured as described above will be described. For convenience of explanation, the selection circuit 30 receives the mode selection signals W0 and W1 of "L, H", selects the output signals A and B in response to the rise of the input pulse PS to be measured, and selects the same input pulse PS. Will be described. Now
When the measured input pulse PS is input, the edge detection circuit 10 outputs an L level in response to the rising of the measured input pulse PS at each time based on the basic clock signals φ1 and φ2 and the inverted basic clock signals φ1X and φ2X. At the same time as the signal A and the output signal A rising from the L level to the H level , the output signal B which becomes the L level is output. Also,
The edge detection circuit 10 detects the input pulse PS
Output signal C of the same output signal C in response to the falling to the L level and outputs the output signal D of the same time L level rises from L level to H level. That is, the edge detection circuit 10 outputs a given time of the output signals A to D in response to the rising edge of the measured input pulse PS.

Then, the selection circuit 30 selects the output signal A and the output signal B which become L level in response to the rise of the input pulse PS to be measured among the output signal signals A to D,
The output signal A and the end signal E are used as the start signal STX.
The output signal B is output to the flip-flop circuit 40 as NX. The flip-flop circuit 40 is set in response to the L level start signal STX (output signal B), and the count enable signal CE is inverted to H level. Subsequently, the flip-flop circuit 40 is reset in response to the input end signal ENX (output signal A), and the count enable signal CE changes from H level to L level. Accordingly, the flip-flop circuit 40 outputs the count enable signal CE at the H level only from the time when the start signal STX falls to the L level to the time when the end signal ENX falls, that is, the H level at the same cycle as the input pulse PS to be measured. Is output.

The count clock generation circuit 50 at the next stage is based on the count enable signal CE which goes high at the same period as the input pulse PS to be measured, and only while the count enable signal CE is high.
1 and C2 are output to the counter 51 at the next stage. Similarly, the counter 51 outputs the count enable signal C which goes high.
A subtraction counting operation is performed based on E and the count clock signals C1 and C2. At this time, when the count enable signal CE falls to the L level, the counter 51 stops the counting operation and outputs the subtracted count value CONT up to that time to the measured value storage memory 52 at the next stage. Then, when the count enable signal CE rises from the L level to the H level, the counter 51 resets the count value CONT to enable a subtraction operation and starts the next subtraction operation. That is, the counter 51 outputs the count enable signal CE.
Measured value storage memory 52 based on the L level inversion operation of
The value CONT obtained by counting one cycle of the measured input pulse PS at that time by the count clock signals C1 and C2 (the value of the width of one cycle of the current measured input pulse PS) is transferred. Then, based on the inversion operation of the count enable signal CE at the H level, the count of the width of one cycle of the next measured input pulse PS is immediately counted.

As described above, in this embodiment, the counter 51 stores the current measured input pulse PS in the measured value storage memory 52 based on the count enable signal CE output in response to the rising edge of the measured input pulse PS. Is transferred, and the count of the width of one cycle of the next input pulse to be measured PS is counted immediately, so that this one counter 51
The pulse width of each period can be counted continuously. Therefore, since the pulse width of each cycle of the input pulse under measurement PS can be counted continuously by one counter 51, the circuit scale can be reduced, and the pulse width measuring circuit can be reduced by one. C to control
The amount of PU control programs can be reduced, and the load on software control can be reduced.

In this embodiment, the measured input pulse PS
Is described from the rising edge to the next rising edge, but it is of course possible to measure from the falling edge of the measured input pulse PS to the next falling edge. Further, the measurement may be performed so as to measure from the rising to the falling of the input pulse under measurement PS, or to measure the opposite from the falling to the rising.

In the above embodiment, the synchronous subtraction counter 51 is used. However, the counter may be implemented by another counter such as an addition counter.

[0031]

As described in detail above, according to the present invention, 1
The pulse width of one cycle can be continuously measured by the number of counters, so that the circuit scale can be reduced, and the load of control by software can be reduced.

[Brief description of the drawings]

FIG. 1 is a principle explanatory diagram for explaining the principle of a pulse width measurement circuit according to the present invention.

FIG. 2 is a time chart for explaining the operation of the pulse width measurement circuit.

FIG. 3 is an electric block circuit diagram of a pulse width measurement circuit for explaining an embodiment embodying the present invention;

FIG. 4 is an electric block circuit diagram illustrating a configuration of an edge detection circuit.

FIG. 5 is a time chart for explaining the operation of the edge detection circuit.

FIG. 6 is an electric block circuit diagram illustrating a configuration of a selection circuit.

FIG. 7 is an electric block circuit diagram illustrating a configuration of a flip-flop circuit.

FIG. 8 is a time chart for explaining the operation of the counter circuit.

FIG. 9 is a circuit diagram of a conventional pulse width measurement circuit.

FIG. 10 is a time chart for explaining the operation of a counter used in a conventional pulse width measurement circuit.

[Explanation of symbols]

 1 Edge detection circuit 2 Counter control circuit, 3 Counter circuit, A and B output signal, CE count enable signal, CLK count clock signal, CONT count value, PS Input pulse signal to be measured, φ1, φ2 basic clock signal.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-52-142545 (JP, A) JP-A-60-111971 (JP, A) Real-life Japanese Utility Model Showa 60-11079 (JP, U) (58) Field (Int.Cl. ⁷ , DB name) G01R 29/02 G01R 23/10

Claims (1)

(57) [Claims] An input pulse signal to be measured (PS) and two-phase basic clock signals (φ1, φ2) having different phases are input and respond to at least one of the rise and fall of the input pulse signal to be measured PS. An edge detection circuit (1) for outputting two one-shot pulse signals (A, B) having different phases, and the two one-shot pulse signals (A, B) having different phases are inputted, and one one-shot pulse Inverted in response to the signal (A), inverted and returned in response to the other one-shot pulse signal (B), and returned in response to at least one of the rise and fall of the measured input pulse signal PS. Shot pulse signals (A,
B) The counter control signal (C
E), a counter control circuit (2), the counter control signal (CE), and a count clock signal (CLK).
Is input, the count operation is stopped by inversion of the counter control signal (CE), and the count content (CONT) is output.
A pulse width measuring circuit comprising: a counter circuit (3) for resetting the count content (CONT) at the next inversion return and starting the count operation of the count clock signal (CLK).