JP3062184B1 - Arithmetic processing method of PLL circuit and logic simulation method using the same - Google Patents

Abstract

Abstract: [Object] An arithmetic processing method of a PLL circuit capable of improving work efficiency, obtaining a high-accuracy result in a short calculation time, and performing synchronous / asynchronous simulation when used in an arithmetic processing of a logic simulation. I will provide a. If an additional delay value tc corresponding to a phase difference between a reference clock signal RCLK and a feedback clock signal CLKI is not set, a predetermined standard delay value ta is set as a delay time td, and an output clock is generated using the delay time td. Generate a change in signal CLKO. Then, the change times of the reference clock signal CLKI and the feedback clock signal CLKI are checked, and the difference between the change times is set as the additional delay value tc. A value obtained by adding the standard delay value ta to the additional delay value tc is used as a delay time td, and a change in the output clock signal CLKO is generated using the delay time td. The change in the generated output clock signal CLKO is used as a calculation processing result.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a simulation of a PLL circuit.
It relates Configuration method and logic simulation method using the same and, more, using the same and simulation method Contact <br/> of PLL circuit used for simulating a logic circuit having a PLL circuit by the event-driven method logic Related to the simulation method.

[0002]

2. Description of the Related Art In recent years, an event driven method has been generally used as a logic simulation method. In the event-driven method, a change in a signal in a logic circuit is called an event, and a logic simulation of the logic circuit is performed based on the event.
That is, when an event occurs at a designated time (hereinafter, referred to as a current time), a circuit cell (for example, AND, OR, flip-flop, etc.) of which input signal changes due to the event from among the circuit cells constituting the logic circuit And an operation calculation (hereinafter referred to as operation processing) is performed only on the specified circuit cell. The arithmetic processing is executed by using arithmetic means (hereinafter referred to as a simulation model, hereinafter simply referred to as a model) in which the operation of the circuit cell is defined. When the output signal of the target circuit cell changes as a result of the arithmetic processing, the change of the output signal is regarded as a new event. The occurrence time of the new event (that is, the change time of the output signal) is set to a time delayed from the current time by a predetermined delay time of the circuit cell. Then, the new event is registered at the set occurrence time. By repeating such a procedure while advancing the current time, the entire logic circuit is subjected to logic simulation.

In general, a large-scale logic circuit has a PLL (Phase Loose Lock) for suppressing clock skew.
cked Loop (phase locked loop) circuit. As a method of performing a logic simulation of a logic circuit having such a PLL circuit by an event-driven method, there has been a logic simulation method using a dummy model for arithmetic processing of the PLL circuit.

The dummy model used in the conventional logic simulation method is a model corresponding to a circuit cell (a so-called delay circuit) that obtains an output signal by delaying the phase of an input signal by a predetermined delay time.

However, the conventional logic simulation method using the dummy model cannot simulate the operation peculiar to the PLL circuit.

Originally, in the PLL circuit, the phase of the output clock signal of the PLL circuit is controlled so that the input reference clock signal and the feedback clock signal fed back are always synchronized. That is, if a phase difference occurs between the reference clock signal and the feedback clock signal, the phase of the output clock signal is determined according to the phase difference. For example, when the phase of the feedback clock signal changes or when the frequency of the reference clock signal changes, the phase of the output clock signal also changes to maintain the synchronization between the reference clock signal and the feedback clock signal. The reason that the phase of the output clock signal changes in response to the feedback clock signal as described above is as follows.
This is an operation specific to the PLL circuit.

On the other hand, in the conventional simulation method using the dummy model, since the phase of the output clock signal is determined independently of the feedback clock signal, the reference clock signal and the feedback clock signal are not synchronized. Therefore, since the operation in a state where the reference clock signal and the feedback clock signal are not synchronized (hereinafter, referred to as asynchronous operation) is simulated, there is a problem that the accuracy of the simulation is deteriorated.

As another conventional logic simulation method, there is a logic simulation method in which a netlist model that directly reproduces the operation of a PLL circuit is used for arithmetic processing of the PLL circuit.

In the conventional logic simulation method using the netlist format model, the original operation of the PLL circuit is simulated. Therefore, the operation in a state where the reference clock signal and the feedback clock signal are synchronized (hereinafter, referred to as an operation). , Synchronous operation).

However, in a conventional logic simulation method using a netlist model, processing for thousands of clocks is required until a synchronous operation is reached. Therefore, there is a problem that the calculation time of the simulation increases.

As a technique for solving the above problem, there is a logic simulation method disclosed in Japanese Patent Application Laid-Open No. 9-5397.

The logic simulation method disclosed in this publication has a delay means for giving a predetermined delay time to the output clock signal. Then, a delay time between the output clock signal and the feedback clock signal is added to a predetermined delay time, and a virtual clock signal whose phase is shifted ahead of the reference clock signal by the added delay time is generated by the delay means. The simulation is performed using the virtual clock signal.

Further, this publication discloses a logic simulation method in which an output clock signal delayed by a time obtained by subtracting a predetermined delay time from a time corresponding to one cycle length of the reference clock signal is generated by the delay means. .

According to the logic simulation method disclosed in the publication, it is possible to simulate the synchronous operation by using the virtual clock signal and the output clock signal generated by the delay means.

[0015]

As described above, the PL
The conventional logic simulation method using the dummy model for the operation processing of the L circuit has a problem that the accuracy of the simulation is inferior. In the conventional logic simulation method using the model of the netlist format for the operation processing of the PLL circuit, the There is a problem that the calculation time increases.

On the other hand, the conventional logic simulation method disclosed in Japanese Patent Application Laid-Open No. 9-5397 has the following problems.

In the conventional logic simulation method of this publication, since the delay time set in the delay means is a constant value, the delay time required for the synchronous operation in accordance with a change in the configuration of the logic circuit or a change in the reference clock signal. Needs to be calculated, and the delay time needs to be reset using the calculated value. The calculation and resetting of the delay time are performed by an operator. Therefore, there is a problem that work efficiency is poor because the number of steps of the simulation work increases.

From the start of the simulation, P
Since the synchronous operation of the PLL circuit is simulated, the asynchronous operation of the PLL circuit cannot be simulated as it is. To simulate the asynchronous operation of the PLL circuit, it is necessary to change the delay time set in the delay means and perform the simulation again. Therefore, there is a problem that the synchronous operation and the asynchronous operation of the PLL circuit cannot be simulated at once.

[0019] It is an object of the present invention is to provide a sheet Myuresho <br/> it is possible to improve the efficiency of emission operations, the simulation method of the PLL circuit highly accurate result can be obtained in a short calculation time.

Another object of the present invention is to provide a method of simulating a PLL circuit capable of simulating synchronous operation and asynchronous operation of a PLL circuit at a time.

Still another object of the present invention is to provide a logic simulation method capable of improving the efficiency of a simulation operation and obtaining highly accurate results in a short calculation time.

Still another object of the present invention is to provide a logic simulation method capable of simulating synchronous operation and asynchronous operation of a PLL circuit at a time.

[0023]

Means for Solving the Problems (1) The first aspect of the present invention
PLL circuitThe simulation method is Output clock signal
Signal is fed back to the input side.
Compared with the quasi-clock signal, the feedback clock signal and the
Operate to eliminate the phase difference of the reference clock signal
The feedback clock signal to the reference clock signal.
For simulating a PLL circuit synchronized with a signal
At (A) The time when the feedback clock signal changes is set as a reference time
Set as time, (B) At a certain current time, the reference clock signal
Whether there is a rising or falling change of
Judge, (C) In (B), the reference clock signal
One of the rising and falling changes
If it is determined that there is a delay,
Set a predetermined first delay value as the interval, (D) In (B), the reference clock signal
It is determined that there is a rising or falling change.
If the connection is interrupted, the difference between the current time and the reference time is calculated.
Set as an additional delay value, and
A second delay value equal to the sum of the first delay value and the delay time
Set as (E) the delay set in (C) or (D)
The output clock is delayed by the time from the current time.
Schedule a change in the traffic light to occur Specially
Sign.

(2) Spot of the first PLL circuit of the present invention
In the modulation method, the feedback clock signal changes.
Time is set as the reference time. On the other hand, some current time
The rising edge of the reference clock signal or
Determines whether there is a falling change. And before
Rising or falling of the reference clock signal
If it is determined that there is any change,
A predetermined “first delay value” is set as the delay time. The base
Rising or falling change of the quasi-clock signal
If it is determined that the other is present, the current time and the
After setting the difference from the reference time as an additional delay value,
"Second delay value" equal to the sum of the acceleration delay value and the "first delay value"
The “extended value” is set as the delay time. And this
Is delayed from the current time by the set delay time
At a time, the output clock signal is changed so that a change occurs.
Schedule it.

As described above, in the first PLL circuit of the present invention,
In the simulation method, the feedback clock signal is changed.
From the standardized time, that is, the “reference time”,
Rise or fall of the clock signal
Calculate the time difference (ie, phase difference) up to the current time
And sets it as the “additional delay value”. And before
As the delay time, for example, the rising edge of the reference clock signal
If it is determined that there is a falling change,
Value "and set the rise of the reference clock signal.
If it is determined that there is a delay, the first delay value and the additional delay
The "second delay value" is set to be equal to the sum of the delay value. This
The output clock signal generated after the current time
The change of the signal is performed at the current time by, for example, the reference clock signal.
If it is determined that there is a falling change in the
Delay by the delay value, but the
When it is determined that there is a rising change of the quasi-clock signal
Is set to the "second delay value".
Value is delayed by "additional delay value"
You. The “additional delay value” is the current time from the “reference time”
Time difference (i.e., phase difference)
At the time delayed by the "extended value"
A phase difference between the signal and the feedback clock signal is eliminated.
That is, the feedback clock signal is synchronized with the reference clock signal.
You. Therefore, the synchronous operation and the asynchronous operation of the PLL circuit are performed.
Simultaneous work can be simulated at once.
In addition, a highly accurate simulation result is obtained. Soshi
Therefore, setting the additional delay value requires a large number of clocks (reference clocks).
Lock signal) is not required. As a result, the PLL circuit
The transition from asynchronous operation to synchronous operation is performed promptly.
And Therefore, the calculation time can be reduced.

Further, before the synchronous operation of the PLL circuit is necessary.
It is automatically calculated and set serial delay time by using the time at which each have a change in the reference clock signal and the feedback clock signal. Therefore, in the case of using the logical simulation, it is made to change the frequency of the structure changes and the reference clock signal of the logic circuit, the calculation and setting of the delay time necessary synchronous operation needs to be performed by an operator Absent. Therefore, the efficiency of the simulation operation is improved.

(3) The second PLL circuit of the present inventionStain
SimulationThe method isOutput clock signal is fed back to the input side
The obtained feedback clock signal is used as a predetermined reference clock signal.
Comparing the feedback clock signal with the reference clock signal
By operating to eliminate the phase difference of
P to synchronize the return clock signal with the reference clock signal
In a method for simulating an LL circuit, (A) The time when the feedback clock signal changes is set as a reference time
Set as time, (B) At a certain current time, the reference clock signal
Whether there is a rising or falling change of
Judge, (C) In (B), the reference clock signal
One of the rising and falling changes
If it is determined that there is a delay,
Set a predetermined first delay value as the interval, (D) In (B), the reference clock signal
It is determined that there is a rising or falling change.
If the connection is interrupted, the difference between the current time and the reference time is calculated.
Set as an additional delay value, and
A second delay value equal to the sum of the first delay value and the delay time
Set as (E) the delay set in (C) or (D)
The output clock is delayed by the time from the current time.
Schedule a change in the traffic light, (F) Whether the frequency of the reference clock signal changes
The frequency of the reference clock signal changes.
If it is determined that there is, the reference clock signal and the
Determines whether the feedback clock signal is synchronized, (G) In the above (F), the reference clock signal and
When it is determined that the feedback clock signal is synchronized
Is the current time for the delay time set in (D).
The output clock signal changes at a time delayed from the time.
Schedule like this, (H) In (F), the reference clock signal and
When it is determined that the feedback clock signal is not synchronized
The reference time set in (A) and the reference time
Clearing the additional delay value set in (D),
(C) from the current time by the delay time set in
The output clock signal changes at a delayed time. As it happens
Schedule to It is characterized by the following.

(4) Stain of the second PLL circuit of the present invention
The first method of the present invention described in the above (1)
The simulation method L circuit, corresponds to that add synchronization operation is obtained again function when synchronous operation of the feedback clock signal is the frequency of the reference clock signal changes is compromised.

That is, the first P of the present invention of the above (1)
Like the simulation method of the LL circuit, wherein
In (A) to (D), the reference time, the first delay value, the additional delay
A delay value and a second delay value are set, and in (E) above,
The delay time set in (C) or (D)
A change in the output clock signal at a time delayed from the current time
Schedule to happen. Further, the above (F)
, There is a change in the frequency of the reference clock signal
Judge whether or not the frequency of the reference clock signal changes.
If it is determined that there is a
It is determined whether the feedback clock signals are synchronized.
Then, in (F), the reference clock signal and the
If the feedback clock signal is determined to be synchronized,
Is the current time for the delay time set in (D).
The output clock signal changes at a time delayed from the time.
Schedule like this. In the above (F),
The reference clock signal and the feedback clock signal are synchronized.
If it is determined that there is no, the above-mentioned set in (A)
Click the reference time and the additional delay value set in (D) above.
The delay time set in (C).
The output clock signal changes at a time later than the current time.
Schedule for the occurrence to occur .

[0030] by, by the same reason as stated above SL (2), a synchronous operation and asynchronous operation of the PLL circuit simulation it is possible to at once, with a high accuracy of the simulation results, it is possible to shorten the calculation time In addition, the efficiency of the simulation operation is improved.

Furthermore, even if the frequency of the reference clock signal is impaired synchronous operation changes because they are re-set after the setting of the additional delay value and the reference time is once cleared (canceled), resetting Using the reference time thus set and the second delay value , a synchronous operation is obtained again. That is, there is an advantage that the present invention can be applied to a logic simulation in which the frequency of the reference clock signal is not constant.

In the conventional logic simulation method disclosed in Japanese Patent Laid-Open No. 9-5397, since the delay time set in the delay means is constant, the synchronous operation is performed only with respect to a reference clock signal having a constant frequency. Is obtained. Therefore, when the frequency of the reference clock signal changes during the logic simulation and the synchronous operation is impaired,
Synchronous operation cannot be obtained for the reference clock signal after the frequency change, and the accuracy of the simulation deteriorates. Therefore, it cannot be applied to a logic simulation in which the frequency of the reference clock signal is not constant.

(5) First and second PLLs of the present invention
In a preferred example of the simulation method of the circuit, the group
The feedback clock signal rises and changes at the quasi-time.
In the case (B), the reference clock signal
At the reference time,
If the feedback clock signal falls,
In (B), the falling of the reference clock signal
Judge that there is a change.

In this case, the reference clock signal changes.
Value from the time obtained by subtracting the reference time corresponds to a phase difference between the reference clock signal and the feedback clock signal. Therefore, before the changed time of the reference clock signal
Since the value itself which is obtained by subtracting the serial reference time may be set to the additional delay value, there is an advantage that the calculation of the additional delay value (and hence the second delay value) is facilitated.

(6) First and second PLLs of the present invention
In another preferred embodiment of the simulation method of the circuit, before
Each of the reference clock signal and the feedback clock signal
From the time when the reference clock signal and the feedback clock
Judge whether the lock signal is synchronized or not.
If so, schedule to output the lock signal.
Jules.

[0036] In this case, there is an advantage that application to simulation shea <br/> tio down the PLL circuit further outputs indicate to <br/> lock signal that synchronous operation is obtained becomes possible.

(7) In the third PLL circuit of the present invention,Stain
SimulationThe method isOutput clock signal is fed back to the input side
The obtained feedback clock signal is used as a predetermined reference clock signal.
Comparing the feedback clock signal with the reference clock signal
By operating to eliminate the phase difference of
P to synchronize the return clock signal with the reference clock signal
In a method for simulating an LL circuit, (A) The time when the feedback clock signal changes is set as a reference time
Set as time, (B) At a certain current time, the reference clock signal
Whether there is a rising or falling change of
Judge, (C) In (B), the reference clock signal
One of the rising and falling changes
If it is determined that there is a delay,
Set a predetermined first delay value as the interval, (D) In (B), the reference clock signal
It is determined that there is a rising or falling change.
If the connection is interrupted, the difference between the current time and the reference time is calculated.
Set as an additional delay value, and
A second delay value equal to the sum of the first delay value and the delay time
Set as  (E)Count the number of input clocks of the reference clock signal
The number of input clocks exceeds the specified value.
Judge (F) In (E), the number of input clocks is
If it is determined that the specified value has not been exceeded,
(C) from the current time by the delay time set in
A change in the output clock signal occurs at a delayed time.
Schedule to (G) In (E), the number of input clocks is
If it is determined that the value exceeds the specified value, the above (C)
Or the current time by the delay time set in (D).
The output clock signal changes at a time later than
Schedule to It is characterized by the following.

(8) Stain of the Third PLL Circuit of the Present Invention
The first method of the present invention described in the above (1)
Like the simulation method of the LL circuit, wherein
In (A) to (D), the reference time, the first delay value, the additional delay
An extension value and a second delay value are set. Furthermore, (E) smell
Counting the number of input clocks of the reference clock signal
And determine whether the number of input clocks exceeds the specified value.
to decide. And in the above (F) and (G),
Judged that the number of input clocks did not exceed the specified value
In this case, the delay time set in (C) is earlier than the delay time.
At a time later than the current time, the output clock signal
Schedule the change to occur and the input clock
If it is determined that the number exceeds the specified value,
The delay time set in (C) or (D)
At a time later than the current time, the output clock signal changes.
Schedule for the occurrence to occur .

[0039] by, by the same reason as described above (2), the simulation it becomes possible to at once synchronous operation and asynchronous operation of the PLL circuit, with high accuracy of the simulation results, it is possible to shorten the calculation time In addition, the efficiency of the simulation operation is improved.

Furthermore, since the asynchronous operation is simulated until the input count exceeds the specified value, there is an advantage that the period of the asynchronous operation can be adjusted by changing the value of the specified value.

(9) Stain of the third PLL circuit of the present invention
In a preferred example of the compilation method, the reference time
When the feedback clock signal rises and changes,
In (B), the rise of the reference clock signal is
The feedback clock at the reference time.
In the case where the falling edge signal changes,
In this case, there is a falling change of the reference clock signal.
Judge.

In this case, for the same reason as described in the above (5), there is an advantage that the calculation of the additional delay value (and the second delay value) becomes easy.

(10) The present invention3Of the PLL circuitShi
SimulationIn another preferred example of the method,Next step
(H), (I), and (J). (H) Whether the frequency of the reference clock signal changes
The frequency of the reference clock signal changes.
If it is determined that there is, the reference clock signal and the
It is determined whether the feedback clock signal is synchronized. (I) In the above (H), the reference clock signal and
When it is determined that the feedback clock signal is synchronized
Is the current time for the delay time set in (D).
The output clock signal changes at a time delayed from the time.
Schedule like this. (J) In the above (H), the reference clock signal and
When it is determined that the feedback clock signal is not synchronized
The reference time set in (A) and the reference time
Clearing the additional delay value set in (D),
(C) from the current time by the delay time set in
A change in the output clock signal occurs at a delayed time.
Schedule to .

In this case, for the same reason as described in the above (4), there is an advantage that it can be applied to a logic simulation in which the frequency of the reference clock signal is not constant.

[0045] (11) of the third PLL circuit of the present invention Shi
In still another preferred embodiment of the simulation method, the
Each of the reference clock signal and the feedback clock signal
From the changing time, the reference clock signal and the feedback clock
Judgment whether the synchronization signal is synchronized
If so, schedule to output a lock signal.
Module.

[0046] In this case, there is an advantage that application to simulation shea <br/> tio down the PLL circuit further outputs indicate to <br/> lock signal that synchronous operation is obtained becomes possible.

(12) In the logic simulation method according to the present invention, a change in a signal of a logic circuit including a PLL circuit is registered as an event, and the registered event is extracted in a time series and extracted. Identify circuit cells whose input signals change due to events, and simulate the identified circuit cells.
In a logic simulation method for executing an operation and registering a change in its output signal as a new event, the extracted event is sent to the PLL circuit.
Of the input reference clock signal and feedback clock signal
If at least one change is indicated, the input signal change
The PLL circuit is specified as a circuit cell to be
The simulation of the LL circuit is performed by the above (1), (3),
(5), (6), (7), (9), (10) and (1)
The simulation method for any one of the PLL circuits of 1)
Said P executed by using
The change of the output clock signal of the LL circuit is detected by the new event.
It is characterized by registering as

[0048] In (13) the logic simulation method of the present invention, can be used first of the present invention, a simulation method of the second and third PLL circuit effectively.

[0049]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be specifically described below with reference to the accompanying drawings.

(First Embodiment) FIGS. 1 and 2 are flowcharts respectively showing a simulation method of a PLL circuit according to a first embodiment of the present invention and a logic simulation method of the first embodiment of the present invention using the same. is there. FIG. 3 is a circuit diagram showing one example of a logic circuit to which the PLL circuit simulation method and the logic simulation method according to the first embodiment of the present invention are applied.

First, the logic circuit of FIG. 3 will be described.

The logic circuit 20 includes a PLL circuit 21, a clock distribution unit 22, and two flip-flops FF1, FF.
F2.

The PLL circuit 21 has a reference clock signal R
CLK and the feedback clock signal CLKI are input.
PLL circuit 21 detects a phase difference between reference clock signal RCLK and feedback clock signal CLKI, and outputs an output clock signal CLKO whose phase is controlled according to the phase difference.

The clock distribution section 22 has two buffer amplifiers BF1 and BF2. The output clock signal CLKO supplied from the PLL circuit 21 is distributed by the clock distribution unit 22 and input to the buffer amplifiers BF1 and BF2. The buffer amplifiers BF1 and BF2 are
Waveform shaping the output clock signal CLK O input, and outputs an internal clock signal CLKI1, CLKI2 respectively. The buffer amplifier BF1 has an internal clock signal CL
The same signal as KI1 is used as feedback clock signal CLKI as P
It is supplied to the LL circuit 21.

The flip-flops FF1 and FF2 receive the internal clock signals CLKI1 and CLKI2 output from the buffer amplifiers BF1 and BF2, respectively, and also receive the logical input signals LIS1 and LIS2. The flip-flops FF1 and FF2 output logical output signals LOS1 and LOS2, respectively.

In the logic circuit shown in FIG.
Continuously adjusts the phase of the output clock signal CLKO so that the reference clock signal RCLK and the feedback clock signal CL
The phases of the KIs are matched. As a result, the feedback clock signal CLKI (that is, the internal clock signal CLKI1 ) is synchronized with the reference clock signal RCLK. Thus, the reference clock signal R is applied to the flip-flops FF1 and FF2.
Internal clock signals CLKI1, CLK synchronized with CLK
I2 is supplied stably.

[0057] [simulation method of the PLL circuit] Next, an example case of applying the PLL circuit 21 shown in FIG. 3, simulation of the PLL circuit of the first embodiment of the present invention
The operation method will be described with reference to the flowchart of FIG. In the following description of FIG. 1, it is assumed that the current time in the event-driven method and an event corresponding to the current time have already been extracted.

In FIG. 1, in step S1, which is executed first, it is determined whether or not an additional delay value tc corresponding to the phase difference between reference clock signal RCLK and feedback clock signal CLKI has already been set. If the determination is "YES" (that is, the additional delay value tc has been set), the process proceeds to step S15. If the determination is "NO" (that is, the additional delay value tc has not been set), the process proceeds to step S2. .

In step S2, it is determined whether or not a reference time ts required for calculating the additional delay value tc has already been set. Then, "YES" (that is, the reference time ts
If is already set), the process proceeds to step S 9, "NO"
(I.e., reference time ts is not set) in the case of, the process proceeds to step S 3.

In step S3, the change of the reference clock signal RCLK is determined by examining the extracted event. Then, “YES” (that is, the reference clock signal RCL
If K has changed), the process proceeds to step S4, and “NO”
In the case of (that is, the reference clock signal RCLK has not changed), the process proceeds to step S7.

In step S4, a predetermined standard delay value ta
Is set to the delay time td.

In the next step S5, the value of the output clock signal CLKO is updated by setting the changed value of the reference clock signal RCLK indicated by the extracted event to the value of the output clock signal CLKO. Thereafter, the process proceeds to step S6.

In step S6, the output clock signal CL
Generate a new event indicating that the value of KO has been updated. The new event occurrence time is set to a time (t + td) delayed from the current time t by the delay time td. That is, a change in the output clock signal CLKO is scheduled as an event at time (t + td). After that, the process ends.

In step S7, the extracted event is examined to determine whether or not the feedback clock signal CLKI has changed in rising. If “YES” (ie, the rise of the feedback clock signal CLKI), the process proceeds to step S8. "NO" (that is, the feedback clock signal CLKI did not change in rising)
In the case of, the process ends.

In step S8, the current time t (ie,
The change time of the feedback clock signal CLKI) is changed to the reference time ts.
Set as After that, the process ends.

In step S9, the extracted event is examined to determine whether or not the reference clock signal RCLK has changed at the falling edge. If “YES” (ie, the reference clock signal RCLK has changed falling), the process proceeds to step S4, and if “NO” (ie, the reference clock signal RCLK has not changed falling), the process proceeds to step S4. Proceed to S10.

In step S10, the extracted event is examined to determine whether or not the rising of the reference clock signal RCLK has changed. If “YES” (ie, the reference clock signal RCLK has changed in rising), the process proceeds to step S11. If “NO” (ie, the reference clock signal RCLK has not changed in rising), the process ends. I do.

In step S11, a value (t-ts) obtained by subtracting the set reference time ts from the current time t (ie, the change time of the reference clock signal RCLK) is set as the additional delay value tc.

In the next step S12, the standard delay value ta
(Ta + tc) obtained by adding the additional delay value tc to the delay time td. Thereafter, the process proceeds to step S13.

In step S13, as in step S5, the reference clock signal RCL indicating the extracted event
The value of the output clock signal CLKO is updated by setting the value after the change of K to the value of the output clock signal CLKO. Thereafter, the process proceeds to step S14.

In step S14, as in step S6, a new event indicating that the value of the output clock signal CLKO has been updated is generated. The new event occurrence time is set to a time (t + td) delayed from the current time t by the delay time td. That is, a change in the output clock signal CLKO is scheduled as an event at time (t + td). After that, the process ends.

In step S15, the change of the reference clock signal RCLK is determined by examining the extracted event.
If “YES” (ie, the reference clock signal RCLK has changed), the process proceeds to step S12, and “NO” (ie, the reference clock signal RCLK has not changed).
In the case of, the process ends.

With the steps described above, the simulation of the PLL circuit 21 is performed.

[0074] simulation method of the PLL circuit of the logic simulation method] FIG. 1 is used by being incorporated in the logic simulation method shown in the flowchart of FIG. The operation of the PLL circuit 21 of FIG. 3 is simulated by repeatedly executing the simulation method of the PLL circuit of FIG. 1 in the logic simulation method of FIG. Further, in the logic simulation method of FIG. 2, the entire operation of the logic circuit 20 including the PLL circuit 21 is simulated. Hereinafter, FIG.
Will be described.

In the flowchart of FIG. 2, first, in step S101, initialization is performed. In the initial setting, circuit cell information, circuit connection information, circuit delay value information, input signal information, and model information are read from an information file prepared in advance.

The circuit cell information is a data group indicating what kind of circuit cell the logic circuit is composed of. 3, the PLL circuit 21 and the buffer amplifier B
F1, BF2 and flip-flops FF1, FF2
The circuit cell information indicates that the configuration is made up of:

The circuit connection information is a data group indicating the connection state between each circuit cell indicated by the circuit cell information. For example, the output terminal of the PLL circuit 21 is a buffer amplifier BF
1, the circuit connection information indicates that it is connected to the input terminal of the BF2.

The circuit delay information is provided by a so-called SDF (Standa
rd Delay File), which is a delay time (hereinafter referred to as a standard delay value) set for each circuit cell indicated by the circuit cell information and a connection line between the circuit cells indicated by the circuit cell information. ). For example, the PLL circuit 21 and the buffer amplifiers BF1, B
The circuit delay information indicates the standard delay value of F2, the standard delay value between the output terminal of the PLL circuit 21 and the input terminal of the buffer amplifier BF1, and the like.

The input signal information is what is called an input vector, and is a data group indicating input signals for verifying the operation of the logic circuit. For example, the reference clock signal RCL
The input signal information indicates a change in K or the like.

The model information is a program group in which models corresponding to each circuit cell are stored. 3, the PLL circuit 21, the buffer amplifiers BF1, BF2, and the flip-flops FF1, FF
The model corresponding to each of 2 is stored in the model information.

Further, in the initial setting, an event is registered based on the read input signal information. All events are registered in chronological order based on the event occurrence time.
For example, to register a change of the reference clock signal RCLK and <br/> the event.

Next, set the current time t at step S102 to the initial value t _0.

Subsequently, in step S103, it is determined whether or not there is an event at the current time t from the registered events. In the case of “YES” (ie, there is a corresponding event), the flow proceeds to step S104 and “NO”
If there is no corresponding event, the process proceeds to step S108.

In step S104, an event at the current time t is extracted, and a circuit cell whose input signal changes due to the event is specified. Then, a model corresponding to the specified circuit cell is extracted from the model information. Thereafter, the process proceeds to step S105.

In step S105, an arithmetic process is performed on the specified circuit cell using the extracted event and model. As a result of the arithmetic processing, if there is a change in the calculated output signal of the circuit cell, the change of the output signal is scheduled as a new event. If the PLL circuit 21 is specified in step S104, the operation of the PLL circuit 21 is performed in step S105 based on the flowchart of FIG. Step S10
If the buffer amplifiers BF1 and BF2 and the flip-flops FF1 and FF2 are specified at 4, the arithmetic processing is performed by a known method.

In step S106, step S105
To determine if a new event has been scheduled. If “YES” (ie, a new event has been scheduled), the scheduled event is registered in the next step S107. If “NO” (that is, no new event has been scheduled), the process returns to step S103. If step S10
5, the event of the output clock signal CLKO is scheduled (see FIG. 1).
It is determined whether or not step S5) has been performed.

In step S108, the current time t is advanced by a predetermined time interval (time step) Δt. In the next step S109, it is determined whether or not the current time t has exceeded the end time t _END . If “YES” (ie, the current time t has exceeded the end time t _END ), the simulation ends. If “NO” (that is, the current time t does not exceed the end time t _END ), step S10
Return to 3.

In step S103, if all events at the current time t have been extracted, "NO" is determined.
Therefore, steps S103 to S107 are repeatedly executed until all the events at the current time t have been extracted.

Thus, a logic simulation of the logic circuit 20 shown in FIG. 3 is performed.

[Simulation Principle] Next, a simulation of the PLL circuit according to the first embodiment of the present invention will be described.
Deployment methods and the principles of logic simulation method will be described using the same. Note that here, P
Only the principle relating to the simulation (arithmetic processing) of the LL circuit will be described.

FIG. 4 is a timing chart showing the operation of the PLL circuit 21 when a simulation is performed using the logic simulation method according to the first embodiment of the present invention.

Referring to FIG. 4, at times t1, t7, t1
At 0 and t14, a rise in the reference clock signal RCLK (that is, a change from level L to level H) occurs. Also, at times t4, t8, t12, t
At 16, a falling change (that is, a change from level H to level L) occurs in the reference clock signal RCLK. These changes in the rise and fall of the reference clock signal RCLK are determined in step S1 of FIG.
01 is registered as an event. That is,
At times t1, t7, t10 and t14, events EV1 and E
V3, EV5, and EV7 are registered, respectively, and at time t4,
Events EV2, EV4, EV at t8, t12, t16
6 and EV8 are respectively registered.

<Case of current time t = t1> In step S108 of FIG. 2, the current time t is advanced to the current time t = t1.
Is set at time t1, the event EV1 is registered at the time t1, so that “YES” is determined in the step S103. Then, in step S104, the event EV1
Is extracted, and a PLL circuit model is extracted.
Further, in step S105, the arithmetic processing of the PLL circuit is performed based on the flowchart of FIG.

At the time t = t1, the additional delay value tc and the reference time ts have not yet been set. Therefore, “NO” is determined in step S1 of FIG. 1, and “NO” is determined in the next step S2, and the process proceeds to step S3.

The event EV1 is the reference clock signal RCL
Since it indicates a change in the rise of K, "YES" is determined in step S3. In the next step S4, the standard delay value ta is set as the delay time td.
Then, in steps S5 and S6, an event EV1a indicating that the value of the output clock signal CLKO has changed from level L to level H is scheduled at time t2 (= t1 + ta).

Thus, the calculation processing in step S105 ends, and the flow advances to step S106.

In steps S106 and S107, the event EV1a is registered. Thereafter, step S103
Is executed, but here, since only the PLL circuit 21 is focused on, the process proceeds to step S108. The same applies to the following description.

In steps S108 and S109, the current time t is advanced.

<If current time t = t2> Step S1
08, when the current time t is set to t = t2, the event EV1a is registered at the time t2.
03 is determined as “YES”. Then, step S1
At 04, the event EV1a is extracted, and a model corresponding to the buffer amplifier BF1 is extracted. In step S105, arithmetic processing is performed by a known method.
As a result, in steps S106 and S107,
An event EV1b indicating that the value of the internal clock signal CLKI1 (that is, the feedback clock signal CLKI) has changed from level L to level H is registered at time t3.
At this time, the occurrence time t3 of the event EV1b is changed to the time t2
Is set to a time (t2 + tb) delayed by a standard delay value tb of the buffer amplifier BF1.

Thereafter, the current time t is further advanced through steps S103, S108 and S109.

<When current time t = t3> Step S1
08, when the current time t = t3 is set, since the event EV1b is registered at the time t3,
03 is determined as “YES”. Then, step S1
04, the event EV1b is extracted and the PL
An L circuit model is extracted. Further, step S105
Then, the arithmetic processing of FIG. 1 is performed.

At the current time t = t3, the additional delay value tc and the reference time ts have not been set yet. Therefore, “NO” is determined in step S1 of FIG. 1, and “NO” is determined in the next step S2, and the process proceeds to step S3.

The event EV1b is the feedback clock signal CL
Since it indicates a change in the rise of KI, "NO" is determined in step S3, and "Y" is determined in the next step S7.
ES ”. Then, in step S8, the current time t = t3 is set as the reference time ts. in this case,
No new events are scheduled.

Thus, the calculation processing in step S105 ends, and the flow advances to step S106.

In step S106, "NO" is determined. Thereafter, steps S103, S108 and S1
After 09, the current time t is further advanced.

<When current time t = t4> Step S1
08, when the current time is set to t = t4, since the event EV2 is registered at the time t4, step S10
It is determined as “YES” in 3. Then, step S10
At 4, the event EV2 is extracted and the PLL circuit model is extracted. Further, in step S105, the calculation processing of FIG. 1 is performed.

At the current time t = t4, the additional delay value tc has not been set yet, and the reference time ts has already been set. Therefore, "NO" in step S1 of FIG.
Is determined, "YES" is determined in the next step S2, and the process proceeds to step S9.

Event EV2 is a reference clock signal RCL
Since it indicates a change in the fall of K, "YES" is determined in the step S9. And step S
At 4, S5 and S6, an event EV2a indicating that the value of the output clock signal CLKO has changed from level H to level L is scheduled at time t5 (= t4 + ta).

Thus, the calculation processing in step S105 ends, and the flow advances to step S106.

In steps S106 and S107, the event EV2a is registered. Then, step S10
3, the current time t is further advanced through S108 and S109.

<When current time t = t5> Step S1
When the current time t = t5 is set in step 08, the event EV2a is registered at the time t5, so that step S1 is executed.
03 is determined as “YES”. And S104, S
In 105, S106 and S107, the current time t = t
2, the internal clock signal CLKI1
Event EV2b indicating that the value of feedback clock signal CLKI has changed from level H to level L
Is registered at time t6 (= t5 + tb).

Thereafter, the current time t is further advanced through steps S103, S108 and S109.

<When current time t = t6> Step S1
08, when the current time t is set to t = t6, since the event EV2b is registered at the time t6, step S1
03 is determined as “YES”. Then, step S1
At 04, the event EV2b is extracted and the PL
An L circuit model is extracted. Further, step S105
Then, the arithmetic processing of FIG. 1 is performed.

At the current time t = t6, the additional delay value tc has not yet been set, and the reference time ts has already been set. Therefore, "NO" in step S1 of FIG.
Is determined, "YES" is determined in the next step S2, and the process proceeds to step S9.

The event EV2b is the feedback clock signal CL
Since it indicates a change in the fall of KI, "NO" is determined in the step S9. Further, "NO" is determined in the next step S10, and the process ends. In this case, no new event is scheduled.

Thus, the calculation processing in step S105 ends, and the flow advances to step S106.

In step S106, "NO" is determined. Thereafter, steps S103, S108 and S10
After 9, the current time t is further advanced.

<When current time t = t7> Step S1
08, when the current time is set to t = t7, since the event EV3 is registered at the time t7, step S10
It is determined as “YES” in 3. Then, step S10
At 4, the event EV3 is extracted and the PLL circuit model is extracted. Further, in step S105, the calculation processing of FIG. 1 is performed.

At the current time t = t7, the additional delay value tc has not been set yet, and the reference time ts has already been set. Therefore, "NO" in step S1 of FIG.
Is determined, "YES" is determined in the next step S2, and the process proceeds to step S9.

The event EV3 is the reference clock signal RCL
Since it indicates a change in the rise of K, "NO" is determined in step S9, and "YES" is determined in step S10, and the process proceeds to step S11.

In step S11, the value (t-ts) (= (t7-t) obtained by subtracting the reference time ts from the current time t = t7.
t3)) is set as the additional delay value tc. In the next step S12, a value (ta + tc) obtained by adding the additional delay value tc to the standard delay value ta is set as the delay time td. In steps S13 and S14, an event EV3a indicating that the value of the output clock signal CLKO has changed from level L to level H is generated at time t9 (= t7 +
ta + tc).

Thus, the calculation processing in step S105 ends, and the flow advances to step S106.

In steps S106 and S107, the event EV3a is registered. Then, step S10
3. The current time t is advanced through steps S108 and S109.

<When current time t = t8> Step S1
08, when the current time t = t8 is set, since the event EV4 is registered at the time t8, the process proceeds to step S10.
It is determined as “YES” in 3. Then, step S10
At 4, the event EV4 is extracted and the PLL circuit model is extracted. Further, in step S105, the calculation processing of FIG. 1 is performed.

At the time t = t8, the additional delay value tc has already been set. Therefore, “YES” is determined in the step S1, and the process proceeds to a step S15.

Since the event EV4 indicates a change in falling of the reference clock signal, "YES" is determined in the step S15. Then, steps S12 and S
At 13 and S14, an event EV4a indicating that the value of the output clock signal CLKO has changed from level H to level L is scheduled at time t11 (= t8 + ta + tc).

Thus, the calculation processing in step S105 ends, and the flow advances to step S106.

At steps S106 and S107, the event EV4a is registered. Then, step S10
3. The current time t is advanced through steps S108 and S109.

<When current time t = t9> Step S1
08, when the current time t is set to t = t9, since the event EV3a is registered at the time t9, step S1 is executed.
03 is determined as “YES”. Then, step S1
04, S105, S106, and S107, the internal clock signal CL is set as in the case of the current time t = t2.
Event E indicating that the value of KI1 (ie, feedback clock signal CLKI) has changed from level H to level L
V3b is registered at time t10 (= t9 + tb).

Thereafter, the current time t is further advanced through steps S103, S108 and S109.

<When current time t = t10> Current time t
= T10, the event EV at time t10
5 and EV3b have been registered, so step S1
03 is determined as “YES”. Then, step S1
At 04, the events EV5 and EV3b are extracted, and the PLL circuit model is also extracted. Further, in step S105, the calculation processing of FIG. 1 is performed.

At the time t = t10, the additional delay value tc has already been set. Therefore, step S1
Is determined as "YES", and the process proceeds to step S15. Since the event EV5 indicates a change in the rise of the reference clock signal RCLK, “YE” is determined in step S13.
S ”. Then, in steps S12, S13 and S14, an event EV5 indicating that the value of the output clock signal CLKO has changed from level L to level H
a is scheduled at time t13 (= t10 + ta + tc).

Thus, the calculation processing in step S105 ends, and the flow advances to step S106.

Thereafter, the current time t is further advanced through steps S103, S108 and S109.

<If current time t = t11> Step S
When the current time t = t11 is set at 108, the time t1
Since the event EV4a is registered in No. 1, "YES" is determined in the step S103. Then, in steps S104, S105, S106 and S107,
As in the case of the current time t = t2, the internal clock signal CLKI1 (that is, the feedback clock signal CLKI)
Is registered at time t12 (t11 + tb), indicating that the value of has changed from level H to level L.

Thereafter, the current time t is further advanced through steps S103, S108 and S109.

<Case of current time t = t12> Step S
When the current time t = t12 is set at 108, the time t1
Since events EV6 and EV4b are registered in No.2, "YES" is determined in the step S103. Then, in the step S104, the events EV6 and E
V4b is extracted, and a PLL circuit model is extracted. Further, in step S105, the calculation processing of FIG. 1 is performed.

At the current time t = t12, the additional delay value tc has already been set. Therefore, step S1
Is determined as "YES", and the process proceeds to step S15. Since the event EV5 indicates a change in the falling of the reference clock signal RCLK, “YE” is determined in step S15.
S ”. Then, in steps S12, S13 and S14, an event EV6 indicating that the value of the output clock signal CLKO has changed from level H to level L.
a is scheduled at time (t12 + ta + tc).

Thus, the calculation processing in step S105 ends, and the flow advances to step S106.

Thereafter, the current time t is further advanced through steps S103, S108 and S109.

If the current time t is set to t13, t14, t15 and t16, the current time t is set to t9, t9
The same processing as that performed when the values are set to 10, t11, and t12 is performed. Thereafter, the processing is similarly executed repeatedly.

According to the timing chart of FIG.
During the period T1 from t6 to t6, the phases of the reference clock signal RCLK and the feedback clock signal CLKI do not match, indicating that the asynchronous operation is simulated.
In a period T2 after time t10, the phases of the reference clock signal RCLK and the feedback clock signal CLKI match,
It can be seen that the synchronous operation has been simulated.
Then, a period T3 from the asynchronous operation to the synchronous operation
Corresponds to two periods of the reference clock signal RCLK.

[0143] Thus, the synchronous operation in a short period T2 is obtained, for the event EV3～EV 6 of the reference clock signal RCLK generated after the time t7, the occurrence of an event EV3a~EV6a of the output clock signal CLKO Is delayed by the delay time td = (ta + tc).

As shown in FIG. 4, the calculated additional delay value tc corresponds to the phase difference between feedback clock signal CLKI and reference clock signal RCLK. In other words, the feedback clock signal CLKI generated when the standard delay value ta is set to the delay time td is the reference clock signal RCL
This means that the phase of K is advanced by the additional delay value tc. Therefore, by further delaying output clock signal CLKO by additional delay value tc, the phases of reference clock signal RCLK and feedback clock signal CLKI can be matched.

As described above, in the PLL circuit simulation method according to the first embodiment of the present invention, the additional delay value t
After calculating c, the synchronous operation is performed using the added delay value tc.
Is set for the delay time td required for. Therefore, even when the configuration of the logic circuit is changed or the frequency of the reference clock signal RCLK is changed, it is not necessary to calculate the delay time of the output clock signal required for the synchronous operation. Therefore, if the method of simulating the PLL circuit according to the first embodiment of the present invention is used for logic simulation of a logic circuit including the PLL circuit , the work efficiency of the simulation is improved.

Further, in the logic simulation method using the PLL circuit simulation method according to the first embodiment of the present invention, the asynchronous operation and the synchronous operation of the PLL circuit can be simulated at once, and a high simulation can be performed in each operation. Accuracy is obtained.

Furthermore, since the synchronous operation is reached in the period T3 corresponding to two cycles of the reference clock signal RCLK, the number of clocks processed for obtaining the synchronous operation is reduced, and the calculation time for the simulation is reduced.

The PLL circuit of the first embodiment shown in FIG.
In the simulation method, the rising change time of the feedback clock signal CLKI is set to the reference time ts in steps S7 and S8.
The falling time of I may be set as the reference time ts. In this case, change the step S 7 that way, the reference clock signal reference time ts from falling transition time in RCLK may be a value obtained by subtracting the added delay value tc in step S11.

In step S9, the reference clock signal R
It may be determined whether or not CLK has changed in rising, and whether or not the reference clock signal RCLK has changed in falling in step S10. Also in this case, the same effect as the simulation method of the PLL circuit of FIG. 1 can be obtained.

(Second Embodiment) FIG. 5 is a diagram showing a simulation of a PLL circuit according to a second embodiment of the present invention.
6 is a flowchart illustrating a method of arranging the parts . PL in FIG.
The L circuit simulation method is also executed in step S105 of the flowchart in FIG.

[0151] simulation method of the PLL circuit of FIG. 5, the simulation method of the PLL circuit of FIG. 1, step S21 in order to correspond when the synchronous operation is compromised,
This corresponds to the addition of S22 and S23. Otherwise, since it is identical with the simulation method of the PLL circuit of FIG. 1, simulated PLL circuit of FIG. 1 in FIG. 5
The Deployment method same steps as the explanation thereof will be denoted by the same reference numerals.

In the flowchart of FIG. 5, if the determination in step S15 is "YES" (that is, reference clock signal RCLK has changed), step S21 is executed.

In step S21, the extracted event is checked to determine whether or not the rising of the reference clock signal RCLK has changed. If the determination is "YES" (that is, the reference clock signal RCLK has changed in rising), the process proceeds to step S22, and the determination is "NO".
In the case of (that is, the rise of the reference clock signal RCLK has not changed), the process proceeds to step S12.

In step S22, the extracted event is examined to determine whether or not the feedback clock signal CLKI has changed in rising. If the determination is "YES" (that is, the feedback clock signal CLKI has changed in rising), the process proceeds to step S12, and the determination is "NO".
In the case of (that is, the feedback clock signal CLKI has not changed in rising), the process proceeds to step S23.

In step S23, the values of the set additional delay value tc and reference time ts are cleared, and the setting of those values is released. Then, the flow advances to step S4.

[0156] Next, the case where the frequency of the reference clock signal RCLK is not constant example, simulator of the PLL circuit of FIG. 5
The simulation principle when the solution method is used for the arithmetic processing of the logic simulation method of FIG. 2 will be described. Until the frequency of the reference clock signal RCLK changes, the first S1 to S15 in FIG.
Synchronous operation is simulated based on the same principle as the logic simulation method of the embodiment. Here, only the principles related to steps S21, S22, and S23 in FIG. 5 will be described to avoid duplication of description.

In steps S21 and S22 of FIG. 5, it is determined whether or not the rise of the reference clock signal RCLK and the rise of the feedback clock signal CLKI simultaneously occur based on the event extracted in step S104 of FIG. . If the extracted event indicates a change in the rise of the reference clock signal RCLK during the synchronous operation, “YES” is determined in step S21, and “YES” is determined in the next step S22, and step S13 is performed. , S12 and S14 are executed. The extracted event is a reference clock signal RCL during synchronous operation.
If it indicates a change in the fall of K, step S
21 is determined to be "NO", and steps S12, S13 and S14 are executed. Therefore, for the event during the synchronous operation, the simulation of the PLL circuit of FIG.
The same processing is performed as in the application method .

When the frequency of the reference clock signal RCLK changes, the synchronous operation is impaired and the operation shifts to the asynchronous operation. This is because the additional delay value tc required for the synchronous operation depends on the frequency of the reference clock signal RCLK. Therefore, if the extracted event indicates a change in the rise of the reference clock signal RCLK after the frequency change, “YES” is determined in the step S21, and “NO” is determined in the next step S22, and the step S23 is determined. Is executed. Then, in step S23, the additional delay value tc
After the setting of the reference time ts is canceled, in the next steps S4, S5 and S6, an event indicating a change in the rising of the output clock signal CLKO is scheduled using the standard delay value ta as the delay time td.

After the setting of the additional delay value tc and the reference time ts is canceled in step S23, the simulation from the asynchronous operation to the synchronous operation is performed according to the same principle as the logic simulation method of the first embodiment. As a result, a new additional delay value tc 'corresponding to the frequency-changed reference clock signal RCLK is set, and the synchronous operation is obtained again.

As described above, the PL according to the second embodiment of the present invention is
If the simulation method of the L circuit is used for the operation processing of the logic simulation, the logic simulation can be performed even when the frequency of the reference clock signal is not constant.
Further, a simulation of the PLL circuit according to the first embodiment of the present invention is performed.
As in the case of the simulation method, it is possible to obtain the effect that the work efficiency of the simulation is improved, high simulation accuracy is obtained, and the calculation time of the simulation is shortened.

The PLL circuit of the second embodiment shown in FIG.
In the simulation method, after performing step S23, the process may proceed to step S12. In this case, the period until the synchronous operation is obtained again after the frequency change becomes slightly longer, but the same effect as in the case of the arithmetic processing method of the PLL circuit in FIG. 5 can be obtained.

(Third Embodiment) FIG. 6 is a diagram showing a simulation of a PLL circuit according to a third embodiment of the present invention.
6 is a flowchart illustrating a method of arranging the parts . PL in FIG.
The simulation method of the L circuit is also executed in step S105 of the flowchart of FIG.

[0163] simulation method of the PLL circuit of FIG. 6, step S31 to adjust the duration of the asynchronous operation to the simulation method of the PLL circuit of FIG. 1, S32, S
This corresponds to the addition of 33 and S34. And
Steps S12 ′, S13 ′ and S14 ′ in FIG. 6 correspond to steps S12, S13 and S14 in FIG. 1, respectively. In step S15 of FIG. 6, the determination is “Y
If "ES" (that is, the reference clock signal RCLK has changed), the process proceeds to step S4. Otherwise, the method is the same as the simulation method of the PLL circuit of FIG.
6, the same steps as those in the simulation method of the PLL circuit in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

In the flowchart of FIG. 6, immediately after the processing is started, the extracted event is checked to determine in step S31 whether or not the rising of the reference clock signal RCLK has changed. If the determination is "YES" (that is, the reference clock signal has changed in rising), the process proceeds to step S32, and if the determination is "NO" (in other words, the reference clock signal RCLK has not changed in rising), Proceed to step S33.

In step S32, "1" is added to the value of the preset counter.

In the step S33, it is determined whether or not the value of the counter is equal to or less than a predetermined value. Judgment is "YE
If "S" (that is, the value of the counter is equal to or less than the prescribed value), the process proceeds to step S1, and if "NO" (that is, the value of the counter exceeds the prescribed value), the process proceeds to step S34.

In step S34, the change of the reference clock signal RCLK is determined by examining the extracted event.
If the determination is “YES” (ie, the reference clock signal RCL
If K has changed), the process proceeds to step S12 ′, and if the determination is “NO” (ie, the reference clock signal RCLK has not changed), the process ends.

In step S12 ', step S12 in FIG.
Similarly to 12, a value (ta + tc) obtained by adding the additional delay value tc to the standard delay value ta is set as the delay time td. Then, in steps S13 'and S14', as in steps S13 and S14 of FIG. 1, the value of the output clock signal CLKO is updated with the changed value of the reference clock signal RCLK indicated by the extracted event, and the output clock signal C
A change in LKO is scheduled as an event at time (t + td). After that, the process ends.

If the determination in step S15 of FIG. 6 is "YES" (that is, reference clock signal RCLK has changed), steps S4, S5 and S6 are executed. That is, the change of the output clock signal CLKO is scheduled using the standard delay value ta as the delay time td.

In the PLL circuit simulation method of FIG. 6, steps 31 and S32 count the number of rising changes of the reference clock signal RCKL. In other words, the number of input clocks of the reference clock signal RCLK is counted. Then, a step S33 compares the counted number of input clocks with a specified value to determine whether or not the number exceeds the specified value. As a result of the comparison in step S33,
If the counted number of input clocks exceeds the specified value (that is, if the determination is “NO”), the sum (ta + tc) of the standard delay value ta and the additional delay value tc is set as the delay time td ( Step S12 '). If the counted number of input clocks is equal to or smaller than the specified value, the standard delay value ta is set to the delay time td even if the additional delay value tc has been set (step S4).

As described above, the PL according to the third embodiment of the present invention is
In the simulation method of the L circuit, the reference clock signal RC
Since the set value of the delay time td can be selected according to the number of input clocks of the LK, the period of the asynchronous operation can be adjusted. Further, as in the case of the PLL circuit simulation method according to the first embodiment of the present invention, the effects of improving the simulation work efficiency, obtaining high simulation accuracy, and shortening the simulation calculation time are obtained. Can be

The simulation of the PLL circuit shown in FIG.
In the PLL method of the second embodiment of the present invention,
As in the simulation method, step S2 in FIG.
It is of course possible to add 1, S22 and S23. In that case, in addition to the above effects, it is possible to apply the present invention to a logic simulation in which the frequency of the reference clock signal is not constant.

(Fourth Embodiment) FIG. 7 is a simulation diagram of a PLL circuit according to a fourth embodiment of the present invention.
6 is a flowchart illustrating a method of arranging the parts . PL in FIG.
The simulation method of the L circuit is also executed in step S105 of the flowchart of FIG.

[0174] simulation method of the PLL circuit of FIG. 7, was added to the simulation method of the PLL circuit of FIG. 1, the steps S51, S52 and S53 in order to schedule a change of the lock signal LOCK to indicate that it has been subjected to the synchronous operation Equivalent to something. Otherwise, the method is the same as the simulation method of the PLL circuit of FIG.
7, the same steps as those in the PLL circuit simulation method of FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

In the PLL circuit simulation method of FIG. 7, step S51 is executed following step S14. In step S51, the extracted event is examined to determine whether or not the reference clock signal RCLK has changed in rising. If the determination is “YES” (ie,
The reference clock signal RCLK has changed in rising)
In step S52, the process proceeds to step S52. If the determination is "NO" (that is, the reference clock signal RCLK has not changed in rising), the process ends.

In step S52, the extracted event is examined to determine whether or not the feedback clock signal CLKI has changed in rising. If the determination is "YES" (that is, the feedback clock signal CLKI has changed in rising), the process proceeds to step S53, and the determination is "NO".
In the case of (that is, the feedback clock signal CLKI has not changed in rising), the processing is ended.

In step S53, an event indicating a change in the lock signal LOCK is scheduled at the current time t. After that, the process ends.

In the method of simulating the PLL circuit shown in FIG. 7, steps 51 and S52 are based on the change in rising of the reference clock signal RCLK and the change of the feedback clock signal CCLK.
FIG. 2 shows whether or not changes in the rise of LKI occurred simultaneously.
The determination is made based on the event extracted in step S104. If the extracted event indicates a change in the rise of the reference clock signal RCLK, “YES” is determined in the step S51, and the next step S2
It is determined as "YES" in 2 and step S53 is executed. If the extracted event indicates a change in the falling of the reference clock signal RCLK, the process proceeds to step S51.
Is determined as "NO", and the process is terminated. If the extracted event indicates a change in the fall of the feedback clock signal CLKI, “NO” is determined in the step S52, and the process ends.

Therefore, only when the reference clock signal RCLK and the feedback clock signal CLKI change at the same time, step S53 is executed, and an event indicating a change in the lock signal LOCK is scheduled.
That is, if the rising changes of the reference clock signal RCLK and the feedback clock signal CLKI are synchronized,
An event indicating a change in the lock signal LOCK is scheduled. Otherwise, no event indicating a change in the lock signal LOCK is scheduled.

As described above, the PL according to the fourth embodiment of the present invention is
In the simulation method of the L circuit, the reference clock signal RC
It is possible to simulate an operation including a lock signal LOCK indicating that changes in rising of the LK and the rise of the feedback clock signal CLKI are synchronized. Therefore,
Simulation of a PLL circuit that outputs the output clock signal CLKO and the lock signal LOCK can be performed. Further, a simulation of the PLL circuit according to the first embodiment of the present invention is performed.
As in the case of the simulation method, the effect of improving the work efficiency of the simulation, obtaining high simulation accuracy, and shortening the calculation time of the simulation is obtained.

The simulation of the PLL circuit shown in FIG.
In the PLL method of the second embodiment of the present invention,
As in the simulation method, step S2 in FIG.
1, S22 and S23 may be added. In this case, in addition to the above-described effects, the present invention can be applied to a logic simulation in which the frequency of the reference clock signal is not constant. In addition, the PLL circuit of the third embodiment of the present invention
As in the simulation method, step S31 in FIG.
S32, S33, S34 and S35 may be added. In that case, the period of the asynchronous operation can be adjusted. Further, steps S21, S22 and S23 in FIG. 5 and steps S31, S32, S33 and S3 in FIG.
It is of course possible to add 4 and S35.

[0182]

As described in the foregoing, in the simulation method of the PLL circuit of the present invention, it is possible to improve the efficiency of the simulation work, highly accurate results can be obtained in a short calculation time, further synchronization operation of the PLL circuit And asynchronous operation can be simulated at once.

In the logic simulation method of the present invention,
It is possible to improve the efficiency of the logic simulation work of the logic circuit including the PLL circuit, to obtain a highly accurate result in a short calculation time, and to simulate the synchronous operation and the asynchronous operation of the PLL circuit at once.

[Brief description of the drawings]

FIG. 1 is a simulation of a PLL circuit according to a first embodiment of the present invention.
6 is a flowchart illustrating a method of arranging the parts .

FIG. 2 is a flowchart illustrating a logic simulation method according to the first embodiment of the present invention.

FIG. 3 is a simulation of the PLL circuit according to the first embodiment of the present invention;
Shon methods and logic simulation method is a circuit diagram showing an example of a logic circuit is applied.

FIG. 4 is a simulation of a PLL circuit according to the first embodiment of the present invention;
4 is a timing chart of a PLL circuit for explaining the principles of a solution method and a logic simulation method.

FIG. 5 is a simulation of a PLL circuit according to a second embodiment of the present invention.
6 is a flowchart illustrating a method of arranging the parts .

FIG. 6 is a simulation of a PLL circuit according to a third embodiment of the present invention.
6 is a flowchart illustrating a method of arranging the parts .

FIG. 7 is a simulation of a PLL circuit according to a fourth embodiment of the present invention.
6 is a flowchart illustrating a method of arranging the parts .

[Explanation of symbols]

 Reference Signs List 20 logic circuit 21 PLL circuit 22 clock signal distribution unit BF1, BF2 buffer amplifier FF1, FF2 flip-flop RCLK reference clock signal CLKI feedback clock signal CLKO output clock signal CLKI1, CLKI2 internal clock signal LIS1, LIS2 logic input signal LOS1, LOS2 logic output Signal t Current time ta Standard delay value of PLL circuit tc Additional delay value of PLL circuit ts Reference time of PLL circuit td Delay time of PLL circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03L ^7/ 00-7/14 G06F 15/60

Claims (9)

(57) [Claims] (1)Return the output clock signal to the input
Feedback clock signal compared to a predetermined reference clock signal
The positions of the feedback clock signal and the reference clock signal.
By operating to eliminate the phase difference, the feedback
PLL for synchronizing a lock signal with the reference clock signal
In the method of simulating a circuit, (A) The time when the feedback clock signal changes is set as a reference time
Set as time, (B) At a certain current time, the reference clock signal
Whether there is a rising or falling change of
Judge, (C) In (B), the reference clock signal
One of the rising and falling changes
If it is determined that there is a delay,
Set a predetermined first delay value as the interval, (D) In (B), the reference clock signal
It is determined that there is a rising or falling change.
If the connection is interrupted, the difference between the current time and the reference time is calculated.
Set as an additional delay value, and
A second delay value equal to the sum of the first delay value and the delay time
Set as (E) the delay set in (C) or (D)
The output clock is delayed by the time from the current time.
Schedule a change in the traffic light to occur Specially
PLL circuitsimulationMethod. (2)Return the output clock signal to the input
Feedback clock signal compared to a predetermined reference clock signal
The positions of the feedback clock signal and the reference clock signal.
By operating to eliminate the phase difference, the feedback
PLL for synchronizing a lock signal with the reference clock signal
In the method of simulating a circuit, (A) The time when the feedback clock signal changes is set as a reference time
Set as time, (B) At a certain current time, the reference clock signal
Whether there is a rising or falling change of
Judge, (C) In (B), the reference clock signal
One of the rising and falling changes
If it is determined that there is a phase difference, Delay
Set a predetermined first delay value as the interval, (D) In (B), the reference clock signal
It is determined that there is a rising or falling change.
If the connection is interrupted, the difference between the current time and the reference time is calculated.
Set as an additional delay value, and
A second delay value equal to the sum of the first delay value and the delay time
Set as (E) the delay set in (C) or (D)
The output clock is delayed by the time from the current time.
Schedule a change in the traffic light, (F) Whether the frequency of the reference clock signal changes
The frequency of the reference clock signal changes.
If it is determined that there is, the reference clock signal and the
Determines whether the feedback clock signal is synchronized, (G) In the above (F), the reference clock signal and
When it is determined that the feedback clock signal is synchronized
Is the current time for the delay time set in (D).
The output clock signal changes at a time delayed from the time.
Schedule like this, (H) In (F), the reference clock signal and
When it is determined that the feedback clock signal is not synchronized
The reference time set in (A) and the reference time
Clearing the additional delay value set in (D),
(C) from the current time by the delay time set in
A change in the output clock signal occurs at a delayed time.
Schedule to PLL circuit characterized in thatStain
SimulationMethod. . 3. The method according to claim 2 , wherein the feedback clock signal is generated at the reference time.
In the case of a rising change, in the above (B),
Judge that there is a rising change of the reference clock signal
And the feedback clock signal falls at the reference time.
In the case of a change, in (B), the reference
2. The method according to claim 1 , wherein it is determined that there is a falling change of the lock signal.
Or the simulation method of the PLL circuit according to 2. 4. The reference clock signal and the feedback clock.
The reference clock starts from the time when each of the lock signals changes.
Clock signal and the feedback clock signal are synchronized
The lock signal
Simulation method of the PLL circuit according to any one of claims 1 to 3 scheduled to output. Claim 5.Return the output clock signal to the input
Feedback clock signal compared to a predetermined reference clock signal
The positions of the feedback clock signal and the reference clock signal.
By operating to eliminate the phase difference, the feedback
PLL for synchronizing a lock signal with the reference clock signal
In the method of simulating a circuit, (A) The time when the feedback clock signal changes is set as a reference time
Set as time, (B) At a certain current time, the reference clock signal
Whether there is a rising or falling change of
Judge, (C) In (B), the reference clock signal
One of the rising and falling changes
If it is determined that there is a delay,
Set a predetermined first delay value as the interval, (D) In (B), the reference clock signal
It is determined that there is a rising or falling change.
If the connection is interrupted, the difference between the current time and the reference time is calculated.
Set as an additional delay value, and
A second delay value equal to the sum of the first delay value and the delay time
Set as  (E)Count the number of input clocks of the reference clock signal
The number of input clocks exceeds the specified value.
Judge (F) In (E), the number of input clocks is
If it is determined that the specified value has not been exceeded,
(C) from the current time by the delay time set in
A change in the output clock signal occurs at a delayed time.
Schedule to (G) In (E), the number of input clocks is
If it is determined that the value exceeds the specified value, the above (C)
Or the current time by the delay time set in (D).
The output clock signal changes at a time later than
Schedule to PLL circuit characterized by the following:
ofsimulationMethod. 6. The feedback clock signal at the reference time
In the case of a rising change, in the above (B),
Judge that there is a rising change of the reference clock signal
And the feedback clock signal falls at the reference time.
In the case of a change, in (B), the reference
6. The method according to claim 5 , wherein it is determined that there is a falling change of the lock signal.
3. The simulation method of a PLL circuit according to 1. 7.And (H) the reference clock signal.
It is determined whether there is a change in the frequency of the reference clock.
If it is determined that there is a change in the frequency of the
The reference clock signal and the feedback clock signal are synchronized.
Or not, (I) In the above (H), the reference clock signal and
When it is determined that the feedback clock signal is synchronized
Is the current time for the delay time set in (D).
The output clock signal changes at a time delayed from the time.
Schedule like this, (J) In the above (H), the reference clock signal and
When it is determined that the feedback clock signal is not synchronized
The reference time set in (A) and the reference time
Clearing the additional delay value set in (D),
(C) from the current time by the delay time set in
A change in the output clock signal occurs at a delayed time.
Schedule to The PLL times according to claim 5 or 6.
On the roadsimulationMethod. 8. The reference clock signal and a feedback clock signal.
From the time when each of the clock signals changes
Signal is synchronized with the feedback clock signal.
Lock signal is issued when it is determined that synchronization has been established.
The simulation method for a PLL circuit according to claim 5 , wherein the scheduling is performed so as to perform the simulation . 9. A change in a signal of a logic circuit including a PLL circuit.
Registered as an event, said registered events extracted in time series, the extracted event to identify changes to the circuit cell of the input signals, simulation of the specified circuit cells
Run the configuration, if any change in its output signal
In the logic simulation method to register as a new event, extracted the event is input to the PLL circuit
At least the reference clock signal and feedback clock signal
When the input signal changes,
The PLL circuit is specified as a path cell, and the PLL circuit
According to the simulation to claim 1
Execute using the PLL circuit simulation method, and
Output clock of the PLL circuit
A logic simulation method , wherein a change in a lock signal is registered as the new event .