JP3055031B2 - A microprocessor that performs selectable alignment checking on memory references. - Google Patents

Description

The present invention relates to the field of semiconductor microprocessors.

[Problems to be solved by conventional technology and invention]

The present invention addresses a scheme for performing an alignment check function controlled by "mode bits" inside a microprocessor. Using this concept, a programmer can choose whether a fault will be generated if a memory reference is to an unaligned address. The presently preferred embodiment of the present invention is incorporated into the architecture of an Intel 80486 microprocessor, also known as a 486 ^™ processor. The 486 ^™ microprocessor is an improvement on Intel's 80386 microprocessor, also called the 386 ^™ processor. (Intel, 80386, 386, 80486 and 486 are Intel Corp.
oration is a trademark. The 80486 microprocessor is a 32-bit high-performance processor, a type of X86 series processor. It is compatible with the 80386 processor for object code. Therefore, the 80486 processor is
It can execute code developed for earlier processors in this series. In general, the 80486 microprocessor is a re-implementation of the 80386 architecture with the goal of improving performance by at least 2.5 times as measured by the average number of clocks per instruction. The present invention represents one such feature of the 80486 microprocessor that assists in this performance enhancement.

As described above, the present invention provides the microprocessor with the ability to select whether a fault occurs if a memory reference in the program is to an unaligned address. Add. Conventionally, one data address is considered aligned if the address is a multiple of the data length. 1
Byte data is always aligned. Two-byte data is aligned if its address is a multiple of two.
Four bytes of data are aligned if the address is a multiple of four. The same applies to data having other lengths. Thus, when the address is a multiple of the size of the data, the data is generally aligned.

Given the microprocessor's internal memory architecture, the importance of aligned memory references becomes apparent. In many computers, the memory is organized such that the data size is equal to the width of the memory. If the memory is organized in 32 bits, a 32-bit item having an address that is a multiple of 4 can be accessed in one memory clock cycle. (32-bit words are often referred to as doublewords or d-words-one d-word is made up of four separate bytes, for example, 0, 1, 2 and 3). In both cases, data can be referred to at any address. If the references are not aligned, the microprocessor suffers a performance penalty. This manifests itself as a situation where accessing or referring to data requires additional memory cycles.

Consider the case where a 32-bit d word starting at address 3 is referred to in memory. In the conventional method, the processor refers to two d words. That is, one would first refer to the d word starting at address 0 to retrieve byte 3, and then refer to the d word starting at address 4 to retrieve the remaining bytes 4, 5, and 6. After accessing the required bytes, the processor in some way joins the bytes together to form a data item,
Reorganize memory references. That is, the conventional method reconstructs, or "joins," at least two points: (1) at least two additional memory cycles are required, and (2) the data item to a new storage location. It is disadvantageous in that.

In order to avoid this disadvantage, several alternatives have been attempted. For example, at 80386, an alignment check can be performed for each memory reference by inserting inline code that proceeds through it. This code generates an address to the register, which in turn masks the lower bits of the register. The masking operation is achieved by taking the same register component and applying an alignment displacement. Basically,
To advance each memory reference using this method, a series of three separate instructions must be executed. In normal programs, this represents an unacceptable overhead, since half of those instructions refer to memory in some way. That is, performance degrades by 20 to 30 percent.

Some machines require all memory references to be aligned, the most prominent of which is the new RISC processor. Such a machine always fails when referring to unaligned data. However, failures are not always selectable, so failures will always occur. This is a problem because many non-artificial intelligence environments (particularly COBOL) benefit from the ability to reference unaligned data. In other types of machines, unaligned references are possible, but with the aforementioned performance degradation. Such machines include the Intel 80386, Digital VAX and IBM370. Therefore, what is needed in the art is a new method of failing for addresses that are not arbitrarily aligned, without the performance penalties described above.

As will be apparent from the following description, the present invention provides a means for performing an alignment check that is user selectable and requires no additional instructions. In addition, the present invention supports masking at two masking levels for the alignment inspection procedure: the application level and the operating system level. Since it is possible to mask the trap or the fault itself,
The present invention will give the user two opportunities to control the alignment inspection.

Accordingly, it is an object of the present invention to provide a means for detecting a state where data is not aligned accidentally. For program debugging, aligning data significantly improves performance.

It is another object of the present invention to use the lower address bits to identify the type of pointer, and then use a small displacement to "adjust" those tag bits to obtain an aligned address. To provide a means for generating an alignment fault in an artificial intelligence (AI) program. The present invention performs pointer type checking without significant performance degradation. Experimental measurements have shown that the present invention achieves a 30% performance improvement for an average AI program running on an 80386 microprocessor. Another study has shown a 20 percent improvement on other machines.

[Means for solving the problem]

A microprocessor including means for detecting unaligned data references is described. The detection means is selectable such that when a reference is made to a data object that is enabled and not aligned, a fault is generated that interrupts the current execution of the program. The detection means is part of the microprocessor segmentation device described herein. In the preferred embodiment, the microprocessor further has a protection mechanism that allows access to some data objects at various privilege levels.

The detecting means includes two mode bits stored in the microprocessor. The first mode bit performs fault masking at the lowest privileged execution level (ie, application level), and the second mode bit performs fault masking at the highest privilege level (ie, operating system level). Perform the masking of Therefore, access to the mode bit, ie, the mask bit, is performed at two different levels. The two mode bits must both be set to "1" when the detection means are to be enabled. The use of two separate mode bits to optionally enable alignment checking provides the best programming flexibility.

〔Example〕

The present invention will be more fully understood from the detailed description of the preferred embodiments thereof given below and the accompanying drawings. However, the description of the preferred embodiments, and the accompanying drawings, are not to be construed as limiting the invention to any particular embodiment, but are merely provided to aid explanation and understanding.

A microprocessor is described that includes means for selecting whether or not a fault should occur whenever an unaligned memory reference is detected. In the following description, for the purpose of providing a thorough understanding of the present invention, numerous details, such as specific bit lengths, register contents, and logic diagrams, will be identified and described in detail in practicing the invention. It will be obvious to one skilled in the art that it is not necessary to employ any particular detail. Also,
In other instances, well-known structures and circuits have not been shown in detail in order not to unnecessarily obscure the present invention.

Before describing the detailed embodiments, it is helpful to understand the present invention first to consider some architectural features of the 80486 microprocessor.

Basic Microprocessor Architectures As computers play an increasingly important role in our society, more and more microprocessors implement protected virtual address mode (protected mode).
The protected mode built into the 80486 microprocessor allows multiple applications to run at the same time, but keeps the applications together so that a failure in one application does not affect other applications. Isolated. The central feature of the protection mechanism is the selector. The program does not directly access any part of the system, but rather a selector that allows access to one system object. For each object, there is information associated with it, for example, information about the location, size, usage restrictions, etc. of the object. In the 80486 microprocessor, only the operating system accesses data referenced by a selector called a descriptor.

The descriptor describes the system object in detail. A memory segment is a type of system object.
Other system objects include tables that support protection mechanisms and special segments that store processor state. By examining the selector, the hardware determines which descriptor the selector is associated with and determines the object to which the descriptor points. One of the items indicated by the descriptor is the privilege level of the object. When a program requests access to an object by a selector, access is denied (if the request violates the rules of the protection mechanism, control is passed from the program to a designated routine in the operating system). Migrate), or access is granted but not granted (eg, if the object is not currently in memory, the operating system routine swaps the object into memory and returns control to the program). Access is granted at the requested privilege level.

The 80486 processor supports four gradually increasing privilege levels, numbered 3,2,1,0 as shown in FIG. Privilege level 0 is the highest privilege level. The selector privilege level in the code segment (cs) register identifies the priority of the currently executing routine and is called the current privilege level (CPL). To maintain reliability, only the most trusted code of the operating system runs at the highest privilege level (CPL = 0). Applications that may fail are run at the lowest level (CPL = 3). FIG. 1 shows the various privilege levels as a series of concentric rings. (The term privilege implies a right or interest not normally granted. In an 80486 microprocessor, the procedure of running on the innermost link can access data objects on the outer ring, but not on the outer ring. Link procedure cannot access objects in the inner ring with greater privileges.) As will be described in further detail below, the present invention provides that the alignment check function can be performed at the application level (eg, CPL =
3) and operating system level (for example,
CPL = 0). The ability to select masking at two different privilege levels thus allows the present invention to be compatible with machines that either always trap when referring to unaligned data or do not trap at all. ing. For example, at the operating system level, disabling the alignment check function at reset can help
Compatibility with the 80386 microprocessor may be provided.

In some programming languages, such as C or Pascal, when a data type is declared at compile time, the selector is permanently tagged with that data type. In other words, the data type does not change during the execution of the program. However, some AI languages, such as LISP or Prolog, provide more flexibility in assigning run / time types. In such a language, the data type may change as the program executes. For this reason, the user must use a function that operates on multiple types (for example, when X is an integer, a short real number, a long real number, a complex number, etc.) Can be defined. Therefore, a plurality of functions can be executed according to the type of data at a specific point in the program.

In LISP or Prolog programs, the pointer field indicates both the address and the type of data. Items that identify the type of data are called tags.
The programmer uses the least significant two bits of the 32-bit pointer as the most significant tag bit. Data type 1
If the type must be one or the operation is invalid, or if the programmer expects the type of data to be one type that is by far the most frequent type, the user must Code can be generated that assumes a value. This code cancels the lower tag bit. For example, if the tag has a value of 2, the code would add a value of -2 to offset the tag bit. This offset or cancellation is also known as a displacement. If the displacement is correct, the memory items are aligned and the data can be referenced without failure or trap.

When running an AI program using the present invention, the memory references are aligned as long as the displacement is aligned with the tag. However, if the displacement does not match the tag,
The alignment inspection apparatus of the present invention arbitrarily causes traps or failures. When this happens, the current execution location (CS: EIP)
And the contents of the flag register (EFLAGS) are saved on the stack, and control transfers to a software routine known as an interrupt handler. There is one specific interrupt number associated with each fault condition. The instruction pointer saved in the stack points to the instruction that caused the failure after the failure occurred. Thus, the operating system can correct the condition and resume the execution of the program.

FIG. 4 is a general block diagram of the microprocessor. FIG. 4 shows a microprocessor according to the present invention incorporating the above-described alignment inspection function in the form of a general block diagram. The microprocessor includes a bus interface device 10 coupled to a 32-bit external data bus 30 and further coupled to an address bus 31 and some other control lines. Since only the physical (hardware) address is handled by the bus interface device 10, the operand address is
First, the segmentation device 14 and the paging device 13
And must pass through. Further, a cache device 12 and a prefetch device 11 are also connected to the bus interface device 10. The look-ahead device is constantly adjusting to the bus interface device to retrieve the contents of the memory at the next instruction address. As soon as the prefetch device receives the data, it inserts the data into a queue and, if the queue is not full, requests another 32 bits of memory content.

The cache device 12 includes a data cache and a controller that controls access to the cache memory. The prefetching device 11 and the cache device 12 are both
It is coupled to the segmentation device 14 via a 32-bit bus. The segmentation device 14 converts a segmented address (segmented address) into a linear address.

The segmentation device 14 has a “LA (ie, Line
The paging device 13 via a 32-bit linear address bus 20, also called an "ar Address (linear address) bus"
And the cache device 12. Paging device 13 takes the linear addresses generated by segmentation device 14 and translates them into physical addresses. If paging is disabled, the linear address of the segmentation device becomes the physical address. When paging is enabled, the linear address of the 80486 microprocessor is stored in multiple 40
Divided into 96 byte blocks. Each page can be mapped to a completely different address. For the sake of understanding the invention, for convenience, a segmentation device
It may be assumed that 14 is the same device used in a commercially available Intel 80386 microprocessor. Intel 80
The 386 microprocessor segmentation and paging devices are described in co-pending application filed June 13, 1985, application number 744,389, entitled "Memory Management fo
r Microprocessor ", assignee is the same as the present invention.

In the microprocessor, the instructions are sent to the instruction decoder unit 15
Is combined with The decoder device operates the same as the prefetch device, fetching individual bytes from the prefetch queue,
Determine the number of bytes required to complete the next instruction. The decoder device operates in conjunction with the controller 19, which stores the microcode instructions and provides a plurality of control signal sequences to the microprocessor. The instruction decoder unit 15 is shown coupled to a control unit 19, which is shown coupled to a segmentation unit 14, a data unit 18 and a floating point unit 17. Data device 18 is Inte
l An arithmetic and logic unit (ALU) that performs ALU functions in a manner similar to the ALU functions performed by the 80386 processor.

The microprocessor further includes a floating point device 17 for performing floating point operations. The exact construction of the floating point unit 17, as well as other units of the microprocessor, is not important to understanding the present invention. The signal flow between the various devices of the microprocessor will now be described only as necessary to understand the invention.

Description of the Preferred Embodiment The selectable alignment tester of the present invention appears to the programmer to appear to the programmer as two new state (mode) bits. One bit is located in the EFLAGAS register and is called the AC (alignment check) bit. EFLA
The GS register holds state information about the current instruction stream (the EIP register stores the address of the currently executing instruction), as well as some fields associated with various different instructions. The other bit, called the AM (alignment masking) bit, is located in the control register CRO.

Next, the details of the EFLAGS register will be described with reference to FIG. (Note that the flag bits 1, 3, 5, 15, and 19 to 31 are undefined.) The AC bit is located at the bit position 18. The AC bit enables the occurrence of a fault if the memory reference is an unaligned address. For example, this can be a word access to an odd address, or O
D word access to an address other than MOD4, or O MO
It can be considered caused by an 8-byte reference to an address that is not D8. Alignment faults occur only at level 3. That is, at levels 0, 1, and 2, AC
Bit settings are ignored (implicitly 0). A reference to the descriptor table (with respect to the selector load) is an implicit level 0 reference, even if the instruction that "emits" the descriptor table is executed at level 3. In the preferred embodiment, alignment failures are reported via interrupt bit 17 with an error code of zero. (Bit 17 is a virtual mode (VM) bit that, when set to 1, indicates that the currently executing instruction stream is X86 code.) The following table shows the various data types of the microprocessor. 3 shows the required alignment for.

Since the alignment check function must be enabled separately for each task, this function is included in the EFLAGS register because each task has its own "copy" of "EFLAGS".

Next, FIG. 3 will be described. FIG. 3 shows a control register (CRO) for storing the alignment mask control bit (AM). The control register CRO is one of several control registers that regulate the paging and numerical coprocessor operation of the microprocessor. As shown in FIG. 3, the alignment mask control bit is at bit position 18 of the CRO. The AM bit controls whether the AC bit in EFLAGS can tolerate an alignment fault. When AM = 0, the test is disabled (eg, 80386 microprocessor compatibility), but when AM = 1, the test is enabled. AM bits are accessible only at privilege level 0, and probably only by the operating system. The operating system sets this bit to one to enable alignment faults only if it contains the appropriate interrupt handler.

Great flexibility is obtained by using two bits to enable alignment checking. The AM bit is located in the register CRO, which is global for all tasks, so it controls the operating system globally and can only be referenced by the operating system. It is. If the operating system includes a suitable interrupt handler (eg, bit 17 of the CRO), the AM bits are normally set when the operating system is initialized.

The AC bits perform application level control. This bit is in the EFAGS register, which is swapped at the task switch and is accessible by the application running at level 3. Since EFLAGS are swapped in the task switch, each task has its own dedicated EFLAGS
It looks as though it has a copy of the GS, and therefore has its own copy of the alignment checker. Usually, the AI program only needs to execute the alignment check at level 3, that is, at the application level. By allowing access to the two mask bits, the programmer has two opportunities to select whether an alignment check is to be performed, i.e., at the application level (by clearing or setting the EFLAGS register programmatically). And the opportunity at the operating system level (AM bit is cleared or set). Note that both bits perform masking at all levels. However,
AC is implicitly masked at all levels except level 3, but the AM bit can only be set / reset (ie, controlled) at level 0.

The alignment checker of the present invention is realized mainly by recognizing access to unaligned data. This is performed according to an instruction by the instruction decoder unit 15 or the control unit 19, using the lower three bits of the 32-bit linear address bus 20 (see FIG. 4) and the length of the bus cycle. Failure due to reference to unaligned data
The linear address is also generated in the segmentation device 14 where it is also generated. The fault is serviced by the controller 19.

The following table defines the access of unaligned data in relation to the values of the lower three bits of the LA bus 20 for bus cycles of different lengths. The length of the bus cycle is determined by decoding the "bus request type" field from the instruction decoder unit 15 or the control unit 19.

Once it is determined that an unaligned access has occurred, it is relatively easy to determine other conditions necessary to cause a failure. Referring to FIG. 5, FIG. 5 shows a circuit diagram of the alignment check logic circuit. Logic gates 40-44 and latches 41 and 45 are connected to segmentation device 14 to ensure that segmentation device 14 is driving LA bus 20 and that the bus cycle is not aborted. Used for decoding received signals. The three least significant bits of the LA bus 20 appear on signal lines 51-53. These signals are combined at the input terminals of gates 46 and 69 with a bus request type field signal from the instruction decoder unit 15 or the control unit 19. Generally, gates 46, 48, 49 and 67-72 are combined
It generates a series of signals indicating the byte length of the references that are not aligned according to Table 2. For example, gate 46 generates a two-byte unaligned reference signal on signal line 80; gate 67 generates a four-byte unaligned reference signal on signal line 81; Gate 71 generates an 8-byte signal indicating an unaligned reference on signal line 82; gate 49 generates a 4ND signal indicating an unaligned reference on signal line 839. The signals on the signal lines 80 to 83 are ORed by the gate 47, and the result is stored in the latch 50. (The symbols P1 and P2 related to the latch in FIG. 5
Indicates the phase at which each latch is clocked. For example, latches 41 and 59 are clocked at phase 2 of the system clock, while latches 45, 50 and 62 are clocked at phase 1 of the next clock pulse. The AM and AC bits appearing on signal lines 54 and 55 are
Input to D gate 57. Both bits must be "1" to cause a misalignment failure. The output of gate 57 is ANDed at gate 63 with the outputs of latches 45 and 50, along with the privilege level of the program supplied to signal line 56. The privilege level in the presently preferred embodiment must be level 3, as determined by the CPL bits of controller 19. Gate
58-62 provide further inputs to AND gate 63 to ensure that the type of bus cycle is of the type that allows AC violations. (An AC violation is not allowed in a certain cycle. For example, since a branch cycle is a 1-byte cycle by definition, an AC violation is not allowed in a branch cycle.) The output of the gate 63 is one input of the AND gate 65. Connected to terminal. The other input to gate 65 is derived from signal line 66 which provides a signal indicating that the microprocessor's pipeline is open before a fault signal is generated. In short, in addition to the AND operation of the AC and AM bits, the logic of FIG. 5 ensures that no access is being made to any system segment and that the proper bus cycle is being performed. Designed to guarantee. The AND gate 65 generates a signal called SINTR (segmentation device interrupt) on the signal line 67. This signal is coupled to the controller 19 whenever all of the above conditions are met.

As soon as the controller receives the SINTR, it stops all execution and takes action to service this alignment check failure. The controller inserts two no-operation (NOP) blocks and then pushes the microcode to the entry point for the alignment check failure. Thereafter, the microcode stores the return address and takes over all the necessary work to notify the user program of the failure.

Thus, a microprocessor that performs a selectable alignment test has been disclosed.

[Brief description of the drawings]

FIG. 1 shows the four privilege levels provided by the microprocessor according to the invention, the highest protection level being level 0 and the least protection level being level 3. FIG. Are extra bits (AC bits) defined in the upper 16 bits, which are arranged inside the microprocessor according to the present invention and support a failure when accessing unaligned data at privilege level 3. FIG. 3 shows the EFLAGS register having EFLAGS.
FIG. 4 shows a machine state control register (CRO) for storing an alignment mask bit (AM) for controlling whether or not an AC bit in the GS can tolerate an alignment fault. FIG. FIG. 5 is a diagram showing how alignment checking is logically implemented in the presently preferred embodiment of the present invention. 10 ... bus interface device, 11 ... prefetching device,
12 ... Cashing device, 13 ... Paging device, 14 ...
Segmentation device, 15 …… Instruction decoder device, 17
… Floating point device, 18… Data device, 19… Control device, 20… 32 bit linear address bus, 30… 32 bit external data bus, 31… Address bus.

Continuation of the front page (56) References JP-A-54-129934 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 12/14

Claims (3)

(57) [Claims] An operating system for controlling the operation of a computer system, comprising: a processing unit for executing a program according to a protection mechanism having a plurality of privilege levels from a highest privilege level to a lowest privilege level; The program is executed at a current privilege level that specifies the priority of the program at the memory unit, the memory unit being coupled to the processing unit to store data, the memory unit being stored at an address defined by the program. Reference means for referring to data stored in the memory, the reference means being controlled by the processing unit, and an alignment fault when a memory reference defined by the program is directed to an unaligned address. A first bit accessible from the lowest privilege level and selectively enabling the generation of an alignment fault, and a first bit accessible from only the highest privilege level and controlling the occurrence of a global alignment fault. A computer system, comprising: means for controlling the occurrence of an alignment fault, including a second bit that is selectively enabled. 2. A control unit comprising a hierarchy of privilege levels from an operation level to an application level, the control unit executing a program according to a protection level allowing selective access to an object, wherein the control unit executes the program in the computer system. The program is executed at a current privilege level for specifying a priority of the program, the memory unit coupled to the control unit to store data, and the data stored in the memory unit at an address determined by the program is stored. Reference means coupled to said control means, said reference means coupled to said control means, comprising: a segmentation unit for converting a segmented address into a linear address, said segmentation unit comprising: Means for detecting a reference to unaligned data; means for controlling the occurrence of an alignment fault when a reference to unaligned data is detected; Means for controlling the occurrence of an alignment fault, including a first bit selectively enabling the generation and a second bit accessible only from the operation level and selectively enabling the generation of a global alignment fault. A computer system comprising: 3. The privilege level for executing an instruction is level 0.
A microprocessor device having a memory request generation system for generating a memory request, the memory request generation system also performing an alignment check for the memory request, and a privilege level 3 A flag register that can be written by an instruction executed at privilege level 0, the flag register includes an alignment check bit that enables an alignment fault to occur, and can be written by an instruction executed at privilege level 0. A control register that cannot be written by an instruction executed at privilege level 3, wherein the control register includes a masking bit and is coupled to receive the contents of both the flag register and the control register. The flag register and the control register are both set. Logic circuitry for generating an enable signal only when the enable signal is coupled to the memory request generation system to generate an unaligned memory request and to generate an alignment fault if the enable signal occurs. A microprocessor device configured as described above.