DE4010733C2 - Microprocessor with means for detecting misaligned data calls - Google Patents

Description

The invention relates to a microprocessor according to the preamble of claim 1.

A microprocessor of the type mentioned is, for example, the Microprocessor 80486 of the company Intel, which is an advancement or improvement of the Intel microprocessor 80386 represents.

The 80486 microprocessor is a 32-bit high-performance processor from the processor family x86. It is object code compatible with the 80386 processor. As a result, he can process codes, for the previous members of this family have been developed. Generally it is a new implementation the 80386 architecture for the purpose of improvement at least 2.5 times the power measured by the average number of clocks per command. The invention ceases Such a feature of the 80486 microprocessor is to improve performance contributes.

When accessing the one coupled to the microprocessor Memory becomes a specific one storing a data unit Memory address addressed. By convention, an address applies a data unit as aligned if it is a multiple the length of the data unit. A one-byte data unit is always aligned. A two-byte data unit is aligned if their address is a multiple of two. A four-byte data unit is aligned if its address is a multiple of four, etc. So data is general aligned if the address is a multiple of their size. Accesses to addresses that do not coincide with the beginning of the data units match, are called misaligned.  

The meaning of aligned memory accesses becomes even clearer when looking at the internal memory architecture a microprocessor. In most Computers, the memory is organized so that the data size is equal to the memory width. If you have a memory Organized with 32 bits, this means that you are within one Memory clock cycle 'can access a 32-bit unit whose Address is a multiple of four. (A 32-bit word will often referred to as a double or D word, with a D word off four separate bytes, e.g. B. 0, 1, 2 and 3). Both the 80386 and 80486 CPUs provide access to data at any addresses. If the access is not aligned is, the microprocessor suffers a performance degradation, which manifests itself in that additional memory cycles for the Access or the call of the data are needed.

It is the case of a memory access to a 32-bit D Word, starting at the address 3, considered. In earlier conceptions the processor called 2 D-words; first the D word starting at address 0 to extract byte 3, then the D word starting at the address 4 to extract the remaining bytes 4, 5 and 6. After accessing the required Bytes, the processor somehow puts them together around the To reconstruct the data unit or memory call. Therefore known solutions suffer at least two penalties: (1) The The need for at least two additional memory cycles; and (2) a reconstruction or "composition" of the data unit at a new storage location.

To avoid this shortcoming, some have become alternative Proposed solutions. So can in the 80386 processor Alignment tests, for example by inserting an in-line code Initially, each memory access is performed. This Code generates an address in a register and then hides the lower bits of the register. The masking operation becomes implemented by having the same register components  takes and adds an alignment shift. Basically must using this approach a series of three separate Instructions are executed preliminarily to each memory access. Since half of the commands of a typical program in any Accessing the memory, this represents an unacceptable Extra effort. It deteriorates the performance by 20 to 30%.

Some machines require the alignment of all memory accesses or addresses. This is especially true for the new RISC processors. These machines always go in one Error condition when accessing misaligned data. These Error states are selectable so that error states become invariable be generated. This is a problem, as many non-artificial intelligence environments (in particular COBOL) benefit from the ability to focus on misdirected Access data. Another machine category allows misaligned references, but with the aforementioned reduction in performance. These machines include the Intel 80386, Digital's VAX and the IBM 370th

The object of the invention is a microprocessor o. G. To provide type, its efficiency at Memory access increases and that of misaligned accesses generate an error signal indicative of the miss can.

This object is achieved by a microprocessor solved with the features of claim 1.

The microprocessor according to the invention contains means for Determine access to misaligned data. The determining means are selectable such that when activated the determining means and access to a misaligned Data object, an error signal is generated, which is the execution of the current program. The determination or detection means are part of the segmentation unit of the described  Microprocessor. In a preferred embodiment the microprocessor also has a protection mechanism, the access to certain data objects on different Granted privilege levels.

The invention provides a means for alignment testing Available, which is selectable by the user and no additional Commands needed. The invention supports two levels of masking for the alignment check: one on the application level and the other at the operating system level. With the ability for masking the trap or the error state itself The invention gives the user two options for control the alignment test.

The determining means comprise two mode bits which are in the microprocessor are stored. The first mode bit sets a Masking of the error signal at the execution levels with the lowest privilege (ie the user level), while the second mode bit masking the error signal at the highest privileged level (ie the operating level) creates. Therefore, access is to the mode or mask bits provided at two different levels. Both Mode bits must be set to "1" to the detector means to activate. The use of the mode bits for optional activation the alignment check gives the optimal programming flexibility.

With the help of the invention also alignment error signals in some artificial intelligence (AI) programs which have lower order address bits to identify of pointer types and then minor shifts to "Auskorrigieren" of these flag bits and for producing a use aligned address. The invention provides a Checking the pointer type without significant performance reduction to disposal. Experimental measurements show that the invention a 30% power boost on average AI programs realized running on the 80386 microprocessor.  

Further studies have a 20% increase over other machines shown.

Advantageous developments of the invention are in the dependent claims characterized.

In the following the invention with reference to a in the drawing explained embodiment illustrated schematically. In the drawing shows

Figure 1 illustrates the four levels of privilege formed by the described microprocessor, with the safest level shown as level 0 and the least secure level as level 3;

Fig. 2 shows the EFLAGS registers arranged in the described microprocessor, each having an extra bit (the AC bit) defined in the upper 16 bits as the error carrier for accessing misaligned data in the privilege level 3;

Fig. 3 shows the machine state control register (CR0) having an alignment mask bit (AM) which controls whether or not the AC bit in EFLAGS can allow an alignment error;

Fig. 4 is a general block diagram of the preferred embodiment of the microprocessor;

Fig. 5 is a circuit diagram of the logical implementation of the alignment test in the described Ausfüh tion of the invention.

The described microprocessor has a device, which determines whether an error condition is to be generated when an error occurs directed memory access is detected. In the following The description will be accompanied by numerous special details For example special bit lengths, register contents, logic switching images, etc., given to the understanding of the present To deepen the invention. However, it is clear to a person skilled in the art that these specific details for the essence of the invention are not crucial. In other cases are known Structures and circuits are not specified in detail the description of the present invention is not unnecessary strain.

It seems appropriate, before the detailed description of Embodiment first, some architectural features of the To explain 80 486 microprocessor.

Basic microprocessor architecture

As the importance of computers in society is ongoing is growing, more and more microprocessors with a ge Protected virtual address mode (protected mode) implemen advantage. The protected built-in 80 486 microprocessor Mode allows simultaneous execution of multiple applications, However, they isolated from each other, so that interference in one application does not affect another application. The central feature of a protection mechanism is the selector. Instead of direct access to any part of the system  a program works together with a selector to access granted to a system object. Are assigned to each object Information, such as the object position, the size, Be restrictions on use, etc. In the 80 486 micropro Only the operating system has access to the selector designated data, which are called descriptor.

Descriptors describe a system object in detail. Spei chersegmente are a type of system objects. Other System objects include tables as carriers of the protection mechanism mus', special segments that store the processor state etc. By checking the selector puts the hardware which descriptor is the selector and the object to which the descriptor indicates is assigned. A feature which the descriptor is the privilege level of the object. When a program uses the selector to access an object required, access is either denied (if the request If a rule of the protection mechanism is violated, the Control from the program to a designated routine in the operating system), access is allowed but not granted (for example, if the object is currently not in memory an operating system routine must place the object in the Transfer memory and return control to the program enter) or the access will be at the requested privilege level granted.

The 80486 processor supports four levels of increasing privilege, numbered 3, 2, 1, and 0 as shown in FIG . Privilege level 0 is the highest privileged level. The privilege level of the selector in the code segment (CS) register identifies the precedence of the currently executing routine and is called the current privilege level (CPL). For reasons of reliability, only the most confidential code in the operating system runs at the highest privileged level (CPL = 0). Applications that can fail are operated at the lowest level (CPL = 3). Various levels of privilege are shown as a result of concentric rings in FIG . (The word "privilege" denotes rights or benefits that are not normally granted.) In the 80486 microprocessor, processes that operate on the inner rings can access data objects in the outer rings, while outer ring processes do not access the inner ring objects with higher ones Access privilege levels).

As will be explained in more detail below, allows the Invention the masking of the alignment test feature both the application level (eg CPL-3) as well as on the operating system stem level (eg CPL-0). This selectability of masking on two different privilege levels makes the present invention also compatible with such machines, which always encourages misaligned access or never respond. For example, on the Operating system level the alignment check feature at reset ent be enabled, making it compatible with the 80 386 microprocessor.

In some programming languages, such as C or Pascal, the selector is finally marked with the data type, if the data type is declared at compile time. In other words, the data type does not change if that Program is executed. In some AI languages, for example As a LISP or Prolog, flexibility in run / time-type is added included. In these languages may be the data type during the execution of the program. This made possible It allows the user to define a function with works several types (eg, where x is either a whole number, a short real size, a long real size, one  complex size, etc.). Therefore, depending on the data type a special item in the program has several functions be led.

In LISP or Prolog programs, the pointer field displays both the Address as well as the type of data. The feature which identifies the data type, becomes "tag" or "day". The programmer uses the lower ones both bits of a 32-bit pointer are rated as the highest ten identification tag bits. In cases where the data type must be of a certain type or the Operation is invalid, or in cases where the Pro programmer a particular type of data with overwhelming frequency expected, the user can generate a code under represents that the identifier is a given Is worth. This code eliminates the lower identifier rungskennzeichenbits. For example, if the ident If the code has a value of 2, the code would have a Value of -2 to clear the tag flags add. This offset or erase is called "displacement" known. If the shift is correct, then this is Spei aligned, and the data can without error condition or trap are called.

When running AI programs using the present memory accesses are aligned so long, like the move with the tag over the mood. However, if the shift does not coincide with the day matches, generates the alignment tester after the present the invention optionally a trap or error signal. Is this the Case, the current execution venue (CS: EIP) and the Contents of the flag registers (EFLAGS) are saved on the stack and the controls go to a software routine, over which as Interrupthandler is known. A special sub  refraction number is assigned to each error condition. The Instruction pointer after the occurrence of an error on the stack is backed up, indicates the command that verifies the error condition ursachte. The operating system can therefore correct the condition and restart the execution of the command.

Overall block diagram of the microprocessor

Referring now to Figure 4, the new microprocessor having the preferred embodiment for implementing the alignment check feature is shown as a block diagram. The microprocessor has a bus interface unit 10 which is coupled to an external 32-bit data bus 30 and additionally to an address bus 31 and some other control lines. The bus interface unit 10 processed only physical (hardware) addresses, so that operand denadressen first a segmentation unit 14 and a page forming unit 13 must go through. Also coupled to the bus interface unit 10 are a cache unit 12 and a pre-fetch 11 . The pre-fetch unit 11 constantly requests the bus interface unit to fetch the memory contents of the next instruction address. Once the prefetcher gets the data, it queues it and requests another 32-bit piece of memory if the queue is not full.

The cache unit 12 includes a data cache and a controller that controls access to the cache memory. Both the pre-fetcher and the cache unit 12 are coupled to the segmentation unit 14 via a 32-bit bus. The segmentation unit 14 translates segmented addresses into linear addresses.

The segmentation unit 14 is connected to the side of forming unit 13 and the cache 12 coupled via a 32-bit Linearadreß bus 20, which is also called the "LA-Bus" (L inear- ADDRESS). The page forming unit 13 takes the linear addresses generated by the segmentation unit 14 and converts them into physical addresses. When page formation is deactivated, the segmentation unit's linear addresses become the physical addresses. When page creation is enabled, linear addresses of the 80486 microprocessor are divided into 4096-byte blocks, called pages. Each page can be mapped to a completely different address. For the purpose of facilitating the understanding of the present invention, let it be assumed that the segmentation unit is the same as that in the Intel 80386 microprocessor.

Within the microprocessor, instructions are applied to an instruction decode unit 15 . The decoding unit works in a similar way as the pre-fetching unit. It dequeches individual bytes and determines the number of bytes needed to complete the next instruction. The decoding unit operates with a control unit 19 in which microcode instructions are stored; the control unit 19 supplies sequences of control signals to the microprocessor. The instruction decoding unit 15 is shown coupled to the control unit 19 and the latter to the segmentation unit 14 , the data unit 18 and the floating-point unit 17 . The data unit 18 is an arithmetic logic unit (ALU) which performs ALU functions in a manner similar to those of the Intel 80 386 processor.

The microprocessor also includes a floating point unit 17 for performing floating point calculations. The exact confi guration of floating point unit 17 and other units of the microprocessor is not critical to the understanding of the present invention. A signal flow between the various units of the microprocessor is only explained insofar as it seems necessary for the understanding of the present invention.

The preferred embodiment

The selectable alignment test assembly of the invention is for the programmer in the form of two new state (or Mode) bits visible from the outside. One bit is in the EFLAGS register and is called the AC (Alignment Check) bit. The EFLAGS register receives status information about the current one Command stream (the EIP register contains the address of the straight expiring command) as well as a number of fields reserved for different commands are relevant. The other bit, called AM (Alignment masking) bit, is located in the control register CR0 net.

In Fig. 2 the details of the EFLAGS register are shown. (Note that flag bits 1, 3, 5, 15 and 19 to 31 are "undefined"). The AC bit is located in bit position 18. The AC bit enables generation of error signals when memory access is made to a misaligned address. This may be effected, for example, by a word access to an odd address, a D-word access to an address other than 0 MOD 4, or an 8-byte call to an address other than 0 MOD 8. Alignment error signals are only generated at level 3 , ie the AC bit setting is ignored at levels 0, 1 and 2 (implicit 0). References to descriptor tables (for selector loads) are implicit level 0 references, even if the "causing" instructions are executed at level 3. Alignment error signals are reported in the described Ausführungsbei play on the interrupt bit 17 with an error code of 0. (Bit 17 is the virtual mode (VM) bit which, when asserted, indicates that the current instruction stream is x86 code).

The following table lists the alignment used for Mi required by microprocessor data types:

Registration requirement by data type data type alignment word 2 D word 4 short real size 4 long real size 8th temporary real size 8th selector 2 48-bit segmented pointer 4 32-bit flag pointer 4 32-bit segmented pointer 2 48-bit "pseudo-descriptor" 4 FSTENV / FLDENV safety zone 4/2 (on operand size) FSAVE / FRSTOR safety zone 4/2 (on operand size) Bit string 4

Because the Alignment Check feature is enabled separately for each task it has been included in the EFLAG register, since each Task has its own "copy" of EFLAGS.  

Referring now to Fig. 3, the control register CR 0 is shown with the alignment mask control bit (AM). The control register CR 0 is one of several control registers that govern the page generation and numeric coprocessor operation of the microprocessor. As shown in Figure 3, the alignment mask control bit is at the bit position 18 of CR 0. The AM bit determines whether or not the AC bit in EFLAGS can allow an alignment error condition. AM = 0 invalidates the test (eg 80 386 microprocessor compatibility) while AM = 1 enables it. The AM bit can only be accessed at privilege level 0. This is probably only possible through the operating system. The operating system sets this bit to 1 to enable alignment error conditions only if the operating system includes the correct interrupt handler.

The use of two bits to activate alignment tests provides a significant degree of flexibility. The AM bit provides a global OS control because it resides in register CR 0, which is globally responsible for all tasks, and can only be called by the operating system. It is typically set when the operating system is initialized, provided that the operating system includes the correct interrupt handler (eg, bit 17 of CR 0).

The AC bit causes application level control. It is located in EFLAGS-Re gister, which is swapped out at a process switch and by an application at level 3 is accessible. Since EFLAGS at a Process switching (task switch) are outsourced, is the Arbeitswei It's as if each task has its own copy of EFLAGS and thus had her own copy of the registration examiner. typically, AI programs require alignment tests only at level 3, the  User level. Due to the access to the two masks bits, the programmer has two options to set whether an alignment test is made or not; a possible at the user level (EFLAGS register can be deleted or set by the program) and one on the operating system stem level (AM bit cleared or set). Get noticed should mask both bits at all levels. However, that is AC implicite at all levels except Level 3 masked while the AM bit is only set to level 0 and can be reset (i.e., controlled).

The implementation of the alignment control according to the invention is centered around the detection of misaligned data accesses. This is done using the three lower bits of the 32-bit linear address bus 20 (see Fig. 4) and the length of the bus cycle in the order specified by the instruction decode unit 15 or the control unit 19 . Error states that are caused by misaligned data calls are generated in the segmentation unit 14 , which also generates the linear addresses. The error is served by the control unit 19 .

Table 2 below defines access to misaligned data for different length bus cycles expressed in lower three bits of LA bus 20 . Bus cycle lengths are determined by decoding the "Bus Request Type" field from the instruction decode unit 15 or the controller 19 .

Table 2

Once it is determined that a misaligned access has occurred, it is relatively easy to determine the other conditions necessary to generate an error condition. Referring to Fig. 5, a circuit diagram of the alignment check circuit will be described. Logic gates 40-44 and latches 41 and 45 serve to decode signals received from segmentation unit 14 to ensure that unit 14 drives bus 20 and that the bus cycle is not aborted. The three lowest bits of LA bus 20 appear on lines 51-53 . These signals are combined with bus request type field signals from either unit 15 or unit 19 at the inputs of gates 46 and 49 . Overall, gates 46 , 48 , 49 and 67-72 cooperate to generate a set of signals indicating the byte length of the misaligned data access as shown in Table 2. For example, gate 46 generates a signal on line 80 indicating a misaligned 2-bit access; Gate 67 generates a signal on line 81 which indicates a 4-byte mismatched access; Gate 71 generates a signal on line 82 indicating a mis-aligned 8-byte access; and gate 49 generates a signal on line 83 which indicates a misaligned 4ND access. Each of the signals 80-83 is ORed by the gate 47 and the result is stored in the latch 50 . (The symbols P1 and P2 are associated with the latches of Fig. 5 and indicate the phase in which each is clocked.) For example, the latches 41 and 59 are in phase 2 of the system clock and the latches 45 , 50 and 62 are clocked in phase 1 of the next clock pulse.)

The AM and AC bits appear on lines 54 and 55 and are applied to an AND gate 57 . To generate a misregistration error signal, both must be "1". The output of gate 57 is ANDed at gate 63 to the outputs of latches 45 and 50 along with the privilege level of the program on line 56 . The Privilegierungsniveau must be in the described embodiment, for example, at level 3, determined by CPL bits in the control unit 19th The gates 58-62 also generate an input signal to the AND gate 63 to ensure that the type of bus cycle is one in which AC breaks or violations are allowed. (AC breaks are not allowed on certain cycles, for example, they are not allowed on branch cycles because they are by definition single byte cycles.)

The output of the gate 63 is coupled to an input of the AND gate 65 . The other input of the gate 65 is the line 66 , on which a signal is pending indicating that the microprocessor pipeline is free before the error signal is generated. All in all, the logic of Figure 5, in addition to the ANDing of the AC and AM bits, is designed to ensure that no access can be made to any of the system segments and that a legitimate bus cycle is performed , AND gate 65 generates a signal called SINTR (Segmentation Unit Interrupt) on line 67 , which is applied to the control unit 19 whenever all of the above conditions are met.

Upon receipt of SINTR, the control unit stops immediately management operations and takes the appropriate steps to to serve this alignment check error. She puts two "kei ne-operation "(NOP) cycles and pushes the microcode to the Entry point for the alignment check errors. After that takes over the microcode and takes the necessary steps to do that To save return address and the user program of that To teach mistakes.

Claims (10)

A microprocessor for executing programs at different privilege levels and for use with a multi-byte organized data store
with a control unit ( 19 ), means ( 10, 12-14, 20, 30, 31 ) for accessing data stored in memory at arbitrary locations in byte width or a multiple of the byte width and a first circuit ( 46-49, 67-72 ) for detecting misalignments of data accesses, ie accesses under byte addresses that do not correspond to a multiple of the current access width (see Table 2, for example, odd-numbered word accesses),
characterized by :
a second circuit ( 54, 55, 57, 63, 65 ) responsive to detection of misalignment by the first circuit
a first module bit (AC) accessible at a first privilege level (level 3),
and a second mode bit (AM) accessible at a second privilege level (level 0),
generates an alignment error signal (SINTR) to interrupt program execution. 2. Microprocessor according to claim 1, characterized that the first privilege level is one of the lowest privilege Level (Level 3) and the second privilege level a highest privileged level (level 0).   3. Microprocessor according to claim 2, characterized the second mode bit (AM) is the first mode bit (AC) in such a way masked that the alignment error signal (SINTR) only generates when both the first mode bit (AC) and the second one Mode bit (AM) are set to a predetermined state. 4. Microprocessor according to claim 3, characterized that application programs are the least privileged Level are assigned and an operating system the highest is assigned to privileged level. 5. Microprocessor according to one of claims 1 to 4, characterized in that a segmentation unit ( 14 ) is provided for the translation of segmented addresses into linear addresses and for the storage of system segments. 6. Microprocessor according to claim 5, characterized in that the alignment error signal (SINTR) can only be generated if none of the system segments within the segmentation unit ( 14 ) is accessed. 7. A microprocessor according to claim 6, characterized in that a page forming unit ( 13 ) is coupled to the segmentation unit ( 14 ) via a bus ( 20 ) and that the page forming unit ( 13 ) converts the linear addresses into physical addresses, wherein bits of the bus ( 20 ) of the first circuit ( 46-49, 68-72 ) indicate misalignment of data access for bus cycles of various lengths. 8. Microprocessor according to one of claims 3 to 7, characterized in that it further comprises:
a flag register for storing the first mode bit (AC) to which a command executed at the lowest privileged level (level 3) can be written; and
a control register (CR 0) for storing the second mode bit (AM) which can be written with a command executed at the highest privilege level (level 0) but at the one with the lowest privilege level (level 3) Command can not be written;
and that the second circuit is connected downstream of the flag register and the control register (CR 0) so as to be able to receive the first mode bit (AC) and the second mode bit (AM) from these registers to generate an enable signal only if both of the first mode bit (AC) and the second mode bit (AM) are in a predetermined state, and generates the alignment error signal (SINTR) when a misalignment of a data access is detected and the enable signal is present. 9. Microprocessor according to one of claims 3 to 8, characterized characterized in that the first mode bit (AC) and the second Mode bits (AM) are in the predetermined state when their values One are. 10. Microprocessor according to one of claims 1 to 9, characterized in that with the microprocessor, an external bus ( 30 ) is coupled, are retrievable via the data.