JP3052982B2 - Clock signal phase stabilization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal phase stabilizing circuit for stabilizing the output phase of a nonlinear amplifier which receives and amplifies a clock signal.

[0002]

2. Description of the Related Art Conventionally, as a clock signal phase stabilizing circuit of this kind, as shown in FIG.
Is known in which an attenuator 52 is provided on the input side. In this clock signal phase stabilizing circuit, the attenuator 52 attenuates the amplitude of the input clock signal to make the amplitude of the input signal to the non-linear amplifier substantially constant, thereby reducing the phase fluctuation of the output signal from the non-linear amplifier 51 Was reduced.

[0003]

However, in the conventional clock signal phase stabilization circuit, when the amplitude fluctuation of the input clock signal occurs in the nonlinear amplifier such as the clock signal direct multiplication circuit and the timing extraction circuit, the amplitude fluctuation is reduced. There is a problem that the output phase changes accordingly.

An object of the present invention is to provide a clock signal phase stabilizing circuit capable of reliably preventing a change in the output phase of a nonlinear amplifier.

[0005]

According to the present invention, in order to solve the above-mentioned problems, the amplitude of an input clock signal is changed.
Variable amplitude circuit that outputs the output signal and the output terminal of the variable amplitude circuit
Signal distribution that distributes clock signals connected to
And one output terminal of the clock signal distributor.
A peak detection circuit for detecting the peak of the clock signal
Voltage control connected between peak detection circuit and variable amplitude circuit
And a first terminal to which a clock signal is inputted
Connected to the second terminal, the third terminal and the clock signal distributor
Constant type having a fourth terminal which is a selected output terminal
Between the second terminal and the reference potential terminal
Connected first capacitor, third terminal and reference potential
A second capacitor connected in series between the
Equipped with a variable capacitance diode, the voltage control circuit has an output terminal
Connects to the connection point between the second capacitor and the variable capacitance diode.
Variable circuit according to the detection value of the peak detection circuit
The output of the variable amplitude circuit is
Clock signal level characterized by keeping the amplitude of force constant
A phase stabilization circuit is provided.

[0006]

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. As shown in FIG. 1, a clock signal phase stabilizing circuit of the present invention distributes a clock signal which is connected to an output terminal of the variable amplitude circuit 1 for changing the amplitude of an input clock signal. A clock signal distributor 2, a non-linear amplifier 3 connected to one output terminal of the clock signal distributor 2 for amplifying a clock signal, and a second output terminal of the clock signal distributor 2. The circuit includes a peak detection circuit 4 for detecting a peak of a clock signal, and a voltage control circuit 5 connected between the peak detection circuit and the amplitude variable circuit.

First, the variable amplitude circuit 1 will be described. As shown in FIG. 1, the amplitude variable circuit 1 is connected to a first terminal T1, a second terminal T2, a third terminal T3, and the clock signal distributor 2 to which the clock signal is input. A distributed constant type directional coupler 6 having a fourth terminal T4 which is an output terminal; and between the second terminal T2 of the directional coupler 6 of the directional coupler 6 and a reference potential terminal. , And a second capacitor 8 and a variable capacitance diode 9 connected in series between the third terminal T3 and the reference potential terminal.

As shown in FIG. 2, the directional coupler 6
Includes an inductance coil 10 connected between the first and second terminals T1 and T2, an inductance coil 11 connected between the third and fourth terminals T3 and T4, First and third terminals T1, T
3; a capacitor 13 connected between the second and fourth terminals T2 and T4; and a capacitor 13 connected between the first and fourth terminals T1, T2 and T4.
3, resistors 14, 15, 16, and 17 respectively connected between T4 and the reference potential terminal.

Now, the first and second capacitors 7 and 8 each have a capacitance C, the inductance coils 10 and 11 each have a self inductance L, a mutual inductance M, and 1
4, 15, 16, and 17 each have a resistance value R.

The clock signal input to the first terminal T1 of the directional coupler 6 is distributed to the second terminal and the third terminals T2 and T3 but is not transmitted to the fourth terminal T4. . The condition is given by the following equations (1) and (2).

[0012]

(Equation 1)

(Equation 2)

The second terminal T from the first terminal T1
2 and the attenuation Loss (T1-T3) when transmitting from the first terminal T1 to the third terminal T3 are expressed by the following equations (3) and (4), respectively. Given by

[0014]

(Equation 3)

(Equation 4)

The phase φ (T1−T2) of the transmission signal when transmitting from the first terminal T1 to the second terminal T2 and the transmission signal when transmitting from the first terminal T1 to the third terminal T3 (T1−T3) is given by the following equations 5 and 6 based on equations 3 and 4, respectively.

[0016]

(Equation 5)

(Equation 6)

Accordingly, the phase difference φ between the output terminals of the directional coupler 6 can be obtained by the following equation (7).

[0018]

(Equation 7)

Therefore, the phase difference φ between the output terminals of the directional coupler 6 is constant at π / 2, and the input impedance Zin of each terminal is equal to R and the impedance matching is maintained.

The directional coupler 6 has a capacitance C and an inductance L as distributed constants. As shown in FIG. 1, in the amplitude variable circuit 1 having the distributed constant type directional coupler 6, when a clock signal is input to a first terminal T1, the clock signal is connected to a second terminal T2. Although the clock signal is distributed to the third terminal T3, since the second terminal T2 and the third terminal T3 are basically grounded via a capacitor, the clock signal is reflected by these and the reflected wave is generated. The signal is output to the fourth terminal T4. here,
For example, when the capacitance is changed by using a variable capacitance diode 9 having a junction capacitance-reverse voltage characteristic as shown in FIG. 3 to change the amount of reflection, the amplitude of the clock signal output from the fourth terminal T4 is controlled. be able to. FIG. 4 shows an example of an output amplitude variable characteristic when a sine wave of 2 GHz is input to the amplitude variable circuit 1.

The voltage control circuit 5 shown in FIG. 1 has an output terminal connected to the connection point between the second capacitor 8 and the variable capacitance diode 9 and responds to the magnitude of the detected value of the peak detection circuit 4. By changing the voltage applied to the variable amplitude circuit 1, the output amplitude of the variable amplitude circuit 1 is made constant. The voltage control circuit 5 includes, for example, a first input terminal connected to an output terminal of the peak detection circuit 4, a second input terminal supplied with a reference voltage Verf, the second capacitor 8, and the variable capacitance diode 9. And a comparator 5a having an output terminal connected to a connection point of the comparator 5a.

[0022]

According to the present invention, fluctuations in the output phase of the nonlinear amplifier can be reliably prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a circuit diagram showing a directional coupler of the embodiment of FIG.

FIG. 3 is a diagram showing a junction capacitance-reverse voltage characteristic of the variable capacitance diode of the embodiment of FIG.

FIG. 4 is a diagram showing characteristics of the variable amplitude circuit of the embodiment of FIG. 1;

FIG. 5 is a block diagram showing a conventional clock signal phase stabilization circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 Amplitude variable circuit 2 Clock signal distributor 3 Nonlinear amplifier 4 Peak detection circuit 5 Voltage control circuit 6 Directional coupler 7 First capacitor 8 Second capacitor 9 Variable capacitance diode

Claims (2)

(57) [Claims] 1. An amplitude variable circuit for changing the amplitude of an input clock signal and outputting the same, a clock signal distributor connected to an output terminal of the amplitude variable circuit for distributing a clock signal, and the clock signal distributor. A peak detection circuit connected to one of the output terminals for detecting a peak of the clock signal , and a voltage control circuit connected between the peak detection circuit and the amplitude variable circuit, wherein a clock signal is input. The first terminal, the second terminal and the
3 and an output terminal connected to the clock signal distributor
Distributed type directional coupling having a fourth terminal that is a child
Connected between the second terminal and a reference potential terminal.
A first capacitor, the third terminal, and a reference potential terminal.
And a variable capacitor connected in series between
A voltage diode having an output terminal connected to a connection point between the second capacitor and the variable capacitance diode, and outputting the voltage to the variable amplitude circuit in accordance with a detection value of the peak detection circuit. Wherein the amplitude of the output of the variable amplitude circuit is kept constant by changing the amplitude of the clock signal. 2. A voltage control circuit comprising: a first input terminal connected to an output terminal of the peak detection circuit; a second input terminal supplied with a reference voltage; the second capacitor; and the variable capacitance diode. 2. The clock signal phase stabilizing circuit according to claim 1, comprising a comparator having an output terminal connected to a connection point of the clock signal.