JP3051273B2 - Semiconductor element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device requiring a high withstand voltage, such as a high-output semiconductor device essential for transmission of high-frequency communication equipment.

[0002]

2. Description of the Related Art In recent years, with the spread of new media, the performance of communication devices such as cellular phones, car phones, and cordless telephones has been improved.

[0003] In particular, portable telephones and car telephones have become widespread. This is because the miniaturization technology has advanced and the number of batteries used has decreased. As a result,
The power supply voltage is in the direction of becoming lower, and the semiconductor element to be used needs to achieve both lower resistance and higher breakdown voltage.

Conventionally, silicon bipolar transistors and gallium arsenide field effect transistors (hereinafter referred to as GaAs FETs) have been used as high-power semiconductor elements used in transmission stages of analog cellular phones and automobile telephones because of their excellent high-frequency characteristics. It is used alive.

FIG. 6 is a schematic sectional view showing the structure of a conventional high-power GaAs FET. In the figure, reference numeral 1 denotes a source, 2 denotes a drain, and 3 denotes a gate. The gate 3 is made of aluminum and titanium, and has a gate length of about 1 μm. An active layer 5 and a contact layer 6 are formed on the substrate 4 by ion implantation, and an intermediate concentration layer 9 is formed between the active layer 5 and the contact layer 6 in order to obtain a high breakdown voltage. This structure has a lightly-doped drain.
n, hereinafter referred to as LDD). With this LDD structure, a high electric field is alleviated in the depletion layer immediately below the gate, and the breakdown voltage is improved. However, when an active layer is formed by implantation, since the current is directly determined by the thickness of the active layer, ions must be implanted at a low accelerating voltage, so that the surface concentration becomes inevitably high and the gate leak current increases. . At this time, if a bias is applied to the FET with a resistor,
This leak current causes the bias point to move to a shallower position, and during class B operation, becomes closer to class A operation, resulting in lower addition efficiency. For example, by lowering each concentration of the active layer and the intermediate concentration layer, 12
When a withstand voltage of V was provided, the on-resistance was 5 ohm / mm with respect to the unit gate width. Therefore, when the battery is made into three cells or when a lithium battery is used, 50%
It was difficult to obtain an additional efficiency of about 60% or more.

As described above, it has been difficult for a conventional high-power semiconductor device to realize a GaAsFET with a low voltage operation and a high added efficiency.

[0007]

As described above, the conventional semiconductor device has a disadvantage that when the power supply voltage is low, the on-resistance between the drain and the source, which contributes most to the power and efficiency, is high. For example, a conventional GaAs FET that is used at a power supply voltage of 4.8 V or more can achieve this.
% Is an issue of practical application in the case of lower voltage.

The present invention provides a semiconductor device suitable for low-voltage operation, having low resistance, high withstand voltage, and low gate leakage current.

[0009]

In order to solve the above problems, a semiconductor device according to the present invention comprises an active layer, a contact layer,
An intermediate concentration layer between the active layer and the contact layer.
In the FET having the multi-layered LDD structure, the active layer
The surface is formed lower than the surface of the contact layer,
Surface of the intermediate concentration layer on the side of the active layer and an end table of the active layer
And the surface of the intermediate concentration layer on the side of the contact layer.
When the surface coincides with the end surface of the contact layer
The surface of the intermediate concentration layer is provided with an inclination to
The thickness of the layer increases in the direction of the contact layer.
You . In addition, the semiconductor element of the present invention can be used for contacting an active layer
Layer and an intermediate concentration between the active layer and the contact layer
In an FET having an LDD structure provided with a layer,
The surface of the conductive layer is formed lower than the surface of the contact layer.
The active layer side surface of the intermediate concentration layer and the active layer
And the contact surface of the intermediate concentration layer
The surface on the side of the contact layer coincides with the end surface of the contact layer.
And the cross section of the intermediate concentration layer has a linear inclination.
By providing a slope, the thickness of the intermediate concentration layer is closer to the contact layer side.
It becomes thicker in the direction . Also, the semiconductor device of the present invention
Are an active layer and a contact layer, and the active layer and the
Has an LDD structure in which an intermediate concentration layer is provided between tact layers
In the FET, the surface of the active layer is the contact layer
The active layer of the intermediate concentration layer formed lower than the surface of
Side surface and the end surface of the active layer coincide with each other.
The surface of the intermediate concentration layer is provided with a slope having a curved cross section.
The thickness of the intermediate concentration layer is increased in the direction of the contact layer.
It will be . Further, the semiconductor device of the present invention
Layer and contact layer, and the active layer and the contact layer
FET with LDD structure with intermediate concentration layer between
Wherein the surface of the active layer is different from the surface of the contact layer.
Surface of the intermediate concentration layer on the side of the active layer.
And the end surface of the active layer coincide with each other,
An inclined surface is provided so that the thickness of the intermediate concentration layer is
In addition to increasing the thickness in the direction of the
A recess is provided, and a gate metal is formed on the recess.
Is what it is . In addition, the semiconductor device of the present invention may further comprise an active layer
Between the contact layer and the active layer and the contact layer.
FET with LDD structure with intermediate concentration layer between
Wherein the surface of the active layer is higher than the surface of the contact layer.
Formed on the surface of the intermediate concentration layer on the side of the active layer.
The end surface of the active layer coincides with the surface of the intermediate concentration layer.
The thickness of the intermediate concentration layer is adjusted so that the contact
Together becomes thick coat layer side direction, the better spacing of intermediate density layer and a gate of the drain side of the source side is longer Monodea
You. In addition, the semiconductor element of the present invention can be used to make contact with an active layer.
Layer and an intermediate concentration between the active layer and the contact layer
In an FET having an LDD structure provided with a layer,
The surface immediately below the gate metal of the conductive layer is the surface of the intermediate concentration layer
And lower than the contact layer,
The surface immediately below the gate metal and the side of the intermediate concentration layer of the active layer
And a surface is provided with an inclination. Ma
Further, the semiconductor device of the present invention comprises an active layer, a contact layer,
An intermediate concentration layer between the active layer and the contact layer.
In the FET having a double-digit LDD structure, the intermediate concentration
The distance between the layer and the gate is longer on the drain side than on the source side
It is characterized by the following.

[0010]

The semiconductor device of the present invention is suitable for low-voltage operation, and can realize extremely high efficiency, low resistance, high withstand voltage, and low gate leak current.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a GaAs of the first embodiment of the present invention.
FIG. 2 is a schematic cross-sectional structure diagram of an FET. This FET is an LDD
The intermediate concentration layer of the structure is thicker than the active layer in a direction perpendicular to the semiconductor surface and forms a projection from the semiconductor surface, and the intermediate concentration layer has a rectangular structure. Reference numeral 1 in the figure,
Reference numeral 2 denotes source and drain electrodes, each of which is made of an ohmic metal using AuGe metal. 3 is a gate. The gate 3 is made of aluminum and titanium and has a gate length of 1 μm.
m. On the GaAs substrate 4, an active layer 5 and a contact layer 6, and an intermediate concentration layer 7 between them are formed by ion implantation. At this time, the intermediate concentration layer 7 is formed in a rectangular shape by using an acid-based wet etching method in order to obtain a high withstand voltage. That is, the active layer 5 and a part of the intermediate concentration layer 7 are mainly etched. With the LDD structure, the breakdown voltage is improved, and a breakdown voltage of 12 V or more can be easily realized. In addition, since the active layer is thinned by etching, an implantation process at a high accelerating voltage of, for example, 180 keV can be performed, and the surface concentration can be reduced, so that the gate leak current can be reduced. At this time, when a bias is applied to the FET with a resistor, the bias point is prevented from moving to a shallower side by the leak current, and the class A operation is closer to that of the class B operation than in the class B operation. The on-resistance can be reduced by the thicker portion in the surface direction of the rectangular intermediate concentration layer 7 in the surface direction than before, and it is possible to realize 3.5 ohm / mm or less. According to the present invention, the reduction of the gate leakage current, the reduction of the on-resistance, and the increase in the withstand voltage can be realized at the same time.
Even for the following power supplies, it is possible to obtain an additional efficiency of 60% or more.

FIG. 2 shows a high power G according to a second embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view of an aAsFET.
The intermediate concentration layer having the D structure is thicker than the active layer in a direction perpendicular to the semiconductor surface and in a direction forming a protrusion from the semiconductor surface, and the intermediate concentration layer has a curved structure. Symbols 1 and 2 in the figure are sources,
Each drain electrode is made of an ohmic metal using AuGe metal. 3 is a gate. The gate 3 is made of aluminum and titanium and has a gate length of 1 μm. The active layer 5 and the contact layer 6 are formed on the GaAs substrate 4 by ion implantation, and the intermediate concentration layer 7 is formed between the active layer 5 and the contact layer 6. At this time, in order to obtain a high withstand voltage, the curved intermediate concentration layer 7 is formed into a curved surface using phosphoric acid-based etching. In the curved intermediate concentration layer 7, since the electric field concentration hardly occurs, the withstand voltage can be further improved, and the on-resistance can be slightly improved. With the LDD structure, the breakdown voltage is improved, and a breakdown voltage of 13 V or more can be easily realized. In addition, since the active layer is thinly etched in the same manner as in the first embodiment, for example, an implantation process of a high accelerating voltage such as 180 keV can be performed, and the surface concentration can be reduced, thereby reducing the gate leakage current. Becomes possible. At this time, if a bias is applied to the FET with a resistor, it is possible to prevent the bias point from moving to a shallower side due to the leak current, and it is possible to avoid that the class B operation becomes closer to the class A operation and the additional efficiency is deteriorated. By using a curved intermediate concentration layer that is thicker in the surface direction than in the related art, the on-resistance can be reduced, and it is possible to realize 3 ohm / mm or less. By simultaneously reducing the gate leakage current, reducing the on-resistance and increasing the breakdown voltage,
An additional efficiency of 60% or more can be obtained even for a power supply of 3.6V or less.

FIG. 3 shows a high power G according to a third embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view of an aAsFET.
The intermediate concentration layer of the D structure has a structure that is thicker than the active layer in a direction perpendicular to the semiconductor surface and forms a projection from the semiconductor surface, and has a structure in which only the portion of the active layer immediately below the gate metal is thin.
Reference numerals 1 and 2 in the figure denote source and drain electrodes, respectively.
It is composed of an ohmic metal using Ge metal. Reference numeral 3 denotes a gate having a gate length of 1 μm using aluminum and titanium. GaAs substrate 4
Then, the active layer 5 and the contact layer 6 are formed by ion implantation, and the intermediate concentration layer 7 is formed between them. At this time, in order to obtain a high breakdown voltage, the active layer 5 which is thinned just below the gate metal is formed by using a dry etching method. The active layer 5 is made thinner just below the gate electrode 3 so as to be less affected by the semiconductor surface. Therefore, the active layer 5 is less affected by the trap and the power output can be improved. In addition, since the thickness of the active layer 5 other than the gate electrode 3 can be slightly increased, the on-resistance can be slightly improved. With the LDD structure, the breakdown voltage is improved, and a breakdown voltage of 12 V or more can be easily realized. In addition, since the entire active layer is etched except for a part of the intermediate concentration layer, an implantation process of a high acceleration voltage of, for example, 180 keV can be performed, and the surface concentration can be reduced, so that the gate leakage current can be reduced. Will be possible. At this time, FET
, A bias point is prevented from moving to a shallower side by this leak current, and A
It can be avoided that the efficiency is close to the class operation and the addition efficiency is deteriorated. By using the thick intermediate concentration layer 7 in the semiconductor surface direction, the on-resistance can be reduced, and it is possible to realize 3 ohm / mm or less. By simultaneously realizing the reduction of the gate leak current, the reduction of the on-resistance, and the increase in the withstand voltage, the power supply of 3.6 V or less can be used.
% Or more can be obtained.

FIG. 4 shows a high output G of a fourth embodiment of the present invention.
It is a schematic sectional drawing of aAsFET. This FET is an LD
The intermediate concentration layer of the D structure has a structure that is thicker than the active layer in a direction perpendicular to the semiconductor surface and in a direction forming a protrusion from the semiconductor surface,
The distance between the intermediate concentration layer and the gate is longer on the drain side than on the source side. Reference numerals 1 and 2 in the figure denote a source and a drain, which are made of an ohmic metal using AuGe metal.
Reference numeral 3 denotes a gate, which is formed with a gate length of 1 μm using aluminum and titanium. The active layer 5 and the contact layer 6 and the intermediate concentration layer 7 between them are formed on the GaAs substrate 4 by ion implantation. At this time, if the distance between the drain-side intermediate concentration layer 7 and the gate electrode 3 is longer than the distance between the source-side intermediate concentration layer 7 and the gate electrode 3, it becomes possible to increase the breakdown voltage between the gate and the drain. In addition, a withstand voltage of 12 V or more can be easily obtained, and the source resistance can be reduced. Further, as a result, since the source resistance is low, a high gain can be expected, and the on-resistance can be reduced, so that 3 ohm / mm or less can be easily realized. In this example, the distance between the intermediate concentration layer 7 and the gate electrode 3 was 0.3 μm on the source side and 0.6 μm on the drain side. In addition, since a part of the intermediate concentration layer 7 and the entire surface of the active layer 5 are etched to remove the surface layer, an ion implantation process at a high acceleration voltage of, for example, 180 keV can be performed. Since the gate leakage current can be reduced, the gate leakage current can be reduced. Accordingly, when a bias is applied to the FET with a resistor, the bias point is prevented from moving to a shallower side due to the leak current, and the operation becomes closer to the class A operation than the class B operation, and the additional efficiency is prevented from being deteriorated. By simultaneously realizing the reduction of the gate leak current, the reduction of the on-resistance, and the increase in the withstand voltage, it is possible to easily obtain an additional efficiency of 60% or more even for a power supply of 3.6 V or less.
Will be possible.

In this description, the rectangular intermediate density layer has been described, but it goes without saying that the curved intermediate density layer has exactly the same effect.

FIG. 5 shows a high output G according to a fifth embodiment of the present invention.
It is a schematic sectional drawing of aAsFET. This FET is an LD
The active layer having the D structure has a thin structure immediately below the gate electrode and a thick structure on the source and drain sides. Reference numerals 1 and 2 in the figure denote a source and a drain, which are made of an ohmic metal using AuGe metal. Reference numeral 3 denotes a gate formed of aluminum and titanium and having a gate length of 1 μm. GaAs
An active layer 5 and a contact layer 6 are formed on the s-substrate 4 by ion implantation, and an intermediate concentration layer is formed between them. At this time, in order to obtain a high withstand voltage, an active layer 5 that is thin immediately under the gate electrode 3 and thick on the source / drain side is formed by using an acid-based etching method. In the thin active layer portion, the depletion layer spreads in the lateral direction, so that the distance is increased and the breakdown voltage is improved. In addition, the active layer 5 in the portion other than the gate electrode 3 can increase the thickness of the active layer and can reduce the on-resistance by using a thick intermediate concentration layer.
5 ohms / mm or less can be easily realized. Also, with the LDD structure, the withstand voltage is improved as a whole, and the withstand voltage slightly decreases at the change of the thickness of the active layer.
Withstand voltage of V or more can be realized. In addition, since the entire active layer is etched except for a part of the intermediate concentration layer, for example, 1
An ion implantation process with a high acceleration voltage of 80 keV can be performed, and the surface concentration can be reduced, so that the gate leakage current can be reduced. In addition, FET
, A bias point is prevented from moving to a shallower side by this leak current, and A
It can be avoided that the efficiency is close to the class operation and the addition efficiency is deteriorated. By simultaneously realizing the reduction of the gate leak current, the reduction of the on-resistance, and the increase of the withstand voltage, it is possible to obtain an additional efficiency of 60% or more even for a power supply of 3.6 V or less.

[0018]

According to the present invention, since the surface of the active layer under the gate can be shaved, highly accelerated ion implantation can be used, and the gate leakage current can be reduced by one digit or more. For this reason, this gate current flowing through the gate bias resistor shifts from class B operation to class A operation.
It is possible to avoid a decrease in efficiency. Further, by realizing a thicker intermediate concentration layer than in the past, it is possible to realize a semiconductor device with low on-resistance, suitable for low-voltage operation, and very high efficiency. As a result, the on-resistance can be reduced to 3 to 3.5 ohms / mm or less compared to the conventional 5 ohms / mm, and a high added efficiency of 60% is realized for a drain bias of 3.6 V or less. It becomes possible to do. That is, it is possible to realize the same high efficiency as at 4.8 V, which has been a problem in realizing a three-cell battery (3.6 V), and there is a great practical effect.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of an FET according to an embodiment of the present invention.

FIG. 2 is a schematic sectional view of a second embodiment FET of the present invention.

FIG. 3 is a schematic sectional view of an FET according to a third embodiment of the present invention.

FIG. 4 is a schematic sectional view of an FET according to a fourth embodiment of the present invention.

FIG. 5 is a schematic sectional view of a fifth embodiment FET of the present invention.

FIG. 6 is a schematic sectional view of a conventional FET.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Source 2 Drain 3 Gate 4 GaAs substrate 5 Active layer 6 Contact layer 7 Intermediate concentration layer

Continuation of front page (56) References JP-A-4-99333 (JP, A) JP-A-4-147630 (JP, A) JP-A-6-177159 (JP, A) JP-A-62-158366 (JP) , A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/337-21/338 H01L 29/80-29/812 H01L 29 / 775- 29/778

Claims (7)

(57) [Claims] An active layer, a contact layer, and the active layer
LDD structure having an intermediate concentration layer between
In a FET having a structure, the surface of the active layer is
Formed lower than the surface of the contact layer,
The surface on the active layer side coincides with the end surface of the active layer.
And a surface of the intermediate concentration layer on the contact layer side and the
The end surface of the contact layer coincides with the
The surface of the intermediate concentration layer is provided with a slope so that the thickness of the intermediate concentration layer is reduced.
A semiconductor element, which is thicker in the contact layer side direction . 2. An active layer, a contact layer, and the active layer.
LDD structure having an intermediate concentration layer between
In a FET having a structure, the surface of the active layer is
Formed lower than the surface of the contact layer,
The surface on the active layer side coincides with the end surface of the active layer.
And a surface of the intermediate concentration layer on the contact layer side and the
The end surface of the contact layer coincides with the
The cross-section is provided with a linear slope on the surface of the
The thickness of the concentration layer is increased in the contact layer side direction
A semiconductor element characterized by the above-mentioned . 3. An active layer, a contact layer and the active layer
LDD structure having an intermediate concentration layer between
In a FET having a structure, the surface of the active layer is
Formed lower than the surface of the contact layer,
The surface on the active layer side coincides with the end surface of the active layer.
And the cross-section of the intermediate concentration layer has a curved inclination.
By providing a slope, the thickness of the intermediate concentration layer is closer to the contact layer side.
A semiconductor element characterized by being thicker in a direction . 4. An active layer, a contact layer and the active layer
LDD structure having an intermediate concentration layer between
In a FET having a structure, the surface of the active layer is
Formed lower than the surface of the contact layer,
The surface on the active layer side coincides with the end surface of the active layer.
The surface of the intermediate concentration layer is provided with an inclination to
When the thickness of the layer increases in the direction of the contact layer,
A concave portion is provided on the surface of the active layer, and the concave portion is provided on the concave portion.
A semiconductor element, wherein a gate metal is formed . 5. An active layer, a contact layer and the active layer
LDD structure of the intermediate density layer is provided between the contact layer
In a FET having a structure, the surface of the active layer is
Formed lower than the surface of the contact layer,
The surface on the active layer side coincides with the end surface of the active layer.
The surface of the intermediate concentration layer is provided with an inclination to
When the thickness of the layer increases in the direction of the contact layer,
A semiconductor element , wherein the distance between the intermediate concentration layer and the gate is longer on the drain side than on the source side. 6. An active layer, a contact layer and said active layer
LDD structure having an intermediate concentration layer between
In the FET having the structure,
The lower surface is the surface of the intermediate concentration layer and the contact
Layer below the gate metal of the active layer.
Between the surface and the surface of the active layer on the side of the intermediate concentration layer.
A semiconductor element , characterized by comprising: 7. An active layer, a contact layer and said active layer
LDD structure having an intermediate concentration layer between
In the FET having the structure, the intermediate concentration layer and the gate
The gap is longer on the drain side than on the source side.
Semiconductor device.