JP3048774B2 - Sense circuit and memory circuit using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory circuit such as a dynamic random access memory (hereinafter referred to as DRAM) or a static RAM (hereinafter referred to as SRAM) which is connected to a data line or the like to perform high-speed reading. The present invention relates to a current differential type sense circuit and the like and a memory circuit including a plurality of such sense circuits.

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, there is one described in the following literature. References: IEEE JOURNAL OF SOLID-STATE CIRUITS
), 26 [4] (1991-4) Evert Seevinck, etc.
“Current-Mode Techniques for High-Speed VLSICirc
uits with Application to Current Sense Anplifier f
2 is a circuit diagram showing an example of the configuration of a conventional current differential type sense circuit described in the above-mentioned document.This sense circuit has a first circuit having the same circuit configuration. The circuit portion 10 includes a circuit portion 10 and a second circuit portion 20. The first circuit portion 10 has a first input terminal IN and a first output terminal OUT connected to a data line. Terminal IN is the data line load 11
Is connected to the power supply voltage Vcc. Two Ps are provided between the first input terminal IN and the first output terminal OUT.
Channel type MOS transistors (hereinafter, referred to as PMOS) 12 and 13 are connected in series, and an output terminal O
The UT is connected to the ground GND via the first resistance means 14.

[0003] The second circuit part 20 comprises a first circuit part 1.
0, the second input terminal IN connected to the data line.
B and a second output terminal OUTB, and the input terminal IN
B is connected to the power supply voltage Vcc via the data line load 21. A second input terminal INB and a second output terminal OU
TB, two PMOSs 22 and 23 are connected in series, and the output terminal OUTB is connected to the second resistance means 2.
4 and connected to GND.

The gate and drain of the PMOS 12 in the first circuit portion 10 and the PMOS 22 in the second circuit portion 20 are cross-connected to each other. Also, PMOS13
And the gate of the PMOS 23 are commonly connected to a terminal Y. Note that, in the circuit of FIG.
Are designed so that the input terminals IN and INB are biased near the power supply voltage Vcc, and the PMOSs 12, 13, 22, and 23 are all saturated.

Next, the operation will be described. When the terminal Y becomes “L” level, the PMOSs 13 and 23 are turned on,
One of the PMOSs 12 and 22 is turned on and the other is turned off by the minute current difference flowing between the input terminals IN and INB connected to the data line, and the minute current difference is detected. Then, this small current difference is amplified, and the first and second currents are amplified.
Are obtained as a large potential difference between the output terminals OUT and OUTB. In this type of sense circuit, the potential difference (corresponding to the data line voltage amplitude) between the input terminals IN and INB is extremely small, and high-speed reading is possible.

[0006]

However, in the conventional sense circuit, there is a problem that (a) it is not easy to obtain a stable operation, and (b) if the power supply voltage Vcc is low, a sufficient operation margin and There is a problem that speed cannot be obtained (that is, disadvantageous in low power supply voltage operation), and the problem will be described below.

(A) Problem of Operation Stability In the conventional sense circuit, the gates and drains of the PMOSs 12 and 22 are cross-connected to each other (ie, because a part of the latch circuit is included), Positive feedback is likely to be applied to the circuit, and the circuit enters the latch operation and holds the output state irrespective of the input, or oscillates, etc.
Operation was likely to be unstable. FIG. 3 (a), (b)
FIG. 4 is an input / output voltage characteristic diagram for determining the operation stability of such a circuit. 3A and 3B, the vertical axis represents the output potential V _{O1 of} the first circuit portion 10 and the second circuit portion 2.
The input potential V _I2 is 0, and the horizontal axis is the input potential V _I1 of the first circuit portion 10 and the output potential V _O2 of the second circuit portion 20. A curve C ₁ in the figure is an input / output voltage characteristic curve in which the gate of the PMOS 12 is regarded as an input and the drain is regarded as an output in the first circuit portion 10. A curve C ₂ is an input / output voltage characteristic curve in which the gate of the PMOS 22 is input and the drain is regarded as output in the second circuit portion 20. Note that the input terminals IN and INB are appropriately biased to the same potential. As shown in FIG. 3 (a), the curve C ₁ and curve C ₂ Gatada one operating point (intersection) P
, The circuit operates stably. However, in the conventional sense circuit, because the curve C ₁ and curve C ₂ in all areas are close, a slight noise and manufacturing variations, the plurality of operating points P ₁ as shown in FIG. 3 (b), P ₂ , P ₃ is generated, or contains a sense circuit to latch operation, there is a risk or to oscillate. Thus, in the conventional sense circuit,
Two PMOs whose gate and drain are cross-connected to each other
Since S12 and S22 were included, a stable operation could not be obtained.

(B) Problem of disadvantage in low power supply voltage operation In the conventional sense circuit, in addition to the resistance means 14 and 24,
At least two PMOSs 12 and 13 in saturation;
Since the terminals 22 and 23 are connected in series, the input terminals IN and INB have at least V _R + V _TP + V _TPa (where, V _R ; the voltage drop of each of the resistance means 14 and 24, V _TP ;
It is necessary to apply only the threshold voltage of the PMOS, V _TPa ; the threshold voltage of the PMOS including the back bias effect). Therefore, when the power supply voltage Vcc is low, a sufficient operation margin and operation speed cannot be obtained. The present invention has the following problems.
An object of the present invention is to provide a sense circuit and a memory circuit using the same, in which a stable operation cannot be easily obtained and disadvantages in low power supply voltage operation are solved.

[0009]

According to a first aspect of the present invention, a first circuit portion having a first input terminal and a first output terminal, and a second input terminal and a second circuit having a first input terminal are provided. 2
Having the same output terminal as the first circuit portion.
A sense circuit for detecting and amplifying a difference between input signals of the first and second input terminals and outputting the amplified signal from the first and second output terminals. Is configured as follows. That is, the first circuit portion includes a first depletion type MOS transistor, the first output terminal, and a reference potential (for example,
GND). The first depletion type MOS transistor has a source connected to the first input terminal and a drain connected directly or via the first switch to the first output terminal.
Gates are respectively connected to the second output terminals. The second circuit portion includes a second depletion type M
An OS transistor; and a second resistor connected between the second output terminal and the reference potential. The second depletion type MOS transistor has a source connected to the second input terminal and a drain connected directly or to the second input terminal.
The gate is connected to the second output terminal via the switch means, and the gate is connected to the first input terminal.

According to a second aspect of the present invention, there is provided a read circuit having a plurality of sense circuits having first and second input terminals and first and second output terminals, wherein data read by the read circuit is provided. Output to the first and second data buses.
Are connected in common to the first and second data buses, respectively , to form a wired logic , and the first data bus is connected to a reference potential via first resistance means. 2 data buses are connected to the reference potential via second resistance means, and the respective sense circuits are configured as follows. That is, each of the sense circuits has a source connected to the first input terminal and a gate connected to the second input terminal.
A first depletion-mode MOS transistor connected to an input terminal of each of the first and second depletion-mode MOS transistors having a source connected to the second input terminal and a gate connected to the first input terminal, respectively; A first switch means connected in series between a drain of a first depletion type MOS transistor and the first output terminal; and a first switch means connected between a drain of the second depletion type MOS transistor and the second output terminal. And second switch means connected in series between them.

In the third invention, the first and second circuit portions of the first invention are configured as follows. That is, the first circuit portion has a first input / output terminal connected to the first input terminal and a second input / output terminal connected directly or via the first switch to the first output terminal. The control terminal is the second
A first negative resistance circuit connected to each of the input terminals, and first resistance means connected between the first output terminal and a reference potential. Further, the second circuit portion includes a first input / output terminal connected to the second input terminal, and a second input / output terminal connected to the second output terminal directly or via a second switch. A second negative resistance circuit having a control terminal connected to the first input terminal, and a second resistance means connected between the second output terminal and the reference potential. I have.

In a fourth aspect, the first and second aspects of the third aspect are provided.
A first conductive type first MOS transistor connected in series between the first and second input / output terminals, a drain at a first reference potential, and a gate at the control terminal. A second conductive type second MOS transistor having a source connected to the gate of the first MOS transistor, a drain connected to the source of the second MOS transistor, and a gate connected to the second input / output terminal. , A source of a second conductivity type connected to a second reference potential, respectively.
MOS transistors. In a fifth aspect, the resistance means of the first or third aspect includes a resistance element and a switch connected in series.
In a sixth aspect, the resistance element according to the fifth aspect is constituted by a MOS transistor having a gate and a drain connected to each other.

In the seventh invention, each sense circuit of the second invention is configured as follows. That is, in each of the sense circuits, a first input / output terminal of the first and second input / output terminals is connected to the first input terminal, and a control terminal is connected to the second input terminal. The first negative resistance circuit and the first
And a second negative resistance circuit having a first input / output terminal connected to the second input terminal and a control terminal connected to the first input terminal, respectively, and A first switch means connected in series between a second input / output terminal of the first negative resistance circuit and the first output terminal;
And a second switch means connected in series between a second input / output terminal of the negative resistance circuit and the second output terminal. In an eighth aspect, the first and second negative resistance circuits according to the seventh aspect are provided as the first conductivity type first MOS transistor connected between the first and second input / output terminals. A second MOS transistor of a second conductivity type having a drain connected to the first reference potential, a gate connected to the control terminal, a source connected to the gate of the first MOS transistor, and a drain connected to the second MOS transistor; A third conductive type third MO having a gate connected to the second input / output terminal, a source connected to the second reference potential, and a source connected to the transistor, respectively.
Each of them is composed of an S transistor.

[0014]

According to the first aspect of the present invention, since the sense circuit is configured as described above, the first circuit part and the second circuit part operate as a source follower circuit with each other to enter a latch operation. Alternatively, stable operation is possible without oscillation. One depletion type MOS transistor in saturation and the resistance means are connected in series between the input terminal and the reference potential, and detect a small input current difference to obtain a large potential difference output. Further, the input potential difference can be kept small. Thus, a sense circuit with excellent operation stability, excellent low power supply voltage operation, and a small number of elements can be provided.

According to the second invention, the first and second circuit portions in each sense circuit operate as a source follower circuit, so that the operation is stable and the low power Voltage operation becomes possible. In addition, the switch means enables a quick transition from the standby state to the operating state. According to the third aspect, since the first and second negative resistance circuits are cross-connected, the first and second circuit portions operate as a source follower circuit with each other. Further, the negative resistance circuit and the resistance means connected in series between the input terminal and the reference potential perform a sensing operation for detecting a small input current difference and obtaining a large potential difference output, and further reducing the input potential difference. Therefore, it is excellent in low power supply voltage operation.

According to the fourth aspect, since the first and second negative resistance circuits are each constituted by the first, second and third MOS transistors, the control terminal in each negative resistance circuit is provided. And a current flowing between the first and second input / output terminals has a relationship similar to that of a depletion type MOS transistor. Therefore, the first and second circuit portions operate as source follower circuits with each other, so that the operation is stabilized. Further, a negative (differential) resistance characteristic is obtained between the first input / output terminal and the second input / output terminal of each negative resistance circuit, and the connection between the first and second input / output terminals is obtained. As the flowing current increases, the resistance between the input and output terminals decreases.
Therefore, the voltage drop generated in the resistance means increases, and the gain of the sense circuit increases.

[0017] According to the fifth and sixth, the resistance means
Standby by turning on and off the switch means
The current consumption at the time is reduced. According to the seventh aspect, since the first and second negative resistance circuits are cross-connected,
As in the second aspect, the first and second circuit portions operate as a source follower circuit with each other, so that the operation is stabilized, and more favorable low power supply voltage operation can be performed. Also, the switch means
A transition from the standby state to the operation state can be quickly performed. According to the eighth invention, the first and second negative resistance circuits are the first and second negative resistance circuits.
Since they are constituted by the second and third MOS transistors, the operation is the same as that of the fourth invention. Therefore, the above problem can be solved.

[0018]

EXAMPLES First Embodiment FIG. 1 is a circuit diagram of a current differential type sense circuit showing a first embodiment of the present invention. This sense circuit includes a first input terminal IN and a first output terminal OUT connected to a data line.
A first circuit portion 110 having a second input terminal INB and a second output terminal OUTB connected to a data line, and a second circuit portion 120 having the same configuration as the first circuit portion 110. In the configuration. First circuit part 110
Is a data line load 111 connected between the first input terminal IN and a first reference potential (for example, power supply voltage Vcc).
And the input terminal IN is connected to the first depletion type PM
The gate is connected to the source of the OS 112, and the gate is connected to the second input terminal INB. The drain of the PMOS 112 is connected to the first output terminal OUT and has a second reference potential (for example,
GND).

The second circuit portion 120 has a second input terminal INB and a power supply voltage Vc, similarly to the first circuit portion 110.
c, and the input terminal INB is connected to a second depletion-type PMOS 122
And the gate thereof is connected to the first input terminal IN.
It is connected to the. The drain of the PMOS 122 is connected to the second
The output terminal OUTB is connected to GND via the second resistance means 123. In this sense circuit, the gates and sources of the two PMOSs 112 and 122 are cross-connected to each other, and the first circuit portion 110 and the second circuit portion 120 are configured to function as source followers.

Next, the operation will be described. First, the input terminal I
N and INB are biased near the power supply voltage Vcc. For example, the bias current I _IN flowing into the input terminal _IN
Increases and the bias current I flowing into the input terminal INB
When _INB is reduced, and raised to the potential V _IN slightly the input terminal IN, it falls to the potential V _INB slightly input terminal INB. Then, the current I _D flowing through the PMOS 112 increases, the current I _DB flowing through the PMOS 122 decreases, and the output terminals OUT, OUT,
A large potential difference V _OUTdif is obtained at OUTB. On the other hand, since the current I _D increases as the current I _IN increases, the current I _L flowing through the data line load 111 does not greatly change. The same applies to the current I _LB flowing through the data line load 121. Therefore, it is possible to reduce the electric potential difference V _{Indi f} of the input terminal IN and INB.

Next, the operation of this embodiment will be described using equations. Let r be the resistance value of each data line load 111, 121,
The resistance value of each of the resistance means 113 and 123 is R. Further, during operation, PMOS112,122 is saturated, and the mutual conductance and _{g m.} For example, the difference between the currents flowing into the input terminals IN and INB is _represented by I _INdif (= I
_IN− I _INB ), the first and second circuit portions 11
Due to the symmetry of _0,120 , when I _INdif = 0, V _IN =
V _INB , I _D = I _DB and V _OUTdif = 0.

Next, it is assumed that a small current difference of I _INdif > 0 occurs. The change of the current I _{IN at} this time is represented by ΔI _IN and the current I _IN
[Delta] I a change in _{INB INB,} current [Delta] I _D changes in I _D, the current I [Delta] I _DB changes in _DB, the potential V _IN changes in [Delta] V _IN, the potential V
_{Assuming that} the change in _INB is ΔV _INB , the following equations (1) to (4) hold. ΔV _IN = −r (ΔI _D −ΔI _IN ) (1) ΔV _INB = −r (ΔI _DB −ΔI _INB ) (2) ΔI _D = g _m (ΔV _IN −ΔV _INB ) (3) ΔI _DB = g _m (ΔV _INB −ΔV _IN ) (4)

(Equation 1) On the other hand, V _INdif = ΔV _IN −ΔV _INB (8) I _INdif = ΔI _IN −ΔI _INB (9) V _OUTdif = R (ΔI _D −ΔI _DB ) (10) From equations (6) and (7), the following equation (1) is obtained.
1) and (12) are obtained.

[0023]

(Equation 2) Accordingly, if the transconductance g _m and the resistance value R are appropriately determined, the minute current difference I _INdif between the input terminals IN and INB is _determined.
And a large output potential difference V _OUTdif is obtained between the output terminals OUT and OUTB, and the potential difference V _INdif between the input terminals IN and INB can be reduced. Also, the equivalent impedance between the input terminals IN and INB, since 1/2 g _m and made with can be minimized, for example in a memory circuit, be connected to the data lines having large parasitic capacitance to the input terminal IN and INB, High-speed reading becomes possible. Moreover, focusing on the equation (5), even if _{rg m → ∞, ΔI D -ΔI} DB <ΔI
_IN− ΔI _INB is satisfied, and a device with excellent operation stability without oscillation or latch operation can be obtained. In addition, in the sense circuit according to the present embodiment, as shown in FIG. 4, even if there is some manufacturing variation or noise, there is obtained a circuit that does not cause a malfunction.

FIG. 4 shows first and second circuit portions 110 and 200 for determining the stability of the operation of the sense circuit shown in FIG.
120 is an input / output voltage characteristic diagram. The vertical axis in FIG.
Output potential V _O1 of the second circuit part 110 and the second circuit part 1
Input potential V _I2 of 20, the horizontal axis, the output potential V _O2 of input potential V _I1 and the second circuit portion 120 of the first circuit part 110
It is. Curve C ₁ is plotted at P
This is an input / output characteristic curve when the gate of the MOS 112 is used as an input and the source is used as an output. A curve C ₂ is an input / output characteristic curve when the gate of the PMOS 122 is input and the source is output in the second circuit portion 120.
The input terminals IN and INB are appropriately biased to the same potential.

As shown in FIG. 4, the curves C ₁ and C ₂ intersect at one operating point P and move away from each other about the operating point P. Therefore, even if the curves C ₁ and C ₂ slightly change, a plurality of operating points are unlikely to occur, and stable operation can be performed even with respect to manufacturing variations and noise. Thus, in the sense circuit of the present embodiment,
Since the first circuit portion 110 and the second circuit portion 120 function as a source follower with each other, a device having excellent operation stability can be obtained. Moreover, in the sense circuit of the present embodiment,
A resistance means 11 is provided between the input terminals IN and INB and GND.
One depletion-type PMO saturated with 3,123
The sense operation can be performed only by providing S112 and S122 in series, and the depletion type PMO
The drain-source voltage for saturating S112 and S122 can be sufficiently reduced. Therefore, an extremely excellent sense circuit can be obtained in a low power supply voltage operation.

Second Embodiment FIG. 5 is a circuit diagram of a main part of a memory circuit according to a second embodiment of the present invention. The elements common to those in FIG. 1 showing the first embodiment are the same as those in FIG. Are denoted by common symbols. This memory circuit includes a sense circuit 100 similar to the sense circuit of FIG. The sense circuit 100 includes a first circuit portion 110A having a first input terminal IN and a first output terminal OUT connected to a data line, and a second input terminal INB and a second input terminal INB connected to a data line. It comprises an output terminal OUTB and a second circuit portion 120A having the same configuration as the first circuit portion 110A.

The first circuit portion 110A has a data line load 111 connected between a first input terminal IN and a power supply voltage Vcc, and the input terminal IN is connected to the source of the first depletion type PMOS 112. It is connected. PMO
The gate of S112 is connected to the second input terminal INB,
Further, the drain of the PMOS 112 is connected to a first output terminal OUT via first switch means (for example, PMOS) 114. Second circuit portion 120A
Has a data line load 121 connected between the second output terminal INB and the power supply voltage Vcc, like the first circuit portion 110A, and the output terminal INB is connected to the source of the second depletion type PMOS 122. It is connected to the. PM
The gate of the OS 122 is connected to the first input terminal IN,
The drain of the PMOS 122 is connected to a second output terminal O via a second switch (for example, a PMOS) 124.
Connected to UTB. The gate of the PMOS 124 is
The gate of the PMOS 114 is commonly connected to the terminal SEB.

First and second output terminals OUT and OUTB
Are commonly connected to the first and second output terminals OUT and OUTB of the other sense circuits via the data buses D and DB to form a wired logic . That is, the sense circuit 100 of the multiple, ... is, a pair of common data buses D, DB
And the data buses D and DB are connected to GND via common first and second resistance means 131 and 132.

Next, the operation will be described. Data bus D, D
A plurality of sense circuits 100 connected commonly to B, in ..., terminal SE of one sense circuit (e.g., 100)
When B goes to the “L” level, P in the sense circuit 100
The MOSs 114 and 124 are turned on to start the sensing operation. As described above, even in a circuit in which the resistance means 131 and 132 are shared by the plurality of sense circuits 100,...
N, INB and GND are substantially connected to PMOS11.
2 and 122 and the resistance means 131 and 132 are connected in series, so that the same sensing operation as in the first embodiment is performed. In this embodiment, unlike the conventional circuit,
Each of the first and second input terminals IN and INB can be used even when the PMOSs 114 and 124 as the switch means are not particularly in a saturated state.
The potential difference between them is suppressed. Therefore, an excellent memory circuit with excellent operation stability and low power supply voltage operation can be obtained. Furthermore, the first and second input terminals IN and INB of the sense circuits 100,... In the standby state in which the terminal SEB is at the “H” level and in the non-selected state are connected to the power supply voltage Vcc close to the potential at the time of operation. Therefore, a quick transition from the standby state to the operation state is possible.

Third Embodiment FIG. 6 is a circuit diagram of a sense circuit showing a third embodiment of the present invention. The elements common to those in FIG. 1 showing the first embodiment are the same as those shown in FIG. Reference numerals are given. This sense circuit
A first circuit portion 110B in which a first negative resistance circuit 115 is provided instead of the first depletion type PMOS 112 in FIG. 1 and a second depletion type PMOS 1 in FIG.
22 and a second circuit portion 120 </ b> B provided with a second negative resistance circuit 125.

The first negative resistance circuit 115 includes first and second
The first input / output terminal TS is connected to the first input terminal IN, and is connected to the power supply voltage Vcc via the first data line load 111. It is connected to the. The second input / output terminal TD is connected to the first output terminal OUT and to GND via the first resistance means 113. Control terminal T
G is the second input terminal INB of the second circuit portion 120B.
It is connected to the. The second negative resistance circuit 125 has a first
Has the same configuration as the negative resistance circuit 115 of FIG.
The first input / output terminal TS is connected to the second input terminal INB, and is connected to the power supply voltage Vc via the data line load 121.
c. The second input / output terminal TD is connected to the second output terminal OUTB and to GND via the second resistance means 123. Control terminal TG
Is connected to the first input terminal IN of the first circuit portion 110B.

The first negative resistance circuit 115 includes first and second negative resistance circuits.
Of the first conductivity type (eg, PMOS) 115a connected between the input / output terminals TS and TD
And a first reference potential (for example, power supply voltage Vcc) and a second reference potential.
And second and third MOS transistors (for example, N-channel MOS transistors, hereinafter referred to as NMOS) 115b and 115c of the second conductivity type connected in series between the reference potentials (for example, GND). . NMO
The gate of S115b is connected to the control terminal TG, and the NM
The source of the OS 115b is connected to the gate of the PMOS 115a and the drain of the NMOS 115c. NM
The gate of the OS 115c is connected to the second input / output terminal TD.

The second negative resistance circuit 125, like the first negative resistance circuit 115, has first and second input / output terminals T
A PMOS 125a connected between S and TD;
The gate of the MOS 125a is connected to the source of the NMOS 125b and the drain of the NMOS 125c. NM
The drain of the OS 125b is connected to the power supply voltage Vcc, and the gate is connected to the control terminal TG. NMOS 12
The gate of 5c is connected to the second input / output terminal TD, and the source is GN.
D.

Next, the operation will be described. Also in this embodiment, the first and second input terminals IN and INB are connected to the power supply voltage V.
biased close to cc. At this time, the first and second
115 in the negative resistance circuits 115 and 125 of FIG.
a and 125a are connected to NMOS 115b and 125a, respectively.
b, at least the first and second input terminals I
NM including back bias effect from the potential of N and INB
The potential is lower by the threshold voltage V _{TNa of} OS. In general, since V _TNa ≫ | V _TP |, each PMO
S115a and 125a are always on.
For example, when the potential of the second input terminal INB decreases, the gate potential of the PMOS 115a in the first negative resistance circuit 115 decreases, and the first and second potentials of the negative resistance circuit 115 decrease.
The current flowing between the input / output terminals TS and TD increases. That is, the first and second negative resistance circuits 115 and 125
Since it operates like a pseudo depletion-type PMOS, the sense circuit of this embodiment performs the same sensing operation as that of the first embodiment. Further, in the present embodiment, since the first and second negative resistance circuits 115 and 125 are used, a circuit having a higher gain than the first and second embodiments can be obtained as shown in FIG. .

FIG. 7 is an operation characteristic diagram of the first output terminal OUT showing the operation example of FIG. The vertical axis in FIG. 7 is the current I _D flowing through the first resistance means 113, and the horizontal axis is the potential V _OUT of the first output terminal OUT. A curve 1 represents, for example, NM in which the gate and the drain are connected as the first resistance means 113.
It is a characteristic curve when OS was used. Curve C ₁ is the second
The potential V _INB input terminal INB of a characteristic curve of the first negative resistance circuit 115 when a V _INB = V _0. Curve C ₂ is a characteristic curve of the first negative resistance circuit 115 when the potential V _INB changes the V _INB = V ₀ -ΔV. Note that in FIG. 7, the potential V _IN of the first input terminal _IN is constant. As shown in FIG. 7, the operating point of the first output terminal OUT at V _INB = V ₀ is the intersection P ₁ next to the curve l and the curve C _1, the I _D = I ₁ this time. V _INB = V ₀ -ΔV
Operating point at the intersection P ₂ next curve l and the curve C _2, this time becomes I _D = I _2.

On the other hand, the characteristic curve of the depletion type PMOS at V _INB = V ₀ becomes a broken line curve C _1a, and I _D = I _1a at the operating point P _1a . The characteristic of the depletion type PMOS at V _INB = V ₀ −ΔV is a curve C _2a ,
I _D = I _2a at the operating point P _2a . As shown in FIG. 7, a _{I 2 -I 1> I 2a -I} 1a, input terminal IN, I
The current change for the same potential change in NB is shown in FIG.
5 and the negative resistance circuits 115 and 125 of the present embodiment are larger than the depletion type PMOSs 112 and 122 of FIG. Therefore, in the (1) to (12), it is the transconductance g _m is increased more in the case of using a negative resistance circuit 115 and 125, having a high gain than the whole circuit can be obtained.

Also in this embodiment, since the first input / output terminal TS and the control terminal TG of the first and second negative resistance circuits 115 and 125 are cross-connected, the first circuit Portion 110B and second circuit portion 120B operate as source followers with each other. Therefore, even if the gain of the entire circuit increases, the loop gain does not exceed 1, and a stable operation can be obtained. This means
In equation (5), even if g _m → ∞, ΔI _D −ΔI _DB <
It is clear from the fact that ΔI _IN −ΔI _INB holds.
Furthermore, since the sense circuit of the present embodiment can be configured without using a depletion type MOS transistor, the manufacturing cost can be reduced. In the present embodiment, the PMOS 11 in the first and second negative resistance circuits 115 and 125 is used.
5a and 125a need to be saturated. Therefore, the first and second input terminals IN and INB need to be biased to a potential of at least V _TP + V _R (where V _{R is} the voltage drop of the resistance means 113 and 123). However, even in this case, the conventional (V _R + V _TP +
_V.sub.TPa ), which is excellent in low power supply voltage operation.

Fourth Embodiment FIG. 8 is a circuit diagram of a sense circuit showing a fourth embodiment of the present invention. The elements common to the elements in FIG. 6 showing the third embodiment are the same as those shown in FIG. Reference numerals are given. In this sense circuit, a first circuit having a different configuration from the first circuit portion 110B of FIG.
Circuit portion 110C of FIG. 6 and second circuit portion 120B of FIG.
And a second circuit portion 120C that is the same as the first circuit portion 110c. The first circuit portion 110C is connected to the first data line load 111 of FIG.
, A first negative resistance circuit 115-1 having a configuration different from that of the first negative resistance circuit 115 in FIG. 6, a first resistance means 113 similar to that in FIG. In the configuration. Similarly, the second circuit portion 120C
6 shows a PMOS 121-1 for a load in place of the second data line load 121 in FIG. 6 and a second negative resistance circuit 12 in FIG.
5 and a second negative resistance circuit 123 similar to FIG. 6.

The first negative resistance circuit 115-1 is composed of the same PMOS 115a and NMOS 115b and 115c as the first negative resistance circuit 115 of FIG.
The difference from FIG. 6 is that the gate of the MOS 115a is extended to the terminal TX. Similarly, the second negative resistance circuit 125-1 includes the PMOS 125 a and the NMOSs 125 b and 125 c similarly to the second negative resistance circuit 125 of FIG.
6 is different from FIG. 6 in that the gate of the PMOS 125a is drawn to the terminal TX.
The terminal TX of the first negative resistance circuit 115-1 is a PMO
The terminal TX of the second negative resistance circuit 125-1 is connected to the gate of the PMOS 111-1, and the terminal TX of the second negative resistance circuit 125-1 is connected to the gate of S121-1.

This embodiment has the following advantages. The potential of the second input terminal INB is shifted down and amplified at the terminal TX of the first negative resistance circuit 115-1. Therefore, the gate potential of the PMOS 121-1 connected to the second input terminal INB is set to the level of the input terminal IB.
It decreases with the decrease in the potential of NB, and the PM
The current flowing through the OS 121-1 increases. Thus, the load PMOS 12 connected to the input terminal INB
1-1, the level-shifted potential of the input terminal INB is applied to the gate, so that the load PMOS
121-1 operates as if the range of its unsaturated region was apparently expanded, and the linearity of the characteristics was improved. The same applies to the PMOS 111-1 for other loads. Therefore, a sense circuit having a wide dynamic range can be obtained.

Fifth Embodiment FIG. 9 is a circuit diagram of a sense circuit showing a fifth embodiment of the present invention. The elements common to the elements in FIG. 6 showing the third embodiment are the same as those shown in FIG. Reference numerals are given. This sense circuit
It is composed of a first circuit portion 110D having a configuration similar to the first circuit portion 110B of FIG. 6 and a second circuit portion 120D having the same configuration as the first circuit portion 110D.
In the first circuit portion 110D, a first negative resistance circuit 11 having a different configuration is used instead of the first negative resistance circuit 115 of FIG.
5-2 are provided, and the first negative resistance circuit 115
6 in that a switch means (for example, a PMOS) 114 is provided between the second input / output terminal TD and the first output terminal OUT. The first negative resistance circuit 115-2 includes a PMOS 115a and NMOSs 115b and 115c as in FIG.
The drain of the MOS 115b is drawn to the terminal TY. The second input / output terminal TD of the first negative resistance circuit 115-2 is connected to the source of the PMOS 114, the drain is connected to the first output terminal OUT, and is connected to GND via the resistance means 113. It is connected.

Similarly to the first circuit portion 110D, the second circuit portion 120D includes a data line load 121 connected between the power supply voltage Vcc and the second input terminal INB, and a second line connected to the input terminal INB. The second input / output terminal TS is connected to the second
Negative resistance circuit 125-2, and the negative resistance circuit 125-2
A PMOS 124 connected between the second input / output terminal TD and the second output terminal OUTB of the second output terminal OUTB;
And a resistance means 123 connected between B and GND. The second negative resistance circuit 125-2 is shown in FIG.
Similarly, the PMOS 125a and the NMOS 125b, 1
25c, and the drain of the NMOS 125b is drawn out to the terminal TY.

The gates of the PMOSs 114 and 124 are commonly connected to a terminal SEB. Further, each terminal TY of the first and second negative resistance circuits 115-2 and 125-2 is connected to PM
The PMOS 13 is commonly connected to the drain of the OS 133.
3 has a gate connected to the terminal SEB and a source connected to the power supply voltage Vcc. As described above, since the PMOSs 114 and 124 controlled by the terminal SEB and the PMOS 133 are provided, power consumption during standby can be reduced. That is,
When the terminal SEB is at the “L” level, the PMOS 133 and the PMOSs 114 and 124 are all turned on, and the same sensing operation as in FIG. 6 of the third embodiment is performed. or,
In this sense operation, the PMOSs 114 and 124 do not need to be saturated, which is advantageous for a lower power supply voltage operation than the conventional one.

When the terminal SEB is at "H" level, the circuit enters a standby state and the PMOS 133, the PMOS 114,
124 is turned off. Therefore, all the currents flowing through the first and second negative resistance circuits 115-2 and 125-2 are cut, and power consumption can be reduced. At this time,
The second input terminals IN and INB are at the power supply voltage Vcc.
Therefore, even if the difference from the bias potential at the time of operation is small and a parasitic data line having a large capacity is connected to the input terminals IN and INB, the transition time from the standby state to the operation state is short.

The present invention is not limited to the above embodiment,
Various modifications are possible. For example, there are the following modifications. (A) In FIG. 5 showing the second embodiment, the first and second output terminals OUT, OUTB of each of the sense circuits 100,.
The data bus D, and not connected to the DB, the data bus D,
Are provided for each of the sense circuits 100,..., And each of the sense circuits 100,.
. May be used as switching means for reducing power consumption during standby. (B) In FIG. 9 showing the fifth embodiment, the PMOS1
The first and second output terminals OUT and OUTB are connected in common between a plurality of sense circuits, and the resistance means 113 and 123 are simply connected in common to the plurality of sense circuits. One set may be connected to constitute a read circuit of the memory circuit.

(C) In FIG. 1 of the first embodiment, FIG. 6 of the third embodiment, and FIG. 8 of the fourth embodiment, the resistance means 113 and 123 are each composed of a resistance element and a switch means. May be included. For example, the resistance means as shown in FIG. 10 includes a first terminal RA connected to an output terminal of a sense circuit, a first NMOS 200 having a drain and a gate connected to the first terminal, and serving as a resistance element. The first N
A second NMOS 201 having a drain connected to the source of the MOS 200 and functioning as a switch;
01 and a second terminal RB connected to a reference potential (eg, GND).
May be provided with a third terminal RC connected to the gate. This makes it possible to reduce the current consumption during standby by turning on and off the switch means. (D) In the first to fifth embodiments, the NMOS
OS, PMOS to NMOS, Vcc to GND, G
Even if ND is replaced with Vcc, the same operation and effect as in the above embodiment can be obtained.

[0047]

As described in detail above, the first and fifth embodiments are described.
According to the sixth aspect, since the first and second circuit portions function as a source follower circuit with each other, there is no danger of entering a latch operation or oscillating and having excellent operation stability. can get. In addition, even with a configuration in which one depletion-type MOS transistor in saturation and a resistance means are connected in series between the input terminal and the reference potential, a small input current difference is detected to obtain a large potential difference output. Operation is possible. In addition, since the input potential difference can be kept small, it is excellent in low power supply voltage operation. Further, a circuit can be configured with a small number of elements.

According to the second aspect, since the first and second circuit portions operate as a source follower circuit with each other, a memory circuit having excellent operation stability and excellent in low power supply voltage operation can be obtained. Further, since the first and second switch means are provided, it is possible to make a quick transition from the standby state to the operation state. According to the third and fourth aspects, the first,
Since the second negative resistance circuit is provided, the first and second circuit portions operate as a source follower circuit to each other, and, similarly to the first invention, detect a small input current difference and output a large potential difference. Can be obtained, and the input potential difference can be reduced. Moreover, compared to conventional ones,
A sense circuit having excellent operation stability and excellent low power supply voltage operation can be obtained. Further, the first and second negative resistance circuits can be configured as a sense circuit having a lower manufacturing cost and a larger gain as compared with a circuit configured with a depletion type MOS transistor.

According to the seventh and eighth aspects, the first, second
, The first and second circuit portions operate as a source follower circuit with each other, and the third and fourth circuit portions
Similarly to the invention, a memory circuit having excellent operation stability, excellent low power supply voltage operation, low manufacturing cost, and high gain can be obtained. In addition, since the first and second switch means are provided, it is possible to quickly transition from the standby state to the operating state.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a sense circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional sense circuit.

FIG. 3 is an input / output voltage characteristic diagram of FIG. 2;

FIG. 4 is an input / output voltage characteristic diagram of FIG. 1;

FIG. 5 is a main part circuit diagram of a memory circuit showing a second embodiment of the present invention.

FIG. 6 is a circuit diagram of a sense circuit showing a third embodiment of the present invention.

7 is an operation characteristic diagram of the output terminal OUT of FIG.

FIG. 8 is a circuit diagram of a sense circuit according to a fourth embodiment of the present invention.

FIG. 9 is a circuit diagram of a sense circuit according to a fifth embodiment of the present invention.

FIG. 10 is another circuit diagram of the resistance means.

[Explanation of symbols]

100 Sense circuit 110, 110A, 110B, 110C, 110D
First circuit part 111, 121 Data line load 111-1, 121-1 Load PMOS 112, 122 First and second depletion type PMOS 113, 131 First resistance means 114, 124 NMOS (first, second 2 switch means) 115, 115-1, 115-2 First negative resistance circuit 115a PMOS (first MOS transistor) 115b, 115c NMOS (second and third M
OS transistor) 120, 120A, 120B, 120C, 120D
Second circuit part 123, 132 Second resistance means 125, 125-1, 125-2 Second negative resistance circuit 125a PMOS (first MOS transistor) 125b, 125c NMOS (second, third M)
OS transistor) 133 PMOS (switch means) GND Ground IN, INB First and second input terminals OUT, OUTB First and first output terminals TS, TD First and second input / output terminals TG Control terminal TX, TY terminal Vcc power supply voltage

Claims (8)

(57) [Claims] 1. A first circuit portion having a first input terminal and a first output terminal, and a first circuit portion having a second input terminal and a second output terminal and having the same configuration as the first circuit portion. A second circuit portion, wherein the first circuit detects and amplifies a difference between the input signals of the first and second input terminals and outputs the amplified signal from the first and second output terminals. The first part has a source connected to the first input terminal, a drain connected to the first output terminal directly or via first switch means, and a gate connected to the second input terminal. And a first MOS transistor connected between the first output terminal and a reference potential.
Wherein the second circuit portion has a source connected to the second input terminal, a drain connected to the second output terminal directly or through a second switch, and a gate connected to the first output terminal. A second depletion-type MOS transistor connected to each of the input terminals, and a second resistance means connected between the second output terminal and the reference potential. circuit. 2. The first and second input terminals and the first and second input terminals.
A readout circuit having a plurality of sense circuits each having an output terminal of: a memory circuit for outputting data read by the readout circuit to first and second data buses; and second output terminals are each connected in common to said first and second data bus word
Iyado logic is configured, the first data bus is connected to the reference potential via a first resistor means, said second data bus is connected to the reference potential via a second resistor means, said Each sense circuit has a first depletion type M having a source connected to the first input terminal and a gate connected to the second input terminal.
An OS transistor, and a second depletion-type transistor having a source connected to the second input terminal and a gate connected to the first input terminal, respectively.
An OS transistor; and a first series connected between a drain of the first depletion type MOS transistor and the first output terminal.
A second switch connected in series between a drain of the second depletion type MOS transistor and the second output terminal.
And a switch means. 3. A first circuit portion having a first input terminal and a first output terminal, and a first circuit portion having a second input terminal and a second output terminal and having the same configuration as the first circuit portion. A second circuit portion, wherein the first circuit detects and amplifies a difference between the input signals of the first and second input terminals and outputs the amplified signal from the first and second output terminals. The first input / output terminal is connected to the first input terminal, and the second input / output terminal is connected to the first input / output terminal directly or via first switch means.
A first negative resistance circuit having a control terminal connected to the second input terminal, and a first negative terminal connected between the first output terminal and a reference potential.
Wherein the first circuit has a first input / output terminal connected to the second input terminal and a second input / output terminal connected directly or via a second switch.
A second negative resistance circuit having a control terminal connected to the first input terminal, and a second resistance means connected between the second output terminal and the reference potential. A sense circuit, comprising: 4. The first and second negative resistance circuits include: a first conductivity type first MOS transistor connected in series between the first and second input / output terminals; A second MOS transistor of a second conductivity type having a gate connected to the control terminal, a source connected to the gate of the first MOS transistor, and a drain connected to the source of the second MOS transistor. ,
4. The sense circuit according to claim 3, wherein a gate is constituted by the second input / output terminal, and a source is constituted by a third MOS transistor of a second conductivity type, the third MOS transistor being connected to a second reference potential. 5. The apparatus according to claim 1, wherein said resistance means includes a resistance element and a switch means connected in series.
Or the sense circuit according to 3. 6. The sense circuit according to claim 5, wherein said resistance element is a MOS transistor having a gate and a drain connected to each other. 7. The first and second input terminals and the first and second input terminals.
A readout circuit having a plurality of sense circuits each having an output terminal of: a memory circuit for outputting data read by the readout circuit to first and second data buses; and second output terminals are each connected in common to said first and second data bus word
Iyado logic is configured, the first data bus is connected to the reference potential via a first resistor means, said second data bus is connected to the reference potential via a second resistor means, said Each sense circuit includes a first negative input terminal having a first input / output terminal of the first and second input / output terminals connected to the first input terminal, and a control terminal connected to the second input terminal. And a second negative terminal having a first input / output terminal connected to the second input terminal and a control terminal connected to the first input terminal, respectively, of the first and second input / output terminals. Resistance circuit; a second input / output terminal of the first negative resistance circuit;
First switch means connected in series between the second input / output terminal of the second negative resistance circuit and the second input / output terminal of the second negative resistance circuit.
And a second switch means connected in series between the output circuit and the output terminal. 8. The first and second negative resistance circuits include: a first MOS transistor of a first conductivity type connected between the first and second input / output terminals; A second conductivity type second MOS transistor having a gate connected to the control terminal, a source connected to the gate of the first MOS transistor, and a drain connected to a source of the second MOS transistor;
8. The memory circuit according to claim 7, wherein a gate is constituted by said second input / output terminal, and a source is constituted by a third MOS transistor of a second conductivity type connected to a second reference potential.