JP3047051B2 - Electric power steering device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electric power steering apparatus for assisting a steering operation.

[0002]

2. Description of the Related Art A vehicle speed detector detects a vehicle speed and a torque detector detects a steering torque applied to a steering wheel.
When the detected torque exceeds a predetermined dead zone, a driving current determined according to the detected torque and the detected vehicle speed is passed to a steering assist motor to drive the motor, and the force required for steering the vehicle is determined by the motor. 2. Description of the Related Art An electric power steering device has been developed which assists a driver with a rotational force to provide a comfortable steering feeling to a driver. The control of the steering assist force is performed by a CPU.
It is done by. In such an electric power steering device, there is a type in which the CPU is a dual system in order to guarantee the safety of the system against abnormal operation such as runaway of the CPU.

[0003] In an electric power steering apparatus having a dual CPU, a main CPU for controlling a steering assist force and a main CPU for monitoring input / output of the main CPU are used.
A sub CPU that detects an abnormality of the main CPU, and when the sub CPU detects an abnormality of the main CPU, the sub CPU executes a fail-safe operation for ensuring system safety such as stopping the motor. Control was performed.

When the CPU is of a dual system,
The basic operation of the CPU must be monitored separately. For this reason, the main CPU and the sub CPU mutually monitor the CPU abnormality by monitoring the watchdog pulse signal output from one CPU by the other CPU, and thereby detect the abnormality of the main CPU or the sub CPU. In such a case, a method has been considered in which the CPU that detects the abnormality performs control to execute the fail-safe operation.

As described above, in the control in which one CPU detects the abnormality of the other CPU and executes the fail-safe operation, when the CPU in the abnormal state returns to the normal state, the fail-safe operation is canceled. Had become.

[0006]

However, the occurrence of an abnormality in the CPU and the return to the normal state are repeated,
If the execution of the fail-safe operation and the release thereof are repeated during running, there is a problem that the operation of the system becomes unstable and the running state becomes unstable. As described above, when the operation of the system becomes unstable, it is dangerous.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and is intended to release a fail-safe operation after the vehicle stops when the CPU returns to a normal state from an abnormal state. It is an object of the present invention to provide an electric power steering apparatus that can stabilize the operation state of a system related to the above.

[0008]

SUMMARY OF THE INVENTION An electric power steering apparatus according to the present invention has two CPUs for executing control related to steering assist performed based on a detected steering torque and a detected vehicle speed.
One CPU monitors the operating state of the other CPU, and when it is determined that the monitored CPU is abnormal, the steering assist is prohibited, and thereafter, it is determined that the monitored CPU has returned to normal. If so, the electric power steering device configured to release the prohibition of the steering assist may include means for determining whether the detected vehicle speed is zero, and determining that the detected vehicle speed is zero. Means for permitting release of the prohibition of the steering assist based on the normal return of the monitoring target CPU only when the monitoring target CPU returns to the normal state.

[0009]

According to the present invention, the release of the prohibition of the steering assist based on the normal return of the monitored CPU is permitted only when the vehicle speed is zero. Is not restarted while driving,
An unstable running state does not occur due to the repeated prohibition and release of the steering assist.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments. FIG. 1 is a block diagram showing a configuration of an electric power steering device according to the present invention.

In FIG. 1, reference numeral 1 denotes a main CPU 1 for performing steering assist control.
The operation status of the main CPU 1 is monitored by the sub CPU 2. From the main CPU 1 to the sub CPU 2, a watchdog pulse signal for the sub CPU 2 to monitor the basic operation state of the main CPU 1 and a reset signal for resetting the sub CPU 2 are given. In addition, the sub CPU 2 provides the main CPU 1 with a watchdog pulse signal for the main CPU 1 to monitor the basic operation state of the sub CPU 2,
And a reset signal for resetting "1".

The main CPU 1 includes a torque detection signal obtained by amplifying a detection result of a torque detector 3 for detecting a steering torque of a steered wheel by an amplifier 30 and an engine speed detector 4 for detecting an engine speed. An engine speed detection signal,
A vehicle speed detection signal from a vehicle speed detector 5 for detecting the vehicle speed is provided.

The sub CPU 2 is provided with a torque detection signal obtained by amplifying the detection result of the torque detector 3 by an amplifier 30 and a vehicle speed detection signal of the vehicle speed detector 5.

The main CPU 1 obtains a drive current for driving the steering assist motor 8 and a rotation direction of the motor 8 by a predetermined calculation based on the torque detection signal and the vehicle speed detection signal given as described above. It has become. Then, the main CPU 1 responds to the obtained drive current.
A PWM drive signal is provided to the motor drive circuit 7. If the rotation direction of the motor 8 is right rotation, a right rotation signal for rotating the motor 8 right is supplied to the motor drive circuit 7. The first AND gate 61, which is the giving gate
When the rotation direction of the motor 8 is counterclockwise, a second AND gate 62 which is a gate for supplying a left rotation signal for rotating the motor 8 to the motor drive circuit 7 is provided. The logic signal given to is set to high level. In addition to the above-described control, the main CPU 1 performs an abnormality monitoring control for a basic operation of the sub CPU 2 as described later, based on a watchdog pulse signal given from the sub CPU 2. I have.

[0015] The sub CPU 2 is based on the torque detection signal and the vehicle speed detection signal given as described above.
A drive current for driving the steering assist motor 8 and a rotation direction of the motor 8 are obtained by the same calculation as that described above. Abnormality monitoring control for the basic operation of the main CPU 1 is performed based on the watchdog pulse signal received, and the first AND gate 61 and the second
A logic signal is applied to the AND gate 62.

The first AND gate 61 sets the right rotation signal given to the motor drive circuit 7 to a high level when the logic signals from the main CPU 1 and the sub CPU 2 are both at a high level. The second AND gate 62 is connected to the main CPU
When both the logic signals from the sub CPU 1 and the sub CPU 2 go high, the left rotation signal given to the motor drive circuit 7 is high.

The motor drive circuit 7 determines the direction of rotation of the motor 8 based on the right rotation signal and the left rotation signal, and drives the motor 8 based on a PWM drive signal supplied from the main CPU 1. In the motor drive circuit 7,
When both the logic signals from the first AND gate 61 and the second AND gate 62 become low level, the driving of the motor 8 is prohibited. The drive current of the motor 8 is a current detection resistor.
The detection result is supplied to the main CPU 1 and the sub CPU 2 via the amplifier 9.

Next, the CPU in the main CPU 1 and the sub CPU 2 of the electric power steering apparatus having the above-described configuration will be described.
Abnormality monitoring control will be described. FIG. 2 is a flowchart showing a main routine of abnormality monitoring control for the main CPU 1 in the sub CPU 2. The sub CPU 2 sequentially executes an input / output monitoring subroutine (step S1), a watchdog monitoring subroutine (step S100a), and a normal recovery processing subroutine (step S200a). FIG. 3 is a flowchart showing a main routine of abnormality monitoring control for the sub CPU 2 in the main CPU 1. The main CPU 1 sequentially executes a watchdog monitoring process subroutine (step S100b) and a normal return process subroutine (step S200b).

First, the input / output monitoring control subroutine (step S1) in the sub CPU 2 will be described. Sub CP
The input / output monitoring processing of the main CPU 1 by U 2
2 executes the same arithmetic processing as the steering assist control of the main CPU 1, compares the arithmetic processing result with the arithmetic processing result in the steering assist control of the main CPU 1, and based on the comparison result, the main CPU 1 This is to detect an abnormality. There are a plurality of parameters to be compared, such as the drive current value of the motor 8 and the drive direction of the motor 8. Here, of the parameters, the input / output monitoring process is performed by monitoring the drive current value of the motor 8. explain.

FIG. 4 is a flowchart showing the processing contents of the input / output monitoring processing subroutine (step S1) in the sub CPU 2. First, the drive current value of the motor 8 is determined by the same calculation as that of the main CPU 1 (step S11), and the difference between the determined drive current value and the detected drive current value of the motor 8 as described above is obtained. (Step S12).

Then, it is determined whether or not these differences are equal to or less than a predetermined value (step S13). If it is determined that these differences are equal to or less than the predetermined value, the main CPU 1 operates normally. All the logical signals given to the first AND gate 61 and the second AND gate 62 are set to high level,
Is permitted (step S14).

On the other hand, if it is determined that the difference is not less than the predetermined value, it is determined that an abnormality has occurred in the operation of the main CPU 1 and all the logic signals applied to the first AND gate 61 and the second AND gate 62 are at low level. Then, a fail-safe operation for inhibiting the driving of the motor 8 is performed (step S15), a CPU abnormality flag indicating that an abnormality has occurred in the CPU to be monitored is set (step S16), and the process returns to the main routine.

Next, the sub CPU executed by the main CPU 1
The watchdog monitoring process for the main CPU 1 and the watchdog monitoring process for the main CPU 1 executed by the sub CPU 2 will be described. The processing contents of these watchdog monitoring processes are the same for the main CPU 1 and the sub CPU 2.

FIG. 5 shows a watchdog monitoring process subroutine (step S100b) executed by the main CPU 1,
9 is a flowchart showing the contents of processing with a watchdog monitoring processing subroutine (step S100a) executed by the CPU 2.

First, it is determined whether or not the edge of the watchdog pulse signal (the leading edge or the trailing edge of the pulse) has occurred (step S101). If it is determined that the edge of the watchdog pulse signal has occurred. Clears the count value of the second cycle counter (step S102), and counts the appearance cycle of the edge of the watchdog pulse signal by the first cycle counter (step S103).

Next, it is determined whether or not the count value of the first cycle counter is equal to or greater than a predetermined value (step S104). If it is determined in step S104 that the count value is equal to or greater than the predetermined value, it is determined that the CPU that outputs the watchdog pulse signal is normal because the frequency of the watchdog pulse signal is an appropriate value. Then, the count value of the first cycle counter is cleared (step S105), and the process returns.

On the other hand, if it is determined in step S104 that the count value is not equal to or larger than the predetermined value, the frequency of the watchdog pulse signal is too high, and the CPU that outputs the watchdog pulse signal is abnormal. It is determined that there is, and the process proceeds to step S108 to perform a fail-safe operation as described later.

If it is determined in step S101 that the edge of the watchdog pulse signal has not appeared, the non-appearance cycle of the edge of the watchdog pulse signal is counted by the second cycle counter (step S1).
06).

Next, it is determined whether or not the count value of the second cycle counter is equal to or more than a predetermined value (step S107). If it is determined in step S107 that the count value is not equal to or greater than the predetermined value, the frequency of the watchdog pulse signal is an appropriate value, so that it is determined that the CPU that outputs the watchdog pulse signal is normal, To return.

On the other hand, if it is determined in step S107 that the count value is equal to or greater than the predetermined value, the frequency of the watchdog pulse signal is too low, and the CPU that outputs the watchdog pulse signal is abnormal. Is determined, and the process proceeds to step S108.

In step S108, all logic signals applied to the first AND gate 61 and the second AND gate 62 are set to low level to perform a fail-safe operation for inhibiting the driving of the motor 8. Then, C indicating that an abnormality has occurred in the monitored CPU
The PU abnormality flag is set (step S109), and the process returns to the main routine.

Next, the sub CPU executed by the main CPU 1
The normal return process for the main CPU 1 and the normal return process for the main CPU 1 executed by the sub CPU 2 will be described.
The processing contents of these normal recovery processing are
The same applies to CPU 2.

FIG. 6 is a flowchart showing the contents of the normal return processing subroutine (step S200b) executed by the main CPU 1 and the normal return processing subroutine (step S200a) executed by the sub CPU 2.

First, it is determined whether or not the CPU abnormality flag is set (step S201). If it is determined in step S201 that the CPU abnormality flag has not been set, the process returns to the main routine. On the other hand, when it is determined in step S201 that the CPU abnormality flag is set, it is determined whether or not the detected vehicle speed is zero (step S202).

If it is determined in step S202 that the vehicle speed is not zero (the vehicle is running), the process returns to the main routine. On the other hand, if it is determined in step S202 that the vehicle speed is zero (vehicle is stopped), the CPU abnormality flag is reset (step S203), the fail-safe operation is canceled (step S204), and the process returns to the main routine. I do.

In the above-described abnormality monitoring control, when an abnormality occurs in the CPU to be monitored, a fail-safe operation is performed to prohibit steering assistance, and thereafter, the CP to be monitored is controlled.
When U returns to normal, the fail-safe operation state is released and the prohibition of the steering assist is released.However, the release of the fail-safe operation state is performed after the stop of the vehicle is detected. During traveling, the prohibition of steering assist and the release thereof are not repeatedly performed, so that stable traveling can be performed.

In this embodiment, the first and second AND gates 61 and 62 are used as fail-safe operations.
The operation to prohibit the drive of the motor 8 is performed by setting all the logic signals given to the low level to the low level, but the present invention is not limited to this. Operation may be performed.

[0038]

As described above in detail, in the electric power steering apparatus according to the present invention, the release of the prohibition of the steering assist based on the normal return of the monitored CPU is permitted only when the vehicle speed is zero. Since the steering assist prohibited by the abnormality of the monitoring target CPU is not restarted during traveling, the prohibition of the steering assistance based on the abnormality of the monitoring target CPU and
Since the unstable running state does not occur due to the repetition of the release of the prohibition of the steering assist based on the return of the monitoring target CPU to the normal state, the operation of the system related to the fail-safe operation can be stabilized. To play.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an electric power steering device according to the present invention.

FIG. 2 is a flowchart showing a main routine of abnormality monitoring control for a main CPU in a sub CPU.

FIG. 3 is a flowchart showing a main routine of abnormality monitoring control for a sub CPU in a main CPU.

FIG. 4 is a flowchart showing processing contents of an input / output monitoring subroutine in a sub CPU.

FIG. 5 is a flowchart showing processing contents of a watchdog monitoring subroutine executed by a main CPU and a watchdog monitoring subroutine executed by a sub CPU.

FIG. 6 is a flowchart showing processing contents of a normal return processing subroutine executed by a main CPU and a normal return processing subroutine executed by a sub CPU.

[Explanation of symbols]

 1 Main CPU 2 Sub CPU 3 Torque detector 5 Vehicle speed detector

Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) B62D 6/00 B62D 5/04 G05B 9/03

Claims (1)

(57) [Claims] 1. Two CPUs for executing control related to steering assist performed based on a detected steering torque and a detected vehicle speed, wherein one CPU monitors an operation state of the other CPU, and the CPU to be monitored is abnormal. Is determined, the steering assist is prohibited, and then, when it is determined that the monitoring target CPU has returned to the normal state, the electric power steering device is configured to release the steering assist prohibition. Means for determining whether or not the detected vehicle speed is zero, and only when it is determined that the detected vehicle speed is zero, permission to release the prohibition of the steering assistance based on the normal return of the monitored CPU is permitted. And an electric power steering device.