JP3045697U - Package substrate for chip mounting - Google Patents
Package substrate for chip mountingInfo
- Publication number
- JP3045697U JP3045697U JP1997006546U JP654697U JP3045697U JP 3045697 U JP3045697 U JP 3045697U JP 1997006546 U JP1997006546 U JP 1997006546U JP 654697 U JP654697 U JP 654697U JP 3045697 U JP3045697 U JP 3045697U
- Authority
- JP
- Japan
- Prior art keywords
- package substrate
- plating
- electrode
- electrode body
- motherboard
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Abstract
(57)【要約】
【課題】リワークを容易且つ確実に行うことができ、し
かもチップからの放熱性と耐熱履歴性に優れるパッケー
ジ基板を提供する。
【解決手段】マザーボード側の電極に融解接続される突
起電極を備えたパッケージ基板において、突起電極が、
融解接続時に実質的に熱融解しない100〜600μm
の突出長さの電極本体と該電極本体の少なくとも先端部
を覆うように被着された低融点金属層とから構成されて
いることを特徴とする
(57) [Summary] [Problem] To provide a package substrate which can easily and reliably perform rework, and is excellent in heat dissipation from a chip and heat resistance history. In a package substrate provided with a protruding electrode that is melted and connected to an electrode on a motherboard side, the protruding electrode includes:
100-600 μm that does not substantially heat melt during fusion splicing
, And a low-melting-point metal layer applied so as to cover at least the distal end of the electrode main body.
Description
【0001】[0001]
本考案はチップ搭載用パッケージ基板、詳しくはマザーボードへの実装に際し 該ボード側の電極に対し突起電極に於いて融解接続する、所謂BGA(Ball G rid Array)タイプのパッケージ基板に関する。 The present invention relates to a package board for mounting a chip, and more particularly, to a so-called BGA (Ball Grid Array) type package board that is fused to an electrode on the board side at the time of mounting on a motherboard at a protruding electrode.
【0002】[0002]
半導体素子の高集積化により、半導体を搭載するパッケージの多電極化が急速 に進んでいる。それに伴いパッケージの形態もQFPからTCPへ、さらにはB GAと開発され、多電極化にも関わらずパッケージの小型化が進んでいる。BG Aは他の方法よりも多くの端子が得られることから、これらの中で最新の技術と して広く使用されるようになってきている。 Due to the high integration of semiconductor devices, the package mounting semiconductors is rapidly becoming multi-electrode. Along with this, the form of the package has been changed from QFP to TCP and further to BGA, and the package has been reduced in size despite the increase in the number of electrodes. Since BGA has more terminals than other methods, BGA is widely used as the latest technology among them.
【0003】 BGAパッケージのマザーボードへの実装方法は、マザーボードの予め定めら れた接続箇所にリフロー半田を印刷、BGAパッケージの接続箇所に半田ボール を固定、それらを正確に位置合わせした後、リフロー炉により半田を融解させ接 続している。半田ボールは融解により形を崩してしまうため、パッケージ基板と マザーボードとの間隙は非常に狭くなり、間隔がほとんど無いに等しい状態にな ってしまう。[0003] The mounting method of the BGA package on the motherboard is to print reflow solder on predetermined connection points of the motherboard, fix solder balls on the connection points of the BGA package, accurately align them, and then reflow the furnace. The solder is melted and connected. Since the solder balls lose their shape due to melting, the gap between the package substrate and the motherboard becomes very narrow, almost equal to a gap.
【0004】[0004]
半導体素子は回路が複雑なためトラブルを発生しやすく、パッケージ基板搭載 前の検査では発見できずマザーボードへの実装後に初めて発見されるトラブルも 多くある。また製品化された後の使用形態が適正でないためトラブルとなること も多い。 Semiconductor devices are easy to cause troubles due to their complicated circuits, and there are many problems that cannot be detected by inspection before mounting on the package substrate and are first detected after mounting on the motherboard. In addition, it is often the case that trouble is caused by the improper use of the product.
【0005】 トラブル時の最良の対応策は、不良となったパッケージを交換することである が、表面実装されているBGA等のパッケージ基板のみを取り外し、再度別のパ ッケージ基板を実装し直す(リワークする)のは困難な状態にある。[0005] The best solution in the event of a trouble is to replace the defective package. However, only the package substrate such as the surface-mounted BGA is removed, and another package substrate is mounted again ( Rework) is in a difficult state.
【0006】 すなわちパッケージ基板を取り外すためには、パッケージ基板とマザーボード を接続している半田を再度熱融解させ取り外すことが必要になる。この時、再溶 解時の熱が他の素子にまでおよべば、その素子を接続している半田を融解させ、 パッケージ基板の交換後に該素子の接続異常の発生確率を高める原因になり、マ ザーボードの再利用の観点から好ましくない。That is, in order to remove the package substrate, it is necessary to re-melt and remove the solder connecting the package substrate and the motherboard again. At this time, if the heat at the time of re-melting reaches other elements, the solder connecting the elements is melted, which increases the probability of occurrence of abnormal connection of the elements after the replacement of the package substrate. It is not preferable from the viewpoint of reuse of the user board.
【0007】 また取り外したパッケージ基板跡に新たなパッケージ基板を実装し確実な接続 を得るためには、マザーボードの接続点にリフロー用半田を再度印刷しなければ ならない。しかし他の素子の影響により接続点に精度良くリフロー用半田を印刷 することは困難であり、パッケージ基板のマザーボードへの再実装ができにくい 状態にある。In order to mount a new package substrate on the trace of the removed package substrate and obtain reliable connection, reflow solder must be printed again at the connection points of the motherboard. However, it is difficult to print reflow solder accurately at the connection points due to the influence of other elements, and it is difficult to re-mount the package substrate to the motherboard.
【0008】 またチップの高集積化につれ発熱量が多くなり、放熱を確実にしなければ熱に よる暴走の原因となる。現在の放熱対策としては、発熱量の大きいものに対して 冷却機等を搭載し強制冷却を図っているが、安価なチップに対しては十分な放熱 対策が採られていない。In addition, the amount of heat generated increases as the degree of integration of the chip increases, and if heat radiation is not ensured, runaway due to heat may be caused. As a current heat dissipation measure, a cooler etc. is installed for those with a large amount of heat generation for forced cooling, but sufficient heat dissipation measures are not taken for inexpensive chips.
【0009】 また熱履歴によりマザーボードとパッケージ基板との接続に用いられている半 田の一部にクラックが生じ、それにより導電性不良を発生し、高い頻度でリワー クの必要性が出ている。[0009] Furthermore, due to heat history, cracks occur in a part of the solder used for connection between the motherboard and the package substrate, thereby causing poor conductivity, and the need for reworking has come up frequently. .
【0010】[0010]
本考案者等は上記の課題に鑑み、様々な検討の結果、BGAにおける半田ボー ルの代わりに融解接続時に実質的に融解しない所定突出高さの電極本体を設け、 該電極本体の先端部にすず、ビスマス等の低融点金属層、すず−鉛合金、すず− ビスマス合金等の低融点合金層、さらにはこれら低融点金属或いは低融点合金に 銀を含有する低融点合金層、或いはこれら金属又はこれら合金を含有する低融点 で熱融解する導電性ペースト層を設けることにより、マザーボードに必要とされ るリフロー半田量を著しく減少させ或いは必要とせず、融解接続方式であるに拘 わらず装着・脱着が容易であり、さらに該パッケージ基板とマザーボード間に電 極本体の突出高さ基づき充分な大きさの間隙を確保でき、放熱性及び熱履歴に対 して優れた本考案パッケージ基板を提供し得るに至ったものである。 In view of the above problems, the present inventors have made various studies and provided an electrode body having a predetermined protruding height that does not substantially melt at the time of fusion connection, instead of a solder ball in a BGA, and provided at the tip of the electrode body. Low melting point metal layers such as tin and bismuth; low melting point alloy layers such as tin-lead alloy and tin-bismuth alloy; and low melting point alloy layers containing silver in these low melting point metals or low melting point alloys; By providing a conductive paste layer containing these alloys and melting at a low melting point, the amount of reflow solder required for the motherboard is not significantly reduced or required, and mounting / removing is possible regardless of the fusion connection method. In addition, a sufficient gap can be secured between the package substrate and the motherboard based on the protruding height of the electrode body, and the present invention is excellent in heat dissipation and heat history. Which has led to may provide a package substrate.
【0011】[0011]
以下に本考案の一実施形態を添付図面に基づき説明すると次の通りである。 An embodiment of the present invention will be described below with reference to the accompanying drawings.
【0012】 図1は本考案パーケージ基板Aのチップ搭載面側を、図2は突起電極形成面側 をそれぞれ概略的に示し、その基本的な構成は従来品と実質的に異なるところが ない。FIG. 1 schematically shows the chip mounting surface side of the package substrate A of the present invention, and FIG. 2 schematically shows the protruding electrode forming surface side. The basic configuration is substantially the same as that of the conventional product.
【0013】 図3は図1,2に於けるスルーホール並びにその内側近傍の構成を拡大して概 略的に示す縦断面図であり、1は本考案パッケージ基板の本体部、2は電極本体 、3は低融点金属層、4はスルーホール、5はスルーホール4を介し接続された 表裏の導体パターンをそれぞれ示している。FIG. 3 is a longitudinal sectional view schematically showing, in an enlarged scale, the through hole in FIGS. 1 and 2 and the structure in the vicinity of the through hole. 1 is a main body of the package substrate of the present invention, and 2 is an electrode main body. Numeral 3 indicates a low melting point metal layer, numeral 4 indicates a through hole, and numeral 5 indicates a front and back conductor pattern connected through the through hole 4, respectively.
【0014】 本考案に於いて、パッケージ基板の本体部1の基体1aとしては、プリント配 線に用いられる材質のものを適用できる。すなわちガラスエポキシ樹脂積層板、 テフロンで代表されるふっ素系樹脂板、ポリイミド樹脂積層板等の積層板、BT レジン,PP,PES,PET,PEEK等のエンジニアリング樹脂板、これらプラ スチックと無機物の複合体、アルミナなどの酸化物系セラミック板、窒化アルミ ニウムなどの窒化物系セラミック板、炭化けい素などの炭化物系セラミック等の 各種セラミック板、ガラス等の非晶質絶縁体、これらセラミック又は非晶質絶縁 体に金属層として銅箔等を積層した金属積層体等を適用できる。In the present invention, the base material 1a of the main body 1 of the package substrate can be made of a material used for printed wiring. That is, laminated sheets such as glass epoxy resin laminated sheets, fluororesin sheets represented by Teflon, polyimide resin laminated sheets, engineering resin sheets such as BT resin, PP, PES, PET, PEEK, and composites of these plastics and inorganic substances And various ceramic plates such as oxide ceramic plates such as alumina, nitride ceramic plates such as aluminum nitride, carbide ceramics such as silicon carbide, amorphous insulators such as glass, etc. A metal laminate in which copper foil or the like is laminated as a metal layer on an insulator can be used.
【0015】 上記基体1aには必要数のスルーホールとなる穴4aをあけ、無電解銅めっき 、電気めっき、めっきレジスト層の積層、該レジスト層へのパターン露光、現像 、二次電気銅めっき、エッチングレジスト金属層のめっき、めっきレジスト層の 剥離、エッチング、エッチングレジスト金属層の剥離の工程を経てパターン5を 形成することにより、本考案パッケージ基板の基本となる本体部1を得る。パッ ケージ基板の本体部1へのパターン5の形成方法は、すでに公知のその他の方法 によって行ってもよい。A required number of through holes 4a are formed in the substrate 1a, and electroless copper plating, electroplating, lamination of a plating resist layer, pattern exposure to the resist layer, development, secondary electrolytic copper plating, By forming the pattern 5 through the steps of plating the etching resist metal layer, stripping the plating resist layer, etching, and stripping the etching resist metal layer, the main body 1 which is the basis of the package substrate of the present invention is obtained. The method of forming the pattern 5 on the main body 1 of the package substrate may be performed by other known methods.
【0016】 つぎに上記本体部1に対し本考案の最も特徴とするところの電極本体2がマザ ーボード(図示せず)側の電極と位置が合うように形成される。 電極本体2の形成に際しては、まず最初に図4(イ)に示すように上記本体部 1の突起電極形成側の面にめっきレジスト層6を形成する。このめっきレジスト 層6は、ドライフィルム、液体レジスト等通常プリント配線板製造工程でめっき レジストとしての機能を有している物で、露光時にレジスト内での光散乱を生じ 難く、電極本体2の要求突出高の1.01〜1.05倍の厚みが得られ、かつ電 極本体2の径に相当する穴を現像により得られる物であれば特に限定されない。 レジスト層6の膜厚を電極本体2の要求突出高さの1.01〜1.05倍とす るのは、上記本体部1のパターン5のパターン幅、パターン厚等の関係からワー ク中央部とワークエッジ部の電極本体形成部の電流分布を均一化させるためであ り、またレジスト穴内の電流分布をも均一にしレジスト層6との界面近傍の成長 を抑制するためのものである。Next, with respect to the main body 1, the electrode main body 2, which is the most characteristic feature of the present invention, is formed so as to be aligned with the electrode on the motherboard (not shown). In forming the electrode main body 2, first, as shown in FIG. 4A, a plating resist layer 6 is formed on the surface of the main body 1 on the side where the protruding electrodes are formed. The plating resist layer 6 has a function as a plating resist in a normal printed wiring board manufacturing process such as a dry film and a liquid resist, and hardly causes light scattering in the resist at the time of exposure. The thickness is not particularly limited as long as the thickness is 1.01 to 1.05 times the protruding height and a hole corresponding to the diameter of the electrode body 2 can be obtained by development. The thickness of the resist layer 6 is set to be 1.01 to 1.05 times the required projection height of the electrode main body 2 because of the pattern width and the pattern thickness of the pattern 5 of the main body 1 described above. The purpose of this is to make the current distribution in the electrode body forming portion at the part and the work edge part uniform, and also to make the current distribution in the resist hole uniform and suppress the growth near the interface with the resist layer 6.
【0017】 上記効果を得るためには、レジスト層6の厚みを増す量は電極本体2の要求突 出高さが高くなればななるほどその割合は少なく、電極本体2の要求突出高さが 低いほどその割合を多くすればよく、具体的にはめっき条件、電極本体の要求突 出高さ、電極本体2の径等の諸条件により上記範囲内で適宜選択決定すればよい 。In order to obtain the above effect, the amount of increase in the thickness of the resist layer 6 decreases as the required protrusion height of the electrode body 2 increases, and the required protrusion height of the electrode body 2 decreases. The ratio may be increased, and specifically, it may be appropriately selected and determined within the above range according to various conditions such as plating conditions, a required protrusion height of the electrode body, and a diameter of the electrode body 2.
【0018】 本体部1にレジスト層6を積層した後は、図4(ロ)に示すように、電極本体 形成のための穴7を形成するためにパッケージ側の電極パターンと一致するパタ ーンとなるように露光及び現像が行われる。After laminating the resist layer 6 on the main body 1, as shown in FIG. 4B, a pattern matching the electrode pattern on the package side is formed to form a hole 7 for forming an electrode main body. Exposure and development are performed so that
【0019】 露光に用いる光波長はそれぞれ用いるレジスト層6に対応した波長でかつレジ スト層6が比較的厚肉なのでレジスト層6内で散乱し難い光を用いればよく、紫 外線平行光やレーザー光等が例示できる。The light wavelength used for the exposure is a wavelength corresponding to the resist layer 6 to be used, and light that is hardly scattered in the resist layer 6 since the resist layer 6 is relatively thick may be used. Light and the like can be exemplified.
【0020】 現像は炭酸カリウム水溶液又は炭酸ナトリウム水溶液で行われるのが一般的で あり、用いるレジスト層6がこれらに対応しておればこれら溶液でよく、レジス ト層6によりこれら以外の物(有機溶剤等)が指定されておれば指定物質を用い ればよい。The development is generally performed with an aqueous solution of potassium carbonate or an aqueous solution of sodium carbonate. If the resist layer 6 to be used corresponds to these solutions, these solutions may be used. If a solvent, etc.) is specified, the specified substance may be used.
【0021】 レジスト層6の現像は重要であり、電極形成部分にもしレジスト層6の残渣が あればその部分にめっきがされないため電極本体2の形成ができなくなる。その ため現像は一度に行うのではなく、現像・シャワー水洗の工程を繰り返し行い、 穴7の残余している現像液或いはレジストをシャワー水洗により確実に除去する ことが好ましい。The development of the resist layer 6 is important, and if there is a residue of the resist layer 6 in the electrode forming portion, the portion is not plated, so that the electrode main body 2 cannot be formed. For this reason, it is preferable that the development and shower washing are repeated, and the developing solution or the resist remaining in the hole 7 is surely removed by shower washing instead of performing the development at once.
【0022】 レジスト層6に電極本体形成用の穴7を設けた後、脱脂、酸洗の工程を経て電 極本体2形成のためのめっき工程に入る。After the holes 7 for forming the electrode main body are provided in the resist layer 6, the plating step for forming the electrode main body 2 is started through the steps of degreasing and pickling.
【0023】 めっき液としては、パターン銅めっき用いられるめっき液に市販の添加剤(例 えば大和特殊(株)製MM−10、日本リーロナール(株)製カパーグリーム) を添加しためっき液(すなわち硫酸銅:70〜90g/l、硫酸銅:170〜2 10g/lで例示されるめっき液)、電鋳用のめっき液(すなわち硫酸銅:20 0〜250g/l、硫酸:10〜50g/l及び添加剤(フェノールスルフォン 酸、糖蜜、デキストリン、カゼイン、膠、アセチルシアンアミド、チオ尿素等) で例示されるめっき液)、或いはプリント基板用めっき液を使用できる。As the plating solution, a plating solution obtained by adding a commercially available additive (for example, MM-10 manufactured by Daiwa Special Co., Ltd., Copperglyme manufactured by Nippon Lee Ronal Co., Ltd.) to a plating solution used for pattern copper plating (ie, sulfuric acid) Copper: a plating solution exemplified by 70 to 90 g / l, copper sulfate: 170 to 210 g / l), a plating solution for electroforming (that is, copper sulfate: 200 to 250 g / l, sulfuric acid: 10 to 50 g / l) And an additive (a plating solution exemplified by phenolsulfonic acid, molasses, dextrin, casein, glue, acetyl cyanamide, thiourea, etc.), or a plating solution for printed circuit boards.
【0024】 メッキは異なるメッキ法を組み合わせて適用することも可能である。すなわち 無電解めっき→電気めっき、無電解めっき→電鋳めっき、無電解めっき→電気め っき→電鋳めっき、無電解めっき→電鋳めっき→電気めっき、電気めっき→無電 解めっき、電気めっき→電鋳めっき、電気めっき→無電解めっき→電鋳めっき、 電気めっき→電鋳めっき→無電解めっき、電鋳めっき→無電解めっき→電気めっ き、電鋳めっき→電気めっき→無電解めっき、電気めっき又は電鋳めっき(圧縮 応力タイプ)→電気めっき又は電鋳めっき(引っ張り応力タイプ)、電気めっき 又は電鋳めっき(引っ張り応力タイプ)→電気めっき又は電鋳めっき(圧縮応力 タイプ)等が可能である。The plating can be applied by combining different plating methods. That is, electroless plating → electroplating, electroless plating → electroforming plating, electroless plating → electroplating → electroforming plating, electroless plating → electroforming plating → electroplating, electroplating → electroless plating, electroplating → Electroforming plating, electroplating → electroless plating → electroforming plating, electroplating → electroforming plating → electroless plating, electroforming plating → electroless plating → electroplating, electroforming plating → electroplating → electroless plating, Electroplating or electroforming plating (compression stress type) → electroplating or electroforming plating (tensile stress type), electroplating or electroforming plating (tensile stress type) → electroplating or electroforming plating (compression stress type), etc. It is.
【0025】 電着条件はめっき液組成、めっき厚等の諸条件により適宜選択すればよく、電 気めっきの場合、電流密度は4〜6A/dm2が好ましく、めっき温度は20〜 50℃の範囲が好ましい。無電解銅めっきを用いる場合には、使用する薬品のメ ーカーの指示に従えばよい。The conditions for electrodeposition may be appropriately selected depending on various conditions such as the composition of the plating solution and the plating thickness. In the case of electroplating, the current density is preferably 4 to 6 A / dm 2, and the plating temperature is in the range of 20 to 50 ° C. Is preferred. In the case of using electroless copper plating, it is only necessary to follow the manufacturer's instructions for the chemical used.
【0026】 電極本体形成用の穴7内まで脱脂液等のめっき前処理液およびめっき液を十分 に行き渡らすためには穴7内に気泡を入れないこと、穴7内の液交換が速やかに 行われるようにしなければならない。このための方法としてすでに提案されてい る超音波、衝撃法、揺動法や処理液の噴流法を適宜組み合わせばよく、めっきの 際には穴7の深さ、穴7の径とこれらの作用による穴7内の液交換速度を考慮し 上記範囲で電流密度を決めればよい。In order to sufficiently distribute the plating pretreatment solution such as a degreasing solution and the plating solution to the inside of the hole 7 for forming the electrode body, no bubbles should be introduced into the hole 7, and the solution exchange in the hole 7 should be promptly performed. Must be done. As a method for this, the ultrasonic wave, the shock method, the oscillating method, and the jetting method of the treatment liquid which have already been proposed may be appropriately combined. The current density may be determined within the above range in consideration of the liquid exchange speed in the hole 7 due to the above.
【0027】 図4(ハ)は上記メッキ手段を適用して電極本体2を形成した後の状況を示し 電極本体2の形成後はレジスト層7を剥離除去することにより、図4(ニ)に示 すように電極本体2を備えた本体部1が得られる。レジスト層6の剥離除去には 、レジスト指定のNaOH水溶液や有機溶媒等の薬品により行えばよく、特に限 定されるものではない。FIG. 4C shows a state after the electrode main body 2 is formed by applying the plating means. After the electrode main body 2 is formed, the resist layer 7 is peeled off to obtain the state shown in FIG. As shown, the main body 1 having the electrode main body 2 is obtained. The peeling and removal of the resist layer 6 may be performed with a chemical such as an aqueous NaOH solution or an organic solvent designated by the resist, and is not particularly limited.
【0028】 得られた電極本体2に無電解ニッケルメッキ、無電解金メッキ又は金メッキを 公知の方法で施すことができる。The obtained electrode body 2 can be subjected to electroless nickel plating, electroless gold plating or gold plating by a known method.
【0029】 電極本体2は低融点金属層3の熱融解時に実質的に融解しないことが必要であ り、上記銅メッキが一般的であるが、その他、銅合金,ニッケル,ニッケル合金等 のメッキであってもよい。It is necessary that the electrode body 2 does not substantially melt when the low-melting metal layer 3 is thermally melted, and the above-mentioned copper plating is generally used. In addition, plating of a copper alloy, nickel, a nickel alloy, or the like is performed. It may be.
【0030】 電極本体2は融解接続時に実質的に融解せず、これによりマザーボードとの間 に突出高さに略々相当する上下幅の間隔を形成することができる。電極本体2の 突出高さは少なくとも100μmを有していることが必要であり、これによりマ ザーボードとの間に少なくとも50μmの間隔を形成することができる。突出高 さの上限はめっき加工技術面の制限や加工コスト面の制限から最大でも600μ m程度に止められる。The electrode body 2 does not substantially melt at the time of fusion splicing, so that an interval of a vertical width approximately corresponding to the protruding height can be formed between the electrode main body 2 and the motherboard. The protruding height of the electrode body 2 needs to be at least 100 μm, so that a space of at least 50 μm can be formed between the electrode body 2 and the motherboard. The upper limit of the protruding height can be limited to a maximum of about 600 μm due to limitations in plating technology and processing cost.
【0031】 図4(ニ)に示す状態で、電極本体2上に低融点金属層3を被着することによ り図3に示すように本考案パッケージ基板Aが得られる。By attaching the low melting point metal layer 3 on the electrode body 2 in the state shown in FIG. 4D, the package substrate A of the present invention is obtained as shown in FIG.
【0032】 低融点金属層3はマザーボード上への実装時に該ボード側の電極と熱融解によ り接続するためのものであり、低融点金属から構成される。The low-melting point metal layer 3 is used for connecting to an electrode on the board side by heat melting when mounted on a motherboard, and is made of a low-melting point metal.
【0033】 ここで使用できる金属(合金を含む)としては、低融点金属であるすず、ビス マスを例示でき、また合金としては260℃以下の共晶点を有し、少なくともこ れら金属のうち一種以上を含有する合金が適当である。これに該当する合金とし てはすず−鉛合金(半田)、すず−ビスマス合金、すず−銀合金、すず−アルミ ニウム合金、すず−カドミウム合金、すず−インジウム合金、すず−亜鉛合金、 ビスマス−カドミウム合金、ビスマス−鉛合金、ビスマス−亜鉛合金等を例示で きる。Examples of the metals (including alloys) that can be used here include tin and bismuth, which are low-melting metals, and the alloy has a eutectic point of 260 ° C. or less, and at least one of these metals. Alloys containing at least one of them are suitable. Such alloys include tin-lead alloy (solder), tin-bismuth alloy, tin-silver alloy, tin-aluminum alloy, tin-cadmium alloy, tin-indium alloy, tin-zinc alloy, bismuth-cadmium. Alloys, bismuth-lead alloys, bismuth-zinc alloys, and the like.
【0034】 これらを低融点金属層3を電極本体2に被着する方法の1つとして、メッキ法 を例示でき、電気めっき法、無電解めっき法、溶融めっき法を金属及び合金の特 性、工程等を考慮し選択適用すればよい。As one of the methods for applying the low melting point metal layer 3 to the electrode body 2, a plating method can be exemplified, and an electroplating method, an electroless plating method, and a hot-dip plating method are used for the characteristics of metals and alloys. What is necessary is just to select and apply in consideration of a process etc.
【0035】 また他の1つの被着法として、上記金属又は合金を含有し260℃以下で融解 する特徴を有する導電性に優れた導電性ペーストを用い、例えば印刷手段を適用 して被着する方法を例示できる。As another deposition method, a conductive paste containing the above-mentioned metal or alloy and having a characteristic of melting at 260 ° C. or less and having excellent conductivity is used, for example, by applying printing means. The method can be exemplified.
【0036】 これら低融点金属類及び導電ペーストの被着量は本考案基板が搭載されるマザ ーボードとの関係、すなわち電極本体2の大きさ、線幅、線間隔、マザーボード 等の反り等により決定されるものであり一義的に決定することはできないが、本 考案者によりなされた様々な検討結果では、電極本体2に対し厚み20〜50μ mの低融点金属層3を被着することにより良好な結果が得られている。この低融 点金属等の最適量は上記の如く、様々な要因により影響を受けるものであり、こ の範囲に必ずしも限定されるものではない。しかし低融点金属等が過剰に被着さ れた場合にはマザーボードへの実装時に短絡等の問題を生じ易く、他方不十分で あると電極との接続が十分なされず電気的結合がなされない又はなされても長期 的信頼性に欠けることになるので、被着量は適正値に設定すべきである。The amount of the low-melting metal and the conductive paste to be applied is determined by the relationship with the motherboard on which the substrate of the present invention is mounted, that is, the size of the electrode body 2, the line width, the line interval, the warpage of the motherboard, and the like. Although it cannot be determined unambiguously, the results of various studies conducted by the present inventors show that the electrode body 2 can be favorably formed by depositing the low melting point metal layer 3 having a thickness of 20 to 50 μm. Results have been obtained. The optimum amount of the low melting point metal and the like is affected by various factors as described above, and is not necessarily limited to this range. However, if low-melting-point metal is excessively adhered, problems such as short-circuiting are likely to occur during mounting on the motherboard.If insufficient, insufficient connection with the electrodes will result in no electrical connection or Even if this is done, long-term reliability will be lacking, so the deposition rate should be set to an appropriate value.
【0037】 以下に、本考案品の製造例及び性能試験結果を示す。Hereinafter, a production example and a performance test result of the product of the present invention will be described.
【0038】[0038]
【製造例1】 18μmの銅箔を積層した300mm×400mmのガラスエポキシ銅張積層 板を通常のプリント基板作成方法により回路パターンを形成した。すなわち銅張 積層板を穴あけ、無電解銅めっき後にドライフィルムをラミネートし、該ドライ フィルムに紫外線により回路パターンを焼き付け、アルカリによる現像、電気銅 めっき、半田めっき、ドライフィルム剥離、銅エッチング及び半田エッチングの 工程を経て所定の回路パターンを形成した基板に厚さ200μmのドライフィル ム(試作品)を真空ラミネーターにより積層し、プリント基板製造時と同様に紫 外線平行露光機を用いて露光を行った。現像は1%Na2CO3水溶液を現像液 とし、ベルトコンベアー式現像機を使用、該現像液をスプレーにより穴内まで十 分に行き渡らせた後、水洗もスプレーにより行い穴内に残余している現像液及び レジストを除去した。この操作を5回繰り返し行い、電極本体形成用の穴の0. 1%をルーペ観察によりレジストが残余していないことを確認した上で脱脂、酸 洗、電気めっきの工程を行った。脱脂は市販の酸性脱脂液を、酸洗は10%硫酸 をそれぞれ使用し公知の処理条件で処理した。次にめっきであるが、めっき液は 硫酸銅80g/l、硫酸190g/l、光沢剤(大和特殊(株)MM−10)6 .3ml/lの浴組成のものを用いた。めっき条件は、電流密度4A/dm2、 浴温25℃で3.7時間めっきを行いめっき厚195μmの電極本体2を得た。[Manufacturing Example 1] A circuit pattern was formed on a 300 mm x 400 mm glass-epoxy copper-clad laminate obtained by laminating 18 µm copper foils by an ordinary method for producing a printed board. That is, a copper-clad laminate is drilled, a dry film is laminated after electroless copper plating, a circuit pattern is baked on the dry film by ultraviolet rays, development with alkali, electrolytic copper plating, solder plating, dry film peeling, copper etching and solder etching. A 200 μm-thick dry film (prototype) was laminated on a substrate on which a predetermined circuit pattern was formed through the above steps by a vacuum laminator, and exposure was performed using an ultraviolet parallel exposure machine in the same manner as when manufacturing a printed circuit board. . For development, a 1% Na2CO3 aqueous solution is used as a developing solution, and a belt conveyor type developing machine is used. The developing solution is sufficiently spread to the inside of the hole by spraying, and then, washing with water is also performed by spraying, and the developing solution and resist remaining in the hole are sprayed. Was removed. This operation was repeated five times, and the hole for forming the electrode body was removed from the hole. After confirming that 1% of the resist did not remain by loupe observation, the steps of degreasing, pickling and electroplating were performed. Degreasing was performed using a commercially available acidic degreasing solution, and pickling was performed using 10% sulfuric acid under known processing conditions. Next, for plating, the plating solution is copper sulfate 80 g / l, sulfuric acid 190 g / l, brightener (MM-10, Daiwa Special Co., Ltd.) 6. A bath composition of 3 ml / l was used. Plating conditions were plating at a current density of 4 A / dm 2 and a bath temperature of 25 ° C. for 3.7 hours to obtain an electrode body 2 having a plating thickness of 195 μm.
【0039】 めっき後1%NaOH水溶液でレジストを剥離した後、該電極本体2の先端約 50μmの範囲に低融点金属層3を溶融めっき手段の適用により平均20μm被 着し本考案品を得た。この本考案品をチップ無搭載の状態にて、予めリフロー半 田を印刷したマザーボードへの実装を行ったが実装には特に問題は発生しなかっ た。さらに実装したパッケージ基板を熱風により加熱し半田を融解、パッケージ 基板を取り外し、新たなパッケージ基板を取り外した部分に熱風により半田を融 解させながら実装を行った。After the plating, the resist was stripped with a 1% NaOH aqueous solution, and then a low-melting metal layer 3 was applied on the tip of the electrode body 2 to an area of about 50 μm by an average of 20 μm by applying a hot-dip plating means to obtain the present invention. . This product was mounted on a motherboard on which a reflow solder was printed in advance with no chip mounted, but no particular problems occurred during mounting. In addition, the mounted package substrate was heated by hot air to melt the solder, the package substrate was removed, and mounting was performed while the solder was melted by hot air at the location where the new package substrate was removed.
【0040】[0040]
【性能試験1】 従来品と本考品との放熱性能を調べた。ここでの従来品とはパッケージ基板の うちパッケージ基板が半田ボールを有しマザーボードに印刷されたリフロー半田 と共に熱溶融により一体化される形状のものを指し、本考案品とは製造例1記載 の方法により得られたパッケージ基板を指す。これらパッケージ基板に発熱体を 搭載、樹脂封じを行い、チップ搭載による発熱と同様の状態を作り、一定温度を 維持するための発熱体に加える電流量を測定した。パッケージ基板とマザーボー ドとの間隙は、従来品ではほぼゼロであり、本考案品では平均150μmであっ た。尚、マザーボートとの間の間隔が電極本体2の突出高さ195μmより小さ くなるのはマザーボードと本考案品にはソルダーレジスト(図示せず)を装膜す るため、その膜厚(通常20〜25μm程度)相当分だけ間隙が小さくなるため である。温度測定は接触型表面温度計にて測定し、一方の温度が低下した場合、 低下した方の発熱体に流れる電流量を調整し両者の表面温度が一定となるように した。各10個行い、従来品に流した電流量を100とした比較を表1に示す。 表1 設定温度 従来品 間隙50μm 間隙100μm 間隙200μm 40℃ 100 103 110 115 50℃ 100 105 112 120 60℃ 100 106 116 138 表1に示すように、本考案品では表面温度を一定に保つためにはより多くの電 流量を必要とした。これは本考案品が従来品よりも放熱効果が優れ、表面温度が 低下したことによるものである。[Performance Test 1] The heat radiation performance of the conventional product and the present product was examined. Here, the conventional product refers to the package substrate having a shape in which the package substrate has solder balls and is integrated by heat melting together with the reflow solder printed on the motherboard. Refers to a package substrate obtained by the method. Heating elements were mounted on these package substrates, sealed with resin, created a state similar to the heat generated by chip mounting, and the amount of current applied to the heating elements to maintain a constant temperature was measured. The gap between the package substrate and the motherboard was almost zero in the conventional product, and was 150 μm on average in the product of the present invention. The reason that the distance between the mother boat and the electrode body 2 is smaller than the projection height of 195 μm is that the solder resist (not shown) is coated on the mother board and the present invention. This is because the gap is reduced by an amount corresponding to about 20 to 25 μm). The temperature was measured with a contact-type surface thermometer, and when one of the temperatures decreased, the amount of current flowing through the decreased heating element was adjusted so that the surface temperatures of both decreased. Table 1 shows a comparison in which each of the ten samples was performed and the amount of current passed through the conventional product was set to 100. Table 1 Set temperature Conventional product Gap 50 μm Gap 100 μm Gap 200 μm 40 ° C. 100 103 110 115 50 ° C. 100 105 112 120 60 ° C. 100 106 116 138 As shown in Table 1, in order to keep the surface temperature constant in the present invention, More current flow was required. This is due to the fact that the product of the present invention has a better heat dissipation effect than the conventional product and the surface temperature has dropped.
【0041】[0041]
【性能試験2】 製造例1に基づき作成した本考案品と性能試験1で用いた従来品とをチップ搭 載部分に樹脂をのせチップ搭載時とほぼ同一条件となるようにした上で各々マザ ーボードへ実装し、+250℃/室温の条件下、各温度での保持時間30秒の温 度サイクル試験を100サイクル繰り返し、マザーボードと本考案品との間の状 況及びマザーボードと従来品との間の状況を調べた。調査方法は、温度サイクル 試験品をチップ搭載基板の部分を除き除去、チップ搭載部分を樹脂で固定した後 、研磨により突起電極及び半田ボールの観察できる状態まで露出させ、それぞれ の状況を調査した。その結果を表2に示す。 表2 本発明品 従来品 試験前状況 異常は認められず 異常は認められず 試験後状況 異常は認められず クラック発生 従来品の試験後の状況観察により半田ボールの一部にクラックの発生が認めら れたため、チップ搭載部の樹脂を除去し、ボンディングパッドを露出させマザー ボードとの間の導通試験を行なった。その結果本考案品では全て安定した導通が 確認されたが、従来品では一部に不安定な導通部分が確認された。[Performance Test 2] The resin of the present invention created based on Production Example 1 and the conventional product used in Performance Test 1 were put on the chip mounting portion with resin, and the conditions were almost the same as when the chip was mounted. 100 cycles of a temperature cycle test with a holding time of 30 seconds at each temperature of + 250 ° C / room temperature under the condition of + 250 ° C / room temperature, and the situation between the motherboard and the product and between the motherboard and the conventional product. Investigated the situation. The inspection method was as follows. The temperature cycle test product was removed except for the chip mounting substrate, and the chip mounting portion was fixed with resin, and then exposed by polishing to a state where the protruding electrodes and solder balls could be observed, and the respective conditions were examined. Table 2 shows the results. Table 2 Present invention product Conventional product Situation before test No abnormalities were observed No abnormalities were observed No post-test conditions No abnormalities were observed Cracks were observed Cracks were observed in some of the solder balls by observing the status of the conventional products after the tests Therefore, the resin on the chip mounting part was removed, the bonding pads were exposed, and a continuity test with the motherboard was performed. As a result, stable conduction was confirmed in all products of the present invention, but unstable conduction was partially observed in the conventional product.
【0042】[0042]
【考案の効果】 本考案によるパッケージ基板は、以上のごとくリワークが容易でかつ確実であ り、またチップからの発熱に対し優れた放熱性を有するばかりでなく、熱履歴に も強い特徴を有している。[Effects of the Invention] As described above, the package substrate according to the present invention is easy and reliable to rework, and has not only excellent heat dissipation from the heat generated from the chip but also a strong heat history. doing.
【図1】本考案の一実施形態を概略的に示す平面図であ
る。FIG. 1 is a plan view schematically showing an embodiment of the present invention.
【図2】同、底面図であるFIG. 2 is a bottom view of the same.
【図3】突起電極の形成状況を概略的に示す部分拡大縦
断面図である。FIG. 3 is a partially enlarged longitudinal sectional view schematically showing a state of formation of a protruding electrode.
【図4】電極本体の形成工程を概略的に示す工程図であ
る。FIG. 4 is a process diagram schematically showing a process of forming an electrode body.
1 パッケージ基板の本体部 2 電極本体 3 低融点金属層 4 スルーホール 5 導体パターン 6 メッキレジスト層 7 穴 REFERENCE SIGNS LIST 1 Body portion of package substrate 2 Electrode body 3 Low melting point metal layer 4 Through hole 5 Conductor pattern 6 Plating resist layer 7 Hole
Claims (6)
起電極を備えたパッケージ基板において、突起電極が、
融解接続時に実質的に熱融解しない100〜600μm
の突出長さの電極本体を備えていることを特徴とするチ
ップ搭載用パッケージ基板。1. A package substrate having a protruding electrode fused to an electrode on a motherboard side, wherein the protruding electrode is:
100-600 μm that does not substantially heat melt during fusion splicing
A chip mounting package substrate, comprising: an electrode body having a protruding length.
低融点金属層が被着されていることを特徴とする請求項
1記載のパッケージ基板。2. The package substrate according to claim 1, wherein a low melting point metal layer is applied so as to cover at least a tip portion of the electrode body.
及び電鋳メッキ法の少なくともいずれか一つのメッキ法
を適用して形成されていることを特徴とする請求項1記
載のパッケージ基板。3. The package substrate according to claim 1, wherein the electrode body is formed by applying at least one of an electroplating method, an electroless plating method and an electroforming plating method.
ッキ法及び溶融メッキ法のうちの少なくとも1つのメッ
キ手段を適用し、或いは低融点金属を主成分として含む
導電性ペーストの印刷手段を適用して電極本体に被着さ
れていることを特徴とする請求項2記載のパッケージ基
板。4. A method for printing a conductive paste in which the low melting point metal layer is formed by applying at least one of an electroplating method, an electroless plating method and a hot-dip plating method, or a conductive paste containing a low melting point metal as a main component. The package substrate according to claim 2, wherein the package substrate is attached to the electrode body by applying the following.
ともいずれか一方、又はこれら金属と260℃以下の共
晶点を有する金属との合金であることを特徴とする請求
項4記載のパッケージ基板。5. The package substrate according to claim 4, wherein the low melting point metal is at least one of tin and bismuth, or an alloy of these metals and a metal having a eutectic point of 260 ° C. or less. .
ドとの間に電極本体の突出高さに基づく少なくとも50
μmの間隔を形成することができることを特徴とする請
求項1〜5のいずれかに記載のパッケージ基板6. When mounted on a motherboard, at least 50 based on the protruding height of the electrode body between itself and the motherboard.
The package substrate according to any one of claims 1 to 5, wherein an interval of μm can be formed.
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---|---|
JP (1) | JP3045697U (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07122852A (en) * | 1993-10-28 | 1995-05-12 | Kyocera Corp | Manufacture of wiring board |
JPH08332590A (en) * | 1995-06-07 | 1996-12-17 | Internatl Business Mach Corp <Ibm> | Interconnection structure by reflow solder ball with low melting point metal cap |
JPH0982759A (en) * | 1995-09-18 | 1997-03-28 | Casio Comput Co Ltd | Connecting method for board with salient electrode |
-
1997
- 1997-07-28 JP JP1997006546U patent/JP3045697U/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07122852A (en) * | 1993-10-28 | 1995-05-12 | Kyocera Corp | Manufacture of wiring board |
JPH08332590A (en) * | 1995-06-07 | 1996-12-17 | Internatl Business Mach Corp <Ibm> | Interconnection structure by reflow solder ball with low melting point metal cap |
JPH0982759A (en) * | 1995-09-18 | 1997-03-28 | Casio Comput Co Ltd | Connecting method for board with salient electrode |
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