JP3044952B2 - Semiconductor chip mounting structure - Google Patents

Semiconductor chip mounting structure

Info

Publication number
JP3044952B2
JP3044952B2 JP4331089A JP33108992A JP3044952B2 JP 3044952 B2 JP3044952 B2 JP 3044952B2 JP 4331089 A JP4331089 A JP 4331089A JP 33108992 A JP33108992 A JP 33108992A JP 3044952 B2 JP3044952 B2 JP 3044952B2
Authority
JP
Japan
Prior art keywords
semiconductor chip
heat
aluminum
mounting structure
silicon chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP4331089A
Other languages
Japanese (ja)
Other versions
JPH06163764A (en
Inventor
宏和 田中
誠 鳥海
秀昭 吉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Corp
Original Assignee
Mitsubishi Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Corp filed Critical Mitsubishi Materials Corp
Priority to JP4331089A priority Critical patent/JP3044952B2/en
Publication of JPH06163764A publication Critical patent/JPH06163764A/en
Application granted granted Critical
Publication of JP3044952B2 publication Critical patent/JP3044952B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612Auxiliary members for layer connectors, e.g. spacers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は半導体チップの実装構
造、詳しくはシリコンチップの熱膨張による歪、応力を
容易に吸収し得る半導体チップの実装構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip mounting structure, and more particularly to a semiconductor chip mounting structure capable of easily absorbing distortion and stress due to thermal expansion of a silicon chip.

【0002】[0002]

【従来の技術】半導体素子、特にパワートランジスタや
半導体整流素子等では、動作面積当りの消費電力が大き
い。このため、半導体素子のケースやリードからの熱量
の放出だけでは、発生熱量を放出しきれず、半導体素子
の内部温度が上昇して、熱破壊を起こしてしまう。その
ために、半導体素子の発熱を吸収する熱溜めが必要であ
り、従来、絶縁基板とシリコンチップ(半導体素子)と
の間に放熱板を介在させて熱を吸収、放散させていた。
2. Description of the Related Art In a semiconductor device, in particular, a power transistor or a semiconductor rectifying device, power consumption per operation area is large. For this reason, only the release of heat from the case or the lead of the semiconductor element cannot completely release the generated heat, and the internal temperature of the semiconductor element rises, causing thermal destruction. For that purpose, a heat reservoir for absorbing the heat generated by the semiconductor element is required. Conventionally, a heat sink is interposed between an insulating substrate and a silicon chip (semiconductor element) to absorb and dissipate heat.

【0003】この放熱板の材質としては、熱伝導性が良
いことからCuが使われていた。特に、発熱量が多い場
合には、放熱板としては、該シリコンチップの熱膨張係
数に近似している熱膨張係数を有するCu−W合金、あ
るいは、Cu/Mo/Cuクラッド材が使われる。
As a material of the heat radiating plate, Cu has been used because of its good thermal conductivity. In particular, when the calorific value is large, a Cu-W alloy having a coefficient of thermal expansion close to the coefficient of thermal expansion of the silicon chip or a Cu / Mo / Cu clad material is used as the heat sink.

【0004】[0004]

【発明が解決しようとする課題】このようにCuは、熱
伝導率は高いものの、その固有の特性として剛性が高い
ため、熱変形が起こりにくく、シリコンチップに発生し
た熱応力を吸収しにくい。例えば、0.2%耐力(4.
9MPa)が大きいので、外力を印加した場合の弾性変
形範囲が広く、加工硬化も大きい。すなわち、熱応力が
塑性変形により吸収される割合が少ない。また、Cu−
W合金またはCu/Mo/Cuクラッド材は、ともに熱
伝導率が極端に小さいだけでなく、コスト的に高価であ
るという難点を有している。さらに、Cu系材料を用い
た放熱板は、基板全体として重量が過大になるという課
題があった。
As described above, although Cu has a high thermal conductivity, it has high rigidity as an inherent characteristic, so that it is difficult for thermal deformation to occur, and it is difficult to absorb thermal stress generated in a silicon chip. For example, 0.2% proof stress (4.
9 MPa), the elastic deformation range when an external force is applied is wide, and the work hardening is also large. That is, the rate at which thermal stress is absorbed by plastic deformation is small. In addition, Cu-
Both the W alloy and the Cu / Mo / Cu clad material have the drawback that not only the thermal conductivity is extremely small but also the cost is high. Further, there is a problem that a heat sink using a Cu-based material becomes excessively heavy as a whole substrate.

【0005】本発明の目的は、半導体素子の熱サイク
ル、断続通電等により、シリコンチップと放熱板との間
に介在する接合層界面の熱疲労による割れやその剥離が
起こりにくい半導体チップの実装構造を提供することに
ある。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor chip mounting structure in which cracking and peeling due to thermal fatigue at the interface of a bonding layer interposed between a silicon chip and a radiator plate due to thermal cycling, intermittent energization, etc. of a semiconductor element are less likely to occur. Is to provide.

【0006】[0006]

【課題を解決するための手段】本発明は、放熱材を純度
99.9%以上のアルミニウムを用いて作製し、この放
熱材の積層方向の厚みを0.2mm以上とする。このよ
うに柔性の高い金属であるアルミニウムを使用すること
により、上記の目的は達成される。
According to the present invention, a heat dissipating material is manufactured using aluminum having a purity of 99.9% or more, and the thickness of the heat dissipating material in the laminating direction is set to 0.2 mm or more. The above object is achieved by using aluminum which is a metal having high flexibility.

【0007】[0007]

【作用】本発明にあっては、半導体チップ実装用の放熱
材に使用される純アルミニウムは、熱膨張率はCuと比
較してほぼ同等である。また、その熱伝導率もCu−W
合金、Cu/Mo/Cuクラッド材と比較して遜色がな
く、Cu単体と比較した場合は、やや劣るものの、それ
以上に変形抵抗が少ないため、熱応力の吸収材として非
常に有効である。例えば、0.2%耐力(2.9MP
a)が小さいため、容易に塑性変形を起こす。すなわ
ち、熱応力に対して抵抗せずに、順応し易いので、熱応
力の吸収が効果的に行われる。また、Cuに比べて加工
硬化が少ないため、外力に対して柔軟に対応することが
できる。すなわち、金属に外力を印加して塑性変形を起
こさせ、一旦外力を取り除き、再度外力を印加した場
合、Cuをはじめ、大部分の金属は、初めの外力よりか
なり大きな外力でないと、再び塑性変形を起こさない
が、アルミニウムはより小さな外力で塑性変形を起こ
す。
According to the present invention, pure aluminum used as a heat dissipating material for mounting a semiconductor chip has substantially the same coefficient of thermal expansion as Cu. Also, its thermal conductivity is Cu-W
Compared with alloys and Cu / Mo / Cu clad materials, they are slightly inferior to Cu alone, but have less deformation resistance than Cu alone, and are thus very effective as thermal stress absorbing materials. For example, 0.2% proof stress (2.9MP
Since a) is small, plastic deformation easily occurs. That is, since it is easy to adapt without resisting the thermal stress, the thermal stress can be effectively absorbed. Further, since work hardening is less than that of Cu, it is possible to flexibly respond to an external force. In other words, when an external force is applied to a metal to cause plastic deformation, the external force is removed once, and the external force is applied again, most of the metals including Cu are plastically deformed unless the external force is considerably larger than the initial external force. However, aluminum causes plastic deformation with smaller external force.

【0008】本発明においては、このアルミニウムの純
度を99.9%以上とする。この範囲未満では、本発明
の実効が発現しない。さらに本発明においては、アルミ
ニウム製放熱材の積層方向の厚さを0.2mm以上とす
る。この値より薄いと熱応力の緩和効果が少なくなるだ
けでなく、熱溜めとして有効に機能しなくなる。そし
て、このアルミニウム製放熱材は、Cu系放熱材と比較
して軽量であり、Cu−W合金、Cu/Mo/Cuクラ
ッド材よりもコストが安い。
[0008] In the present invention, the purity of this aluminum is 99.9% or more. Below this range, the effect of the present invention is not realized. Further, in the present invention, the thickness of the aluminum heat radiating material in the laminating direction is set to 0.2 mm or more. If the thickness is smaller than this value, not only does the effect of relaxing the thermal stress decrease, but also it does not function effectively as a heat reservoir. The aluminum heat radiator is lighter in weight than the Cu-based heat radiator, and is lower in cost than the Cu-W alloy and the Cu / Mo / Cu clad material.

【0009】[0009]

【実施例】以下、本発明の一実施例について図1を参照
して説明する。この図に示すように、セラミックス、樹
脂、アルミニウム絶縁基板等を用いて作製された絶縁基
板11の上面には、例えばアルミニウム製の回路形成用
導体基板12がろう材等により接合されている。この導
体基板12の上面には、アルミニウム放熱板13がはん
だ14により固着されている。このアルミニウム放熱板
13の表面にははんだ14との濡れ性を良くするためめ
っき層15が被着されている。そして、このアルミニウ
ム放熱板13の上面にはシリコンチップ16が例えばは
んだ17により固着されて搭載されている。ここで、放
熱板13は純度99.9%以上のアルミニウムを用いて
いる。図2はアルミニウムの引張性質に及ぼす不純物の
影響を示すグラフである。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG. As shown in this figure, a circuit-forming conductor substrate 12 made of, for example, aluminum is joined to the upper surface of an insulating substrate 11 made of ceramics, resin, an aluminum insulating substrate, or the like by a brazing material or the like. An aluminum radiator plate 13 is fixed to the upper surface of the conductive substrate 12 by solder 14. A plating layer 15 is provided on the surface of the aluminum radiator plate 13 to improve the wettability with the solder 14. A silicon chip 16 is mounted on the upper surface of the aluminum radiator plate 13 by being fixed with, for example, solder 17. Here, the heat sink 13 is made of aluminum having a purity of 99.9% or more. FIG. 2 is a graph showing the effect of impurities on the tensile properties of aluminum.

【0010】また、放熱板13の厚さは、0.2mm以
上、好ましくは0.2〜2.0mmとする。厚さがこの
範囲を超えると実用的でない。はんだ層14、17との
濡れ性を高めるために放熱板13の表裏面に被着された
めっき層15に用いられるめっき材としては、ニッケル
またはAu/Niを用いる。このめっき層15を挟んで
設層されるはんだ層14、17としては、通常のPb−
Sn系、Su−Sb系、Pb−In系、Au−Si系、
あるいは、Au−Sn系はんだを用いる。殊に、Pb−
Sn系はんだを用いれば、ニッケルめっき層15は、搭
載されるシリコンチップ16が小型の場合、シリコンチ
ップ16のはんだ付けが必要な部分のみに設層すれば、
シリコンチップ16の位置ずれが防止でき好適である。
このような構成に係る実装構造にあっては、シリコンチ
ップ16にパワートランジスタ等を形成した場合でも放
熱板13が発熱を伝達、放散することとなる。そして、
トランジスタ等の繰り返しての使用にあってもはんだ1
4、17の割れ、剥がれ、シリコンチップ16の割れが
生じにくい。これはアルミニウム放熱板13が容易に塑
性変形することにより熱応力を緩和、吸収するからであ
る。
The thickness of the heat radiating plate 13 is 0.2 mm or more, preferably 0.2 to 2.0 mm. If the thickness exceeds this range, it is not practical. Nickel or Au / Ni is used as a plating material used for the plating layer 15 attached to the front and back surfaces of the heat sink 13 in order to enhance the wettability with the solder layers 14 and 17. The solder layers 14 and 17 provided with the plating layer 15 interposed therebetween include ordinary Pb-
Sn-based, Su-Sb-based, Pb-In-based, Au-Si-based,
Alternatively, Au-Sn based solder is used. In particular, Pb-
When the Sn-based solder is used, the nickel plating layer 15 is formed only in a portion where the silicon chip 16 needs to be soldered when the silicon chip 16 to be mounted is small,
This is preferable because the displacement of the silicon chip 16 can be prevented.
In the mounting structure having such a configuration, even when a power transistor or the like is formed on the silicon chip 16, the heat radiating plate 13 transmits and dissipates heat. And
Solder 1 even for repeated use of transistors, etc.
Cracks and peeling of 4 and 17 and cracking of the silicon chip 16 hardly occur. This is because the aluminum heat sink 13 is easily plastically deformed, thereby relaxing and absorbing the thermal stress.

【0011】表1は耐熱サイクル試験の結果を示すもの
である。この表にあって、本発明品としては純度99.
9%のアルミニウムを放熱板として用い、比較品として
はCuを放熱板として用いたものである。試験条件は以
下の通りである。すなわち、1サイクルは、上記絶縁基
板を、−40℃で60分保持した後、室温で10分間保
持し、さらに125℃にて60分間保持し、室温で10
分間保持するものである。
Table 1 shows the results of the heat cycle test. In this table, the purity of the product of the present invention is 99.
9% of aluminum was used as a radiator plate, and as a comparative product, Cu was used as a radiator plate. The test conditions are as follows. That is, in one cycle, the insulating substrate is held at −40 ° C. for 60 minutes, then at room temperature for 10 minutes, further at 125 ° C. for 60 minutes, and at room temperature for 10 minutes.
Hold for a minute.

【0012】[0012]

【表1】 [Table 1]

【0013】図3は上記熱サイクル試験後の比較品のは
んだ部分の割れを100倍に拡大して示す顕微鏡写真で
ある。
FIG. 3 is a photomicrograph showing the cracks in the solder portion of the comparative product after the heat cycle test at 100 times magnification.

【0014】[0014]

【発明の効果】本発明の半導体チップの実装構造にあっ
ては、放熱材の変形抵抗が小さく、塑性変形し易いので
シリコンチップを接合するはんだ層内で発生する熱応力
の緩和効果が高く、シリコンチップに対する熱サイクル
や断続通電に際して、シリコンチップの破壊などを効果
的に抑えることができる。
According to the semiconductor chip mounting structure of the present invention, the heat dissipating material has a small deformation resistance and is easily plastically deformed, so that the effect of reducing the thermal stress generated in the solder layer joining the silicon chip is high. During thermal cycling or intermittent energization of the silicon chip, breakage of the silicon chip can be effectively suppressed.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例に係る半導体チップの実装構
造を示す断面図である。
FIG. 1 is a sectional view showing a mounting structure of a semiconductor chip according to one embodiment of the present invention.

【図2】本発明に係る高純度アルミニウムの降伏応力と
耐力とを示すグラフである。
FIG. 2 is a graph showing the yield stress and proof stress of the high-purity aluminum according to the present invention.

【図3】本発明を説明するための比較品の顕微鏡写真で
ある。
FIG. 3 is a photomicrograph of a comparative product for explaining the present invention.

【符号の説明】[Explanation of symbols]

11 絶縁基板 13 放熱板 16 シリコンチップ 11 Insulating substrate 13 Heat sink 16 Silicon chip

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平2−348(JP,A) 特開 平3−125463(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 23/373 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-2-348 (JP, A) JP-A-3-125463 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 23/373

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 絶縁基板と、この絶縁基板上に接合層を
介して搭載された半導体チップと、これらの絶縁基板と
接合層との間に介装された放熱材と、を備えた半導体チ
ップの実装構造において、 上記放熱材を、純度99.9%以上のアルミニウムによ
り形成したことを特徴とする半導体チップの実装構造。
1. A semiconductor chip comprising: an insulating substrate; a semiconductor chip mounted on the insulating substrate via a bonding layer; and a heat dissipating material disposed between the insulating substrate and the bonding layer. 3. The mounting structure of a semiconductor chip according to claim 1, wherein said heat radiation material is formed of aluminum having a purity of 99.9% or more.
【請求項2】 上記放熱材の積層方向の厚さを0.2m
m以上とした請求項1に記載の半導体チップの実装構
造。
2. The thickness of the heat radiating material in the stacking direction is 0.2 m.
The mounting structure of the semiconductor chip according to claim 1, wherein m is not less than m.
JP4331089A 1992-11-17 1992-11-17 Semiconductor chip mounting structure Expired - Fee Related JP3044952B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4331089A JP3044952B2 (en) 1992-11-17 1992-11-17 Semiconductor chip mounting structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4331089A JP3044952B2 (en) 1992-11-17 1992-11-17 Semiconductor chip mounting structure

Publications (2)

Publication Number Publication Date
JPH06163764A JPH06163764A (en) 1994-06-10
JP3044952B2 true JP3044952B2 (en) 2000-05-22

Family

ID=18239736

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4331089A Expired - Fee Related JP3044952B2 (en) 1992-11-17 1992-11-17 Semiconductor chip mounting structure

Country Status (1)

Country Link
JP (1) JP3044952B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5729052A (en) * 1996-06-20 1998-03-17 International Business Machines Corporation Integrated ULSI heatsink
US7239016B2 (en) 2003-10-09 2007-07-03 Denso Corporation Semiconductor device having heat radiation plate and bonding member
WO2007142261A1 (en) 2006-06-06 2007-12-13 Mitsubishi Materials Corporation Power element mounting substrate, method for manufacturing the power element mounting substrate, power element mounting unit, method for manufacturing the power element mounting unit, and power module

Also Published As

Publication number Publication date
JPH06163764A (en) 1994-06-10

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