JP3044756B2 - Phase compensation method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase compensation method suitable for use in a sample servo type magneto-optical disk reproducing apparatus.

[Summary of the Invention]

The present invention relates to a data reproducing apparatus in which a reference clock is recorded on a recording medium, and the phase of an external clock is compensated using a reproduced signal of the reference clock.
The phase of the external clock is sequentially advanced to one side, the reproduced signal of the reference clock is sampled with this external clock, the difference value of this sampling value is obtained, and the difference value of the present difference value and the previous difference value or the peak value of the difference value so far is obtained. The peak value of the difference value is detected, and when the peak value of the difference value is detected, the phase of the external clock that becomes the peak value is output, and the phase of the external clock is changed in the opposite direction. Proceed and detect the peak value of the difference value by the same control,
When the peak value is detected, the phase of the external clock that becomes the peak value is output, and the phase of the external clock is advanced in the opposite direction. Thereafter, the same control is repeated to detect the peak value of the difference value. By detecting the optimal phase of the external clock using the phase of the external clock that becomes the peak value obtained in the first control, it is possible to perform highly accurate external clock phase compensation in a short time. .

[Conventional technology]

In the sample servo type magneto-optical disk recording / reproducing apparatus, an external clock is formed based on a reproduction signal of a pit for clock reproduction in a servo area, and data is reproduced using the external clock. As described above, in the magneto-optical disk recording / reproducing apparatus that reproduces data using an external clock, the phase of the reproduced data and the external clock are determined by the difference in the distance between the pits between the outer peripheral portion and the inner peripheral portion and the temperature characteristics. Phase error may occur. Therefore, a proposal has been made in which a reference clock having the highest repetition frequency is recorded in a predetermined area of the header of each sector during data recording, and a phase error of an external clock is compensated for using a reproduction signal of this reference clock during reproduction. Have been.

In other words, when the reference clock having the highest repetition frequency is used, as shown in FIG. 13, the external reference clocks φ ₀ , φ ₁ , φ ₂ ,... When FIG. 13A) is sampled, when the phase relationship between the reference clock and the external clock is optimal, the difference value between successive sampling values becomes maximum. In the FIG. 13, the difference value d at the time of sampling by the external clock phi _1
21 is the largest. Therefore, a plurality of external clock phi ₀ phases different from each _other, phi _1, phi _2, and sequentially samples the reproduction reference clock in ..., each external clock phi _0, phi _1,
If the difference value of the sampling values at φ ₂ ,... is obtained, the peak value of the difference value is detected, and data is reproduced using an external clock having a phase at which the difference value has a peak, the phase of the external clock Compensation can be made.

Detection control of the peak value, the external clock phi ₀ the phase of the external _clock, phi _1, phi _2, one to proceed to the ... order, each external clock _{φ 0, φ 1, φ 2} , ... difference value d ₂₀ in, d ₂₁ , d ₂₂
.. Are sequentially compared to hold the larger difference value in the peak register and determine whether the current difference value is smaller than the peak value stored in the peak register. Can be realized by: That is, when the phase of the external clock is approaching the phase at which the peak value is reached, the current difference value is larger than the previous peak value of the difference value stored in the peak register up to the previous time. When the peak value is exceeded, the current difference value becomes smaller than the peak value of the previous difference value. Therefore, by detecting whether the current difference value has become smaller than the peak value of the difference value stored in the peak register up to the previous time, it is possible to determine whether the peak value has been reached.

By the way, if the disk has a defect, the reproduction reference clock fluctuates greatly. If noise is mixed in the reproduction reference clock, the reproduction reference clock is disturbed. Therefore, highly reliable external clock phase compensation cannot be performed only by controlling the peak value of the sampling value of the reproduced reference clock once. In order to perform highly reliable phase compensation of the external clock, control for detecting the peak value of the sampling value of the reproduction reference clock is performed a plurality of times, and by using the phase having the peak value obtained by the control multiple times, It is necessary to determine the optimal phase of the external clock.

Therefore, conventionally, the phase of the external clock is advanced to one in the order of the external clocks φ ₀ , φ ₁ , φ ₂ ,..., The difference values of the respective external clocks are sequentially compared, and the larger difference value is held in the peak register. The control to detect the peak value of the difference value is performed a plurality of times while determining whether the current difference value is smaller than the peak value stored in the peak register. For example, an average value of the phase of the external clock which becomes the peak value obtained in the step (1) is obtained, and the optimum phase of the external clock is obtained.

Thus, when performing the peak value detection control a plurality of times,
Conventionally, the direction in which the external clock is advanced is always the same for each control. That is, the phase of the external clock is advanced to one of the external clocks φ ₀ , φ ₁ , φ ₂ ,... In order, and control for detecting the peak value of the difference value is performed. Are advanced in the same direction in the order of the external clocks φ ₀ , φ ₁ , φ ₂ ,..., And the control for detecting the peak value of the difference value is repeated.

[Problems to be solved by the invention]

However, when performing the peak value detection control a plurality of times as described above, if the direction in which the external clock advances is always the same direction for each control, a long processing time is required until the optimum external clock phase is detected. Become.

That is, conventionally, when the peak value of the sampling value is detected, the phase of the external clock is returned to the initial value phase,
The peak value detection control is repeated from the initial value phase of the external clock. In this case, if the phase of the external clock, which is the peak value of the previous sampling value, is different from the initial value phase, it is necessary to greatly move the external clock phase in order to return the external clock phase to the initial value phase. If the phase of the external clock is largely changed, a setup time is required.

Further, it is highly possible that the phase of the external clock which becomes the peak value in the current control is near the phase of the external clock which becomes the peak value in the previous control. Therefore, if the current peak value detection control is started near the phase of the external clock that becomes the peak value in the previous control, the control time can be reduced. However, conventionally, since the current peak value detection control is started from the initial value phase, a long control time is required.

Therefore, an object of the present invention is to provide a phase compensation method capable of shortening the processing time when detecting the phase of the external clock at which the sampling value of the reference clock has a peak and detecting the optimal phase of the external clock. It is in.

[Means for solving the problem]

According to the present invention, a reference clock is recorded on a recording medium, and a phase compensation method for compensating a phase of an external clock using a reproduction signal of the reference clock is sequentially advanced to one side, and the phase is sequentially advanced to one side. The reproduced signal of the reference clock is sequentially sampled by the external clock to be obtained, a difference value of the sampled value is obtained, and the difference value of the current value is sequentially compared with the previous difference value or the peak value of the difference value so far. When the peak value is detected and the peak value of the difference value is detected, the phase of the external clock that becomes the peak value is output, and the phase of the external clock is sequentially advanced in the opposite direction. Is detected, and when the peak value is detected, the phase of the external clock that becomes the peak value is output, and the phase of the external clock is sequentially advanced in the opposite direction. By repeating the above control, the peak value of the difference value is detected, the phase of the external clock that becomes the peak value is output, and the phase of the external clock that becomes the peak value obtained by these multiple controls is used to determine the optimal external clock. This is a phase compensation method for detecting the phase of a clock.

[Action]

When performing peak detection control multiple times, the direction in which the phase of the external clock is advanced is reversed for each control, so setup time is not required before the next control, and the peak value is also used for the next control. Can be detected quickly, and the control time can be reduced.

〔Example〕

 Embodiments of the present invention will be described in the following order.

a. Regarding magneto-optical disk b. Configuration of one embodiment c. Description of flowchart of one embodiment d. Operation of one embodiment e. Operation when there is an error in reproduction reference clock f. Other embodiments g .Explanation of flowcharts of other embodiments h. Optimal phase detection circuit i.Explanation of flowchart of optimal phase detection circuit a. Magneto-optical disk The present invention relates to a sample servo type magneto-optical disk recording / reproducing apparatus which uses a reference clock. Is applied to perform phase compensation of the external clock. First, a sample servo type magneto-optical disk for recording such a reference clock will be described.

FIG. 2 shows the appearance of the magneto-optical disk 1. On the magneto-optical disk 1, for example, a spiral track T is formed. Each track T has multiple sectors S
, And data is recorded / reproduced for each of the sectors S0, S1, S2,.

Each of the sectors S0, S1, S2,... Is further divided into a plurality of segments as shown in FIG. Each segment is composed of a servo area and a data area.

In the servo area, as shown in FIG. 4, a pair of wobble pits P1 for obtaining a tracking error signal and
P2 is provided with the same amount of offset around the track center, and a clock reproduction pit P3 for reproducing an external clock is provided. Tracking servo control is performed based on the reproduced signals of the wobble pits P1 and P2. Further, an external clock is formed by the PLL based on the reproduction signal of the clock reproduction pit P3.

As shown in FIG. 3, the head segment of each sector is a header H1 for recording control information of each sector. Information such as an address and a sector mark is recorded in the header H1.

The subsequent segment is a header H2. In the header H2, a reference clock is recorded at the time of data recording.

As the reference clock, a clock having a frequency equal to the highest repetition frequency is used. The external clock is phase-compensated using the reference clock recorded in the header H2.

b. Configuration of One Embodiment FIG. 1 shows a configuration of one embodiment of the present invention.

In FIG. 1, an input terminal 11 is connected to the magneto-optical disk 1.
The reference clock reproduced from the header H2 (see FIG. 3) is supplied. The reproduction signal of the reference clock from the input terminal 11 is supplied to the A / D converter 12. The external clock selected by the selector 15 is supplied to the A / D converter 12. The reproduction signal of the reference clock from the input terminal 11 is
It is sampled by the external clock selected by the selector 15.

The input terminal 13 is supplied with an external clock. This external clock is formed by a PLL based on the reproduction signal of the clock reproduction pit P3 (see FIG. 4) in the servo area. An external clock from the input terminal 13 is passed through a cascade connection of a plurality of delay circuits (in this example, six stages of delay circuits 14A to 14F), and an output between the stages of the delay circuits 14A to 14F is selected by a selector.
Supplied to 15. The selector 15 is supplied with a select signal from the counter 16. The output of the selector 15 is supplied to the A / D converter 12 as a sampling clock.

A plurality of external clocks φ _{0 to} φ ₆ having different phases are output from between the stages of the delay circuits 14A to 14F. The value of the counter 16 is set according to the output from the controller 17.
The value of the counter 16 sets the selected state of the selector 15. The external clock selected by the selector 15 among the external clocks φ _{0 to} φ ₆ is supplied from the selector 15 to the A / D converter 12.

In this example, seven external clocks φ _{0 to} φ ₆ having different phases are formed by the delay circuits 14A to 14F. However, a large number of delay circuits are connected in cascade, and the external clocks having a larger number of phases are connected. The accuracy is improved by forming a clock.

The value of the counter 16 is supplied to the peak value phase register 18. The peak value phase register 18 is controlled according to the output from the controller 17. An output terminal 24 is derived from the peak value phase register 18.

The output of the A / D converter 12 is supplied to the subtraction circuit 19 via the register 20 while being supplied to the subtraction circuit 19. The subtraction circuit 19 and the register 20 determine a difference value between the sampling values output from the A / D converter 12.

The output of the subtraction circuit 19 is supplied to one input terminal of the comparison circuit 21 and is also supplied to the peak register 22. The state of the peak register 22 is set by the output of the controller 17. The output of the peak register 22 is supplied to the other input terminal of the comparison circuit 21.

The output of the comparison circuit 21 is supplied to the counter 23. The output of the counter 23 is supplied to the controller 17.

c. Description of Flowchart of One Embodiment FIG. 5 shows a flowchart of one embodiment of the present invention. Each variable and constant are set as follows.

D _O : Variable indicating the difference value output from the subtraction circuit 19 D _P : Variable indicating the peak value stored in the peak register 22 P _P : Variable indicating the phase value stored in the peak value phase register 18 M: Peak value phase constant indicating the number of protections after detecting m: variable indicates the count value of the counter 23 first, the peak value D _P of the peak register 22 is the initial value set to "0" (step 101).

Then, the counting direction of the counter 16 is set so that the counter 16 advances, for example, in the forward direction (step
102).

First, “0” is output from the counter 16 and the selector
15 external clock φ ₀ is selected in. The external clock phi ₀ is supplied to the A / D converter 12, the reproduction reference clock is sampled by an external clock phi _0.

In the subtraction circuit 19, the difference value D _O of the sampling value when sampled by an external clock phi ₀ is determined (step
103).

Whether this difference value D _O is larger than the peak value D _P of the peak register 22 is determined by the comparator circuit 21 (Step 10
Four).

The initial setting state, so there is a peak value D _P of the peak register 22 is "0" at step 101, towards the difference value D _O is greater than the peak value D _P of the peak register 22. Difference value D _O
There is greater than the peak value D _P, the count value m of the counter 23 is reset to "0" (step 105).

Then, the value of the counter 16 at this time is stored in the peak value phase register 18 (step 106). The value of the counter 16 at this time because "0", the phase value P _P stored in the peak value phase register 18 becomes "0". And the peak register
22 difference values D _O when this is stored (step 107), returns to step 103.

Then, the counter 16 is incremented to "1", the external clock phi ₁ is selected by the selector 15. This external clock φ ₁
Is supplied to the A / D converter 12, the reproduction reference clock is sampled by an external clock phi _1.

In the subtraction circuit 19, the difference value D _O of the sampling value when sampled by an external clock phi ₁ is determined (step
103).

Whether this difference value D _O is larger than the peak value D _P of the peak register 22 is determined by the comparator circuit 21 (Step 10
Four).

If not exceed the peak value of the difference value, towards the difference value D _O is greater than the peak value D _P of the peak register 22. When the difference value D _O is larger than the peak value D _P, the count value m of the counter 23 is reset to "0" (step 105).

Then, the value of the counter 16 at this time is stored in the peak value phase register 18 (step 106). The value of the counter 16 at this time since "1", the phase value P _P stored in the peak value phase register 18 becomes "1".

Then, the difference value D _O when this is stored in the peak register 22, it is returned to step 103.

Hereinafter, the counter 16 is "2", "3", is incremented ... to the external clock phi ₂ at the selector _15, phi _3, ... are sequentially selected, the external clock phi _2, phi _3, ... it is A / D Are sequentially supplied to the converter 12 and the reproduction reference clock is supplied to the external clock φ ₂ , φ
₃ , ... are sampled.

The subtraction circuit 19 sequentially obtains a difference value D _O of the sampling values when sampling is performed with the external clocks φ ₂ , φ ₃ ,... (Step 103), and the comparison circuit 21 calculates the difference value D _O from the peak value D _P. It is determined sequentially whether they are larger (step
104).

Exceeding the peak value of the difference value, the difference value D _O is smaller than the peak value D _P of the peak register 22.

When the difference value D _O becomes smaller than the peak value D _P , the counter
23 is incremented (step 108).

It is determined whether the count value of the counter 23 has reached a predetermined number of protections M (for example, M = 3) (step 10).
9).

If the count value of the counter 23 has not reached the predetermined number of protections M, the process returns to step 103.

Then, a sampling value D _O at the time of sampling with the next external clock is obtained (step 103), and the difference value D _{O is obtained.}
It is compared with the peak value D _P (step 104).

If the peak value is exceeded, the difference value D _O is again changed to the peak value D _P
Since it is smaller, the counter 23 is further incremented (step 108).

When the count value of the counter 23 reaches a predetermined number of protections M, the phase value P _P stored in the peak value phase register 18
Is output from the output terminal 24 (step 110).

Then, the counting direction of the counter 16 is reversed (step 111).

Then, the difference value D _O when this is stored in the peak register 22 (step 112), returns to step 103, is reversed phase direction of the external clock, same control as described above is performed.

 The above control is repeated a plurality of times.

d. Description of Operation of One Embodiment The operation of one embodiment of the present invention will be described.

As described above, the reproduction reference clock signal from the input terminal 11 is sequentially sampled by the external clocks φ _{0 to} φ ₆ sequentially selected by the selector 15. When the clock with the highest repetition frequency is used as the reference clock,
When the relationship between the phase of the reference clock and the phase of the external clock becomes optimal, the difference between the sampling values becomes the peak value. Therefore, if the external clock phase at which the difference between the sampling values reaches the peak value is detected, the external clock phase can be compensated.

When the phase of the external clock is sequentially changed to one side, when the difference value approaches the peak value, the current difference value is larger than the previous difference value, and when the difference value exceeds the peak value, The current difference value is smaller than the difference value up to.

Therefore, the peak value of the difference value up to the previous time is stored in the peak register 22, and the current difference value and the peak register are stored.
The current difference value is compared with the previous peak value stored in the peak register 22. If the current difference value is larger than the previous peak value stored in the peak register 22, the current difference value is stored in the peak register 22. Store, the difference value of this time is a peak register
If it is determined that the difference value has reached the peak value when it becomes smaller than the previous peak value stored in 22, the peak value of the difference value can be detected.

However, since the header H2 of the magneto-optical disk 1 may be defective or the reproduction reference clock may contain noise, the peak value of the difference value obtained by one peak value detection control is not reliable. Is low. Therefore, it is necessary to repeat the control for detecting the peak value of the difference value as described above a plurality of times. However, if the process of detecting the peak value of the difference value by sequentially changing the phase of the external clock to one is repeatedly performed a plurality of times, a long processing time is required.

Therefore, in one embodiment of the present invention, when the peak value of the difference value is detected, the phase of the external clock is advanced in the opposite direction, and the control of detecting the peak value of the difference value is repeated a plurality of times. If the phase of the external clock is advanced in the opposite direction when the peak value of the difference value is detected, it is not necessary to greatly shift the phase of the external clock when moving to the next peak value detection control of the difference value. Is unnecessary. Also, since the peak value of the next difference value is likely to have substantially the same phase as the peak value of the previous difference value,
The peak value of the difference value can be detected without a large phase shift.

That is, as shown in FIG. 6A, the counter 16 is advanced in the forward direction (0, 1, 2, 3,...). The external clocks φ ₀ , φ ₁ , φ ₂ ,... Are sequentially output from the selector 15 in which the counter 16 advances in the forward direction so that the delay amount increases sequentially as shown in FIG. 6C. FIG. 6B shows an external clock supplied to the input terminal 13.

The external clock φ ₀ , φ ₁ , φ selected by the selector 15
_2, ... are sequentially supplied to the A / D converter 12. As shown in FIG. 6D, the reproduced signals of the reference clocks are sequentially sampled by the A / D converter 12 using the external clocks φ ₀ , φ ₁ , φ ₂ ,. As a result, sampling values at each of the external clocks φ ₀ , φ ₁ , φ ₂ ,... Are sequentially obtained.

As shown in FIG. 6E, the difference values d ₀ , d ₁ , d ₂ ,... Of the sampling values are sequentially obtained by the subtraction circuit 19 and the register 20.

The peak register 22 stores the peak value of the difference value up to the previous time. The comparison circuit 21 compares the peak value of the difference value up to the previous time stored in the peak register 22 with the difference value of the current sampling value.

Here, if the phase change direction of the external clock approaches the peak value of the difference value, the difference value of the current sampling value becomes larger than the peak value of the difference value stored in the peak register 22 up to the previous time. . When the difference value exceeds the peak value, the difference value of the current sampling value becomes smaller than the previous difference value stored in the peak register 22, and it is detected that the peak value has been reached.

When the difference value of the current sampling value is larger than the peak value of the difference value up to the previous time, the value of the peak register 22 is updated to the difference value of the current sampling value, and the value of the counter 16 at this time is changed to the peak value phase register. Stored in 18. At this time, the counter 16 continues counting in the same direction.

That is, in the example of FIG. 6, the counter 16 is "0" to "3".
Until is counted, the difference values d ₀ , d ₁ , d ₂ , and d ₃ of the current sampling value are larger than the peak values of the difference values up to the previous time. At this time, as shown in FIG. 6F, the value of the peak register 22 is sequentially updated to d ₀ , d ₁ , d ₂ , and d ₃ . At the same time, as shown in FIG. 6H, the values "1", "2", and "3" of the counter 16 at this time (FIG.
Are sequentially stored.

When the difference value of the current sampling value becomes smaller than the previous peak value of the difference value, the contents of the peak value phase register 18 at this time are output as the peak value phase, and the counting direction of the counter 16 is reversed. . And
The value of the peak register 22 is updated to a difference value of the current sampling value.

That is, in the example of FIG. 6, when the value of the counter 16 (FIG. 6A) is counted from “3” to “4”, the difference value d ₄ of the current sampling value is equal to the peak value of the difference value up to the previous time. smaller than the value (the difference value d ₃ in this case). At this time, as shown in FIG.
The value "3" stored in 18 is output from the output terminal 24 as the peak value phase, and the counting direction of the counter 16 is reversed as shown in FIG. 6G. Thus, the phase phi ₃ as a peak value d ₃ is detected. Then, as shown in FIG. 6 F, the value of the peak register 22 is changed to the difference value d ₄ of the current sampling value.

The counting direction of the counter 16 is reversed, and the same control is repeated.

That is, in the example of FIG. 6, the counting direction of the counter 16 is reversed, and the next counter value becomes “3”. And
The difference between the peak value stored in the peak register 22 and the current sampling value is compared. As shown in FIG. 6 E, the value of the peak register 22 at this time is d _4, the difference value of the current sampling value is d _5, peaks towards the d ₅ of the difference value of the current sampling values greater than the value d ₄ of the register 22. Accordingly, as shown in FIG. 6 F, together with the value of the peak register 22 is changed to d ₅ from d _4, the value "3" of the counter 5 at this time is stored in the peak value phase register 18.

Then, the value of the counter 16 becomes “2”. As shown in FIG. 6 F, the value of the peak register 22 at this time was d _5,
The difference value d ₆ of the current sampling value is the peak register
22 value d ₅ less than the. Accordingly, as shown in FIG. 6I, the value “3” stored in the peak value phase register 18 at this time is output from the output terminal 24 as the peak value phase, and as shown in FIG. The counting direction of the counter 5 is reversed.

Hereinafter, similar control is repeated. As a result, the sixth
As shown in FIG. I, the peak value phases “3”, “3”, “3”,... Detected from the output terminal 24 are sequentially output.

e. Operation when there is an error in the reproduction reference clock The example of FIG. 6 shows a case where the disc has no defect. In this case, phase a peak value detected by the peak value detection control is always phi _3, so that the peak value phase "3" is always outputted from the output terminal 24.

If the disk is defective, the reference clock will fail. In this embodiment, a large error is not caused in the peak value phase even when the reference clock has an error.

In FIG. 7, the reference clock in the portion indicated by E1 (FIG. 7D) has an error. When the reference clock of the portion indicated by E1 is in error, as shown in FIG.
₁₅ becomes very small. The difference value d ₁₅ is the difference value when the sampled reference clock with an external clock phi _3, and serves as a original peak value.

FIG. 7 shows the peak value detection control of the difference value in such a case.

Until the value of the counter 16 (FIG. 7A) is counted from “0” to “3”, the difference value of the current sampling value is d ₁₀ ,
Since d ₁₁ , d ₁₂ , and d ₁₃ increase in order, the values of the peak register 22 are sequentially updated to d ₁₀ , d ₁₁ , d ₁₂ , and d ₁₃ as shown in FIG. As shown at H, the values “1”, “2”, and “3” of the counter 16 at this time are stored in the peak value phase register 18.
Are sequentially stored.

When the counter 16 is counted from “3” to “4”,
Since the difference value d ₁₄ of the current sampling value is smaller than (the difference value d ₁₃ in this case) the peak value of the difference value to the last, as shown in FIG. 7 I, the peak value phase register 18 The stored value "3" is output from the output terminal 24 as the peak value phase, and the counting direction of the counter 16 is reversed as shown in FIG. 7G. And
As shown in FIG. 7 F, the value of the peak register 22 is changed to the difference value d ₁₄ of the current sampling value.

Since the count value of the counter 16 is reversed, the count value of the next counter 16 becomes “3”. As shown in FIG. 7 E, the value of the peak register 22 at this time was d _14, the difference value of the current sampling value is d _15. This difference value d ₁₅
Is an error and its value is very small. Therefore, the difference value d ₁₅ of the current sampling value is smaller than the peak value d ₁₄ of the differential value up to the previous. For this reason, as shown in FIG. 7I, the value "3" stored in the peak value phase register 18 is output from the output terminal 24 as the peak value phase, and as shown in FIG. The 16 count directions are reversed. Then, as shown in FIG. 7 F, the value of the peak register 22 is changed to the difference value d ₁₅ of the current sampling value.

Since the count value of the counter 16 is reversed, the count value of the next counter 16 becomes “4”. Then, the difference between the peak value stored in the peak register 22 and the current sampling value is compared. As shown in FIG. 7 E, the value of the peak register 22 at this time was d _15, the difference value of the current sampling value is d _16, the peak register towards the difference value d ₁₆ of the current sampling values 22 greater than the value d ₁₅ of. Accordingly, as shown in FIG. 7 F, peak with the value of the register 22 is amended from d ₁₅ to d _16, a seventh value "4" is the peak value phase register of the counter 16 at this time as shown in FIG. H Stored in 18.

Next, the value of the counter 16 becomes “5”. Sixth, as shown in FIG E, the value of the peak register 22 at this time was d _16, the peak register 2 is more difference values d ₁₇ of the current sampling values
Less than a value of 2 d _16. Accordingly, as shown in FIG. 7I, the value "4" stored in the peak value phase register 18 at this time is output from the output terminal 24 as the peak value phase, and as shown in FIG. The counting direction of the counter 16 is reversed.

Hereinafter, similar control is repeated. As a result, the seventh
As shown in FIG. I, the detected peak value phases “3”, “3”,
"4", "3" ... are sequentially output. If average these peak values phase, the optimum peak phase phi ₃ is obtained.

In the above description, in order to simplify the explanation, when the difference value of the current sampling value becomes smaller than the previous peak value, it is immediately determined that the difference has exceeded the peak value, and the phase of the external clock of the peak value is determined. And the direction in which the phase of the external clock is variable is inverted. However, because of the influence of noise, if it is determined that the current sampling value exceeds the peak value immediately after the current sampling value becomes smaller than the previous peak value, erroneous detection is likely. Therefore, as shown in FIG. 1, a counter 23 that counts the output of the comparison circuit 21 is provided, and the difference value of the current sampling value is M times (for example, three times) continuously from the previous peak value. If it becomes smaller, it is determined that the peak value has been exceeded, and the phase of the external clock having the peak value is output, and the phase of the external clock is inverted.
This control is realized by the processing of steps 108 and 109 in the flowchart shown in FIG.

f. Another embodiment FIG. 8 shows another embodiment of the present invention.

In FIG. 8, a reference clock reproduced from the header H2 of the magneto-optical disk 1 is supplied to an input terminal 31.
The reproduction signal of the reference clock from the input terminal 31 is supplied to the A / D converter 32. The external clock selected by the selector 35 is supplied to the A / D converter 32. The reproduction signal of the reference clock from the input terminal 31
Is sampled by the external clock selected in step (1).

The input terminal 33 is supplied with an external clock. This external clock is formed by a PLL based on a reproduction signal of the clock reproduction pit P3 in the servo area. An external clock from the input terminal 33 is passed through a cascade connection of a plurality of delay circuits (in this example, six-stage delay circuits 34A to 34F), and the delay circuit 34
Outputs between the stages A to 34F are supplied to the selector 35. The selector 35 is supplied with a select signal from the counter 36.
The output of the selector 35 is supplied to the A / D converter 32 as a sampling clock.

The value of the counter 36 is supplied to a peak value phase register 38. The peak value phase register 38 is controlled according to the output from the controller 37. An output terminal 45 of the peak value phase is derived from the peak value phase register 38.

The output of the A / D converter 32 is supplied to the subtraction circuit 39 and also to the subtraction circuit 39 via the register 40. The subtraction circuit 39 and the register 40 calculate the difference between the sampling values output from the A / D converter 32.

The output of the subtraction circuit 39 is supplied to one input terminal of the comparison circuit 40 and one input terminal of the comparison circuit 41, and is also supplied to the previous value register 42 and the peak register 43. The output of the previous value register 42 is supplied to the other input terminal of the comparison circuit 40.
The output of the peak register 43 is supplied to the other input terminal of the comparison circuit 41.

The output of the comparison circuit 40 is supplied to the counter 44. The output of the counter 44 is supplied to the controller 37. Comparison circuit 41
Is supplied to the controller 37.

g. Description of Flowchart of Another Embodiment FIG. 9 shows a flowchart of another embodiment of the present invention. Each variable and constant are set as follows.

D _aO : Variable indicating difference value output from subtraction circuit 39 D _aP : Variable indicating peak value stored in peak register 43 D _a-1 : Variable indicating previous difference value stored in previous value register 42 P _aP : peak value phase register 38 to a variable indicating the phase value stored M _a: constant indicating the number of protections after the peak value phase detecting m _a: variable indicates the count value of the counter 44 is first, last differential value before value register 42 _Da-1 is initialized to "0" (step 201).

The peak value _DaP of the peak register 43 is initialized to “0” (Step 202).

Then, the counting direction of the counter 36 is set so that the counter 36 advances, for example, in the forward direction (step
203).

First, “0” is output from the counter 36 and the selector
External clock φ ₀ is selected at 35. The external clock phi ₀ is supplied to the A / D converter 32, the reproduction reference clock is sampled by an external clock phi _0.

In the subtraction circuit 39, the difference value D _aO-sampling value when sampled by an external clock phi ₀ is determined (step 204).

The comparison circuit 40 determines whether or not the difference value _DaO is larger than the previous difference value _{Da -1} of the previous value register 42 (step 205).

In the initial state, since the previous difference value _Da-1 of the previous value register 42 is set to "0" in step 201, the difference value D
_aO is larger than the previous difference value _{Da -1} of the previous value register 42. Difference value D _aO-is when the last is greater than the difference value D _a-1, the count value m _a counter 44 is reset to "0" (step 206).

Then, the difference value D _aO-whether greater than the peak value D _aP are stored in the peak register 43 is determined (step 207).

In the initial state, since the peak value D _aP peak register 43 at step 202 is "0", towards the difference value D _aO-is greater than the peak value D _aP. When the difference value D _aO-is greater than the peak value D _aP, the value of the counter 36 is stored in peak value phase register 38. Since the value of the counter 36 at this time is “0”, the phase value _PaP stored in the peak value phase register 38
Becomes "0" (step 208).

Then, the difference value _DaO at this time is stored in the peak register 43 (step 209).

Then, the difference value _DaO is stored in the previous value register 42 (step 210).

 Then, the process returns to step 204.

Then, the counter 36 is incremented to "1", the external clock phi ₁ is selected by the selector 35. This external clock φ ₁
Is supplied to the A / D converter 32, the reproduction reference clock is sampled by an external clock phi _1.

In the subtraction circuit 39, the difference value D _aO-sampling value when sampled by an external clock phi ₁ is determined (step 204).

The comparison circuit 40 determines whether or not the difference value _DaO is larger than the previous difference value _{Da -1} of the previous value register 42 (step 205).

If the difference value does not exceed the peak value, the difference value _DaO is larger than the previous difference value Da _-1 .

If the difference value D _aO is larger than the previous difference value D _a-1 ,
Count value m _a counter 44 is reset to "0" (step 206).

Then, the difference value D _aO-whether greater than the peak value D _aP are stored in the peak register 43 is determined (step 207).

If not exceed the peak value of the difference value, towards the difference value D _aO-is greater than the peak value D _aP. Difference value D _aO is peak value
If it is larger than _DaP , the value of the counter 36 is stored in the peak value phase register 38. The value of the counter 36 at this time since "1", the phase value P _P stored in the peak value phase register 38 becomes "1" (step 208).

Then, the difference value _DaO at this time is stored in the peak register 43 (step 209).

Then, the difference value _DaO is stored in the previous value register 42 (step 210).

 Then, the process returns to step 204.

Note that when a larger peak value D _aP the difference value D _aO-is stored in the peak register 43 in step 207, proceeds to step 210, the difference value D _aO-is stored in the previous value register 42.

Hereinafter, the counter 36 is "2", "3", is incremented ... to the external clock phi ₂ at the selector _35, phi _3, ... are sequentially selected, the external clock phi _2, phi _3, ... it is A / D is supplied to the converter 32, the reproduction reference clock is an external clock phi _2, phi _3,
Sampled by ...

In the subtraction circuit 39, the external clock phi _2, phi _3, ... difference value D _aO-sampled values when the sampling is sequentially calculated by (step 204), the difference value D _O is the previous difference value D in the comparison circuit 40 _It is sequentially determined whether the value is larger than _a-1 (step 205).

When the difference value exceeds the peak value, the difference value _DaO becomes smaller than the previous difference value _{Da -1} .

If the difference value _DaO becomes smaller than the previous difference value _{Da -1} ,
The counter 44 is incremented (step 211).

When the count value of the counter 44 is equal to a predetermined protection number M _a (for example,
It is determined whether or not M _a = 3) has been reached (step 21).
2).

If the count value of the counter 44 has not reached the predetermined number of protections M _a, the difference value D _a is stored in the previous value register 42, it is returned to step 204.

Then, a sampling value _DaO at the time of sampling with the next external clock is obtained (step 204), and the difference value _DaO is obtained.
_aO is _compared with the previous difference value _{Da -1} (step 20).
Five).

If it exceeds the peak value, the difference value _DaO becomes smaller again than the previous difference value _{Da -1} , so the counter 44 is further incremented (step 211).

When the count value of the counter 44 reaches a predetermined number of protections M _a, it is determined that monotonic decrease exceeds a peak since the proceeding, the phase value P _aP are stored in the peak value phase register 38 is output from the output terminal 45 (Step 214).

Then, the difference value _DaO is stored in the peak register 43 (Step 215).

Then, the counting direction of the counter 36 is reversed (step 216).

Then, the difference value _DaO at this time is stored in the previous value register 42 (step 217).

 Then, the process returns to step 204.

 The above control is repeated a plurality of times.

If the change of the difference value of the sampling value with respect to the phase change of the external clock becomes as shown in FIG.
The peak of the difference value should be detected at the n _P- th phase. However, the difference value of the n _0th time is larger due to noise,
n ₊₁ th, when n ₊₂ th, n ₊₃ th difference value is smaller than n ₀ th difference value, in the control of an embodiment described above, when the number of protections m is 3, n _0-th difference The value is determined to be the peak value. In contrast, in this embodiment, when the (n _{+ 1)} th difference value is obtained, it is determined that the difference is not monotonically decreasing.
n Does not erroneously detect the _0th difference value as a peak value.

h. Optimal phase detection circuit FIG. 11 is an example of an optimal phase detection circuit that determines an optimal phase of an external clock using a peak detection phase value obtained by a plurality of repetitive controls.

In FIG. 11, a peak detection phase value obtained by a plurality of controls is supplied to an input terminal 50. This peak detection phase value is output from the output terminal 24 in FIG. 1 or the output terminal 45 in FIG. The peak detection phase value from the input terminal 50 is supplied to the registers 51, 52, 53, and also to one input terminal of the comparison circuits 55, 56, 57.

The input / output of the registers 51, 52, 53 is controlled by the controller 58. The register 51 stores the maximum value, the register 52 stores the next largest value, and the register 53 stores the minimum value. The value of register 51 can be transferred to register 52,
The value of 52 can be transferred to the register 53. The value of the register 53 can be transferred to the register 52,
The value of 52 can be transferred to the register 51.

The output of the register 51 is supplied to the other input terminal of the comparison circuit 55, and is also supplied to an averaging circuit 59. Comparison circuit 55
Then, the input peak detection phase value is compared with the value of the register 51. The output of the register 52 is supplied to a comparison circuit 56 and also to an averaging circuit 59. The comparison circuit 56 compares the input peak detection phase value with the value of the register 52. The output of the register 53 is supplied to a comparison circuit 57 and also to an averaging circuit 59. The comparison circuit 57 compares the input peak detection phase value with the value of the register 53. Also, register 51
And the output of the register 53 are supplied to the comparison circuit 60.
The comparison circuit 60 detects whether the value of the register 51 and the value of the register 53 are within a predetermined value.

The output of the comparison circuit 55, the output of the comparison circuit 56, and the output of the comparison circuit 57 are supplied to the controller 58. The output of the comparison circuit 60 is supplied to the controller 58.

The state of the averaging circuit 59 is controlled by the output of the controller 58. The outputs of the registers 51 to 53 are averaged by the averaging circuit 59, and an optimum phase is obtained. This averaging circuit 59
Is output from the output terminal 61.

i. Description of Flowchart of Optimal Phase Detection Circuit FIG. 12 shows a flowchart of the above-described optimal phase detection circuit. Note that each variable is defined as follows.

φR ₀ : peak detection phase value from input terminal 50 φR ₁ : value of register 51 storing the largest value φR ₂ : value of register 52 storing the next largest value φR ₃ : value n of register 53 storing the smallest value : Number of Data Acquisitions First, the number n of data acquisitions is initialized to “0” (step 301).

The peak detection phase value φR ₀ is input from the input terminal 50 (step 302).

The number n of times of data acquisition is incremented (step 303).

It is determined whether the number n of times of data acquisition is “3” or less (step 304).

If the number n of data acquisitions is equal to or less than "3", it is determined whether the number n of data acquisitions is "1" (step 30).
Five).

If the number n of times of data acquisition is “1”, the input peak detection phase value φR ₀ is set to the value φR _{1 of the} register 51 (step 30).
6) Return to step 302.

If the number of data acquisitions n is not "1", it is determined whether the number of data acquisitions n is "2" (step 30).
7).

If the number n of times of data acquisition is “2”, the input peak detection phase value φR ₀ is compared with the value φR _{1 of the} register 51 (step 308).

In step 308, if the input peak detection phase value φR ₀ is larger than the value φR _{1 of} the register 51, the value φR _{1 of the} register 51 is set to the value φR _{2 of the} register 52 (step 309), and the input peak detection phase value φR ₀ is The value φR of register 52 is set to ₁ (step
310), returning to step 302.

In step 308, if the input peak detection phase value φR ₀ is smaller than the value φR _{1 of the} register 51, the input peak detection phase value φR
R ₀ is the value .phi.R ₂ of the register 52 (step 311), returns to step 302.

If n is not "2" in step 307, it is determined that the number n of times of data acquisition is "3" (step 312).
If the number n of data acquisitions is "3", the input peak detection phase value φR ₀ is compared with the value φR _{1 of the} register 51 (step 313).

If the input peak detection phase value φR ₀ is larger than the value φR _{1 of the} register 51, the value φR ₂ of the register 52 is changed to the value φR _{3 of the} register 53.
Is (step 314), the value .phi.R ₁ of the register 51 is set to the value .phi.R ₂ of the register 52 (step 315), the input peak detection phase value .phi.R ₀ is a value .phi.R ₁ of the register 51 (Step 31
6) Return to step 302.

In step 313, if the input peak detection phase value φR ₀ is smaller than the value φR _{1 of the} register 51, the input peak detection phase value φR ₀
Whether R ₀ is between the values .phi.R ₂ values .phi.R ₁ and the register 52 of the register 51 is determined (step 317).

At step 317, if the input peak detection phase value φR ₀ is a value between the value φR _{1 of the} register 51 and the value φR ₂ of the register 52, the value φR _{2 of the} register 52 is set to the value φR _{3 of the} register 53 ( (Step 318), the input peak detection phase value φR ₀ is set to the value φR _{2 of the} register 52 (Step 319), and the process returns to Step 302.

If the input peak detection phase value φR ₀ is not between the value φR _{1 of the} register 51 and the value φR _{2 of the} register 52, it is determined that the input peak detection phase value φR ₀ is equal to or less than the value φR _{2 of the} register 52 (step
320), the input peak detection phase value φR ₀ is
_{It is set to 3} (step 321), and the process returns to step 302.

Through the above steps 301 to 321, when three input peak detection phase values are fetched from the initial state, the largest value among them is set to the value φR _{1 of the} register 51, and the next largest value is set to the value φR _{2 of the} register 52. It is set to the minimum value is set to a value .phi.R ₃ of register 53.

If the number of data acquisitions n becomes equal to or more than "3" in step 304, the input peak detection phase value φR ₀ is set to the value φ of the register 51.
Whether greater than R ₁ is judged (step 322).

If the input peak detection phase value φR ₀ is larger than the value φR _{1 of the} register 51 storing the maximum value, the previous values of the register 51 and the register 52 are sequentially shifted to the lower registers 52 and 53, respectively. The input peak detection phase value is stored in the register 51 for storing the value, and the previous value of the register 53 for storing the minimum value is played. That is, when the input peak detection phase value is greater than the value .phi.R ₁ of the register 51, the value .phi.R ₂ of register 52 is set to the value .phi.R ₅₃ of the register 53, (step 323), the value .phi.R ₁ of the register 51 is a register 52 is a value .phi.R _52, are (step 324), the value .phi.R ₅₁ of the input peak detection phase value .phi.R ₀ registers 51 (step 325). The value φR ₃ previously stored in the register 54 is discarded. Then go to step 336.

In step 322, the input peak detection phase value φR ₀ is
If the value of ₁ is smaller than φR ₁ , the input peak detection phase value φR ₀
There whether between values .phi.R ₂ of register 52 for storing the next largest value as the value .phi.R ₁ of the register 51 for storing the maximum value is determined (step 326).

When the input peak detection phase value φR ₀ is between the value φR _{1 of the} register 51 and the value φR ₂ of the register 52, the value of the register 52 is shifted to the register 53, and the input peak detection phase value is stored in the register 52. The value stored in the register 53 is played back. That is, when the input peak detection phase value φR ₀ is between the value φR _{1 of the} register 51 and the value φR ₂ of the register 52, the value φR _{2 of the} register 52 is set to the value φR _{3 of the} register 53 (step 327). ), The input peak detection phase value φR ₀ is set to the value φR _{2 of the} register 52 (step 328). The value φR ₃ previously stored in the register 53 is discarded. Then go to step 336.

In step 326, if the input peak detection phase value φR ₀ is not between the value φR _{1 of the} register 51 and the value φR _{2 of the} register 52,
The value φR _{2 of the} register 52 for storing the next largest input phase detection phase value φR ₀ and the value φR _{3 of the} register 53 for storing the minimum value
Is determined (step 329).

When the input peak detection phase value φR ₀ is between the value φR ₂ of the register 52 and the value φR _{3 of the} register 53, the value φR ₂ of the register 52 is shifted to the register 51, and the input peak detection phase The value is stored, and the previous value of the register 51 is played. That is, when the input peak detection phase value φR ₀ is between the value φR ₂ of the register 52 and the value φR _{3 of the} register 53, the value φR _{2 of the} register 52 is set to the value φR _{1 of the} register 51 (step 330). ), The input peak detection phase value φR ₀ is set to the value φR _{2 of the} register 52 (step 331). Register 51
The value φR ₁ stored so far is discarded. Then go to step 336.

In step 329, if the input peak detection phase value φR ₀ is not between the value φR ₂ of the register 52 and the value φR _{3 of the} register 53,
It is determined that the input peak detection phase value φR ₀ is equal to or smaller than the value φR _{3 of the} register 53 storing the minimum value (step 33).
2).

If the input peak detection phase value φR ₀ is equal to or smaller than the value φR _{3 of} the register 53, the previous values of the registers 52 and 53 are sequentially shifted to the upper registers 51 and 52, respectively, to store the minimum value. The input peak detection phase value is stored in the register 51, and the previous value of the register 51 storing the maximum value is played back. That is, the input peak detection phase value φR ₀ is
In the case of 53 values .phi.R ₃ or less, the value .phi.R ₂ of register 52 is set to the value .phi.R ₁ of the register 51 (step 333), the value .phi.R ₃ of register 53 is set to the value .phi.R ₂ of the register 52 (step 334) ,
The input peak detection phase value φR ₀ is set to the value φR _{3 of the} register 53 (step 335). The value φR ₁ previously stored in the register 52 is discarded. Then go to step 336.

Steps 332 to 335 remove the input peak detection phase value that is greatly deviated from the input peak detection phase value.
51 stores the largest peak detection phase value, register 52 stores the next largest peak detection phase value, and register 53 stores the smallest peak detection phase value.

In step 336, the difference between the value .phi.R ₁ and value .phi.R ₃ of register 53 in register 51 whether within a predetermined amount is determined. If the difference between the value φR _{1 of the} register 51 and the value φR _{3 of the} register 53 is not the predetermined amount (H), the process returns to the step 302. When the difference between the value φR _{1 of the} register 51 and the value φR _{3 of the} register 53 is within a predetermined amount, the average of the value φR _{1 of the} register 51, the value φR _{2 of the} register 52, and the value φR _{3 of the} register 53 is obtained. (Step 337).

As described above, in this optimum phase detection circuit, a peak detection phase value obtained by a plurality of control operations that has a greatly deviated value is excluded, and the difference between the maximum value and the minimum value is within a predetermined value. , The peak detection phase values are averaged. For this reason, the peak detection phase value error can be reduced.

〔The invention's effect〕

According to the present invention, when performing the peak detection control a plurality of times, the direction in which the phase of the external clock is advanced is reversed for each control. By inverting the direction in which the phase of the external clock is advanced for each control, when the next control is performed after the peak value of the sampling value is detected, the phase of the external clock must be advanced by one step in the opposite direction. , So setup time is not required.

Also, since the phase of the external clock that becomes the peak value in the current control is likely to be near the phase of the external clock that becomes the peak value in the previous control, the phase of the external clock is advanced for each control. If the direction is reversed, the peak value can be detected in a short time.

 Therefore, the processing time can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a plan view showing an outline of an optical disk to which the present invention can be applied, FIG. 3 is a schematic diagram used for describing an optical disk to which the present invention can be applied, and FIG. FIG. 4 is a schematic diagram used for explaining a servo area of an optical disk to which the present invention can be applied, FIG. 5 is a flowchart used for explaining one embodiment of the present invention, and FIGS. 6 and 7 are one embodiment of the present invention. FIG. 8 is a block diagram showing another embodiment of the present invention.
FIG. 9 is a flowchart used for explaining another embodiment of the present invention, FIG. 10 is a graph used for explaining another embodiment of the present invention, FIG. 11 is a block diagram showing an example of an optimum phase detecting circuit, and FIG. FIG. 13 is a flowchart used to explain an optimum phase detection circuit, and FIG. 13 is a timing chart used to explain a conventional data reproducing apparatus. Description of main reference numerals in the drawings 11, 31: input terminal of reproduction signal, 13, 33: input terminal of external clock, 15, 35: selector, 12, 32: A / D converter, 16, 36:
Counter, 19, 39: Subtraction circuit, 22, 43: Peak register, 2
1,40,41: Comparator circuit, 18,38: Peak value phase register, 42:
Previous value register.

Claims (1)

(57) [Claims] A reference clock is recorded on a recording medium,
In the phase compensation method of performing phase compensation of an external clock using the reproduction signal of the reference clock, the external clock phase is sequentially advanced to one side, and the external clock whose phase is sequentially advanced to one side is used to reproduce the reference clock reproduction signal. Sampling is sequentially performed, a difference value of the sampled value is obtained, and a difference value of the difference value is detected by sequentially comparing the current difference value with the previous difference value or the peak value of the difference value so far. When the peak value is detected, the phase of the external clock that becomes the peak value is output, and the phase of the external clock is sequentially advanced in the opposite direction. Then, the phase of the external clock which becomes the peak value is output, and the phase of the external clock is sequentially advanced in the opposite direction. Thereafter, the same control is repeated. Detect the peak value of the difference value, output the phase of the external clock that becomes the peak value, and detect the optimal external clock phase using the phase of the external clock that becomes the peak value obtained through these multiple controls. Phase compensation method.