JP3038708B1 - Charge pump type booster circuit - Google Patents

Abstract

Abstract: PROBLEM TO BE SOLVED: To eliminate a fluctuation of an output voltage synchronized with a driving pulse. SOLUTION: Output terminals N11, N2 of a first booster circuit 4 are provided.
1 have drive pulses φ1 and φ2, respectively.
1 and C21, while the second booster 5
Drive pulses φ1,
φ2 is exchanged and supplied via capacitors C12 and C22. Therefore, the drive pulses φ1, φ2 are transmitted through the gate-source overlap capacitances Co2, Co3.
Even if the influence of the voltage change 2 appears at the circuit output terminal 3, the voltage fluctuations are in opposite phases, and thus cancel each other out, and the fluctuation of the output voltage synchronized with the drive pulse is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge pump type booster circuit.

[0002]

2. Description of the Related Art In a solid-state image pickup device or the like using a battery as a power supply, a charge pump type booster circuit is used to obtain a required voltage. However, there is a voltage fluctuation synchronized with the driving pulse in the voltage boosted and generated by the conventional charge pump booster circuit, and this voltage fluctuation may adversely affect a circuit using the boosted voltage as a power supply as a voltage fluctuation noise. Was.

First, a conventional charge pump type booster circuit will be described with reference to the drawings. FIG. 3 is a circuit diagram showing an example of a conventional charge pump type booster circuit. The charge pump type booster circuit 102 is connected to the power supply 1 (VD
D) is boosted to nearly three times, and N is used in which the gate and the drain are connected in common between the power supply 1 and the circuit output terminal 3.
In this configuration, three (N-type) MOS transistors are connected in series such that the forward direction matches the direction toward the output terminal 3. The first-stage NMOS transistor M1 has a gate and a drain connected to the power supply 1, and the second-stage NMOS transistor M2 has a gate and a drain of NM.
The third-stage NMO is connected to the output terminal N1 of the OS transistor M1.
The S-transistor M3 has a gate and a drain connected to the output terminal N2 of the NMOS transistor M2, respectively.
The source of the S transistor M3 is connected to the circuit output terminal 3. Then, a load capacitance CL exists between the circuit output terminal 3 and the ground (reference potential point).

A final stage NMOS transistor M3
A transistor M3 is connected between the gate of
The gate-source overlap capacitance Co1 of FIG.
Are surrounded by a dotted frame A). Then, the first-stage and second-stage NMOS transistors M1 and M2
Are applied to the output terminals N1 and N2 through capacitors C1 and C2, respectively. The change width of the voltages of the drive pulses φ1 and φ2 is substantially equal to the power supply voltage.

[0005] Next, the operation of the conventional charge pump type booster circuit 102 configured as described above will be described. 4A to 4C are timing waveform diagrams showing the operation of the charge pump type booster circuit 102 in FIG.
(A) and (B) show the drive pulses φ1 and φ2, respectively, and (C) shows the boosted voltage at each stage. In FIG. 4C, the solid line is the power supply voltage, the dotted line is the boosted voltage V1 at the output terminal N1, the one-dot chain line is the boosted voltage V2 at the output terminal N2, and the two-dot chain line is the final boosted voltage VOUT at the circuit output terminal 3. Represents.

First, immediately after the power supply 1 is turned on, the NMOS transistors M1, M2 and M3 are all conducting. When the drive pulse φ1 is input via the capacitor C1 in this state, first, when the drive pulse φ1 is at the L (low) level, the drain and gate of the NMOS transistor M1 have the same potential as the power supply voltage VDD. N1 becomes a potential (VDD-VT1) lower than the power supply voltage VDD by the threshold voltage VT1 of the NMOS transistor M1.

Next, when the drive pulse φ1 goes to the H (high) level, the voltage V1 at the output terminal N1 is boosted by the amplitude thereof (provided that the load capacitance existing at the output terminal N1 is sufficiently smaller than the capacitor C1). .). At this time, the output terminal N
The power supply voltage VDD is lower than the boosted voltage V1 of 1, so that the NMOS transistor M1 is turned off, and the voltage of the output terminal N1 is maintained in a boosted state. Also N
The gate and the drain of the MOS transistor M2 are at the same potential as the boosted voltage V1, and the driving pulse φ2 applied via the capacitor C2 at this time has the opposite phase to the driving pulse φ1 and is therefore at L level. Therefore NMOS
The output terminal N2 of the transistor M2 is connected to the threshold voltage V of the NMOS transistor M2 from the boosted voltage V1 of the output terminal N1.
The potential becomes lower by T2.

Next, when the driving pulse φ2 becomes H level, the voltage V2 of the output terminal N2 of the NMOS transistor M2 becomes
Is boosted by the amplitude (provided that the load capacitance existing at the output terminal N2 is sufficiently smaller than the capacitor C2). At this time, the voltage of the output terminal N1 becomes the level of (VDD-VT1) because the drive pulse φ1 becomes the L level, and the NMOS transistor M2 is reverse-biased and becomes non-conductive, so that the voltage of the output terminal N2 is changed. V2 is held in a boosted state.

The boosted voltage V2 causes N
The MOS transistor M3 becomes conductive, and the voltage V2 is output from the circuit output terminal 3 as the output voltage VOUT through the NMOS transistor M3. However, since the voltage of the NMOS transistor M3 decreases by the threshold voltage, the output voltage VOUT becomes lower than the boosted voltage V2 by the threshold voltage VT3. Thereafter, when the drive pulse φ2 becomes L level, the NMOS transistor M3 is turned off, and the output voltage VOUT is held. As a result, a voltage obtained by boosting the voltage of the power supply 1 to nearly three times is output from the circuit output terminal 3.

[0010]

However, in such a conventional charge pump type booster circuit 102, since the circuit output terminal 3 is connected to the output terminal N2 via the capacitor Co1, the transistor M3 is turned off. Even if
The drive pulse φ2 changes from H level to L level and the output terminal N2
, The voltage at the circuit output terminal 3, that is, the output voltage VOUT slightly decreases. The magnitude of the voltage drop ΔVOUT is

[0011]

ΔVOUT = (Co1 · VCL2) / (Co1 + CL) Here, VCL2 is a voltage change width when the drive pulse φ2 changes from H to L at the output terminal N2, and CL is a load capacitance connected between the circuit output terminal 3 and the ground. That is, the output voltage VOUT is equal to the drive pulse φ2
Is changed from H level to L level, ΔV
A voltage drop occurs at the width of OUT.

Therefore, for example, when the output voltage of the charge pump type booster circuit 102 is used as a power supply in a solid-state imaging device and used as a reset drain voltage of a charge detection unit, for example, the reset drain voltage is synchronized with the drive pulse φ2. Therefore, the offset level of the charge detection voltage also varies, and noise due to the variation of the offset level is mixed in the video signal output from the solid-state imaging device. In particular, in the case of a solid-state imaging device that amplifies and outputs a video signal, this noise becomes even greater.

Although it is possible to increase the load capacitance CL and increase the voltage smoothing ability in order to alleviate such fluctuations in the output voltage of the charge pump type booster circuit 102, the mounting area is significantly increased. In addition, it is difficult to sufficiently suppress the output fluctuation only by increasing the load capacitance CL.

The present invention has been made in order to solve such a problem, and an object of the present invention is to provide a charge pump type booster circuit in which a change in output voltage synchronized with a driving pulse is eliminated.

[0015]

In order to achieve the above object, a charge pump type booster circuit according to the present invention comprises a plurality of first transistors each having a gate and a drain connected to each other so that the drain is on the power supply side. In a charge pump type booster circuit configured to be connected in series between a power supply and an output terminal and to apply a driving pulse of opposite phase alternately to each common connection point of the adjacent first transistors, And a drain connected to the output terminal of the second transistor.
The third transistor is connected to a common connection point of the first transistors, the source of the second transistor is connected to the output terminal, and the driving pulse is applied to each common transistor of the adjacent first transistors. It is characterized in that it is applied to a connection point via a capacitor.

Therefore, the influence of the voltage change of the driving pulse supplied to the drain of the first transistor appears on the voltage of the output terminal through the gate-source overlap capacitance of the first transistor connected to the output terminal. Even so, this effect is due to the gate-
It is canceled by the influence of the voltage change of the opposite-phase drive pulse supplied to the drain of the second transistor, which appears through the overlap capacitance between the sources, and as a result, no voltage fluctuation occurs at the output terminal.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an example of a charge pump type booster circuit according to the present invention. The charge pump booster circuit 16 shown in FIG. 1 differs from the conventional charge pump booster circuit 102 shown in FIG. 3 in that an NMOS transistor M4 is added. As shown in FIG. 1, the transistor M4 has a gate and a drain connected to the output terminal N1 and a source connected to the circuit output terminal 3. Then, similarly to the case where the gate-source overlap capacitance Co1 exists between the gate of the final-stage NMOS transistor M3 and the circuit output terminal 3, the NMOS
Between the gate of the transistor M4 and the circuit output terminal 2, there is also a gate-source overlap capacitance Co4 (surrounded by a dotted frame D in the figure).

Next, the operation of the charge pump type booster circuit 16 configured as described above will be described. FIGS. 2A to 2C are timing waveform diagrams showing the operation of the present embodiment. (A) and (B) show the drive pulses φ1 and φ2, respectively, and (C) shows the boosted voltage at each boosting stage. In FIG. 2C, the solid line represents the power supply voltage, the dotted line 18 represents the boosted voltage V1 at the output terminal N1, and the dashed line 20 represents the boosted voltage V2 at the output terminal N2. The two-dot chain line 24 indicates the output voltage VOUT output from the output terminal 3.

The operation of the parts other than the transistor M4 is the same as that of the conventional one, and the description is omitted here. As shown in FIG. 1, since the gate and the drain of the NMOS transistor M4 are connected to the output terminal N1,
The voltage becomes the voltage V1, while the source of the transistor M4 is connected to the output terminal 3, so that the voltage becomes the output voltage VOUT. Therefore, as can be seen from the waveform diagram of FIG. 2C, the voltage V1 is always the output voltage VOU.
Since the voltage is lower than T, the NMOS transistor M4 is always in a non-conductive state.

The overlap capacitance Co1 between the gate of the NMOS transistor M3 and the circuit output terminal 3
Is connected between the output terminal N2 and the circuit output terminal 3, whereas the overlap capacitance Co4 between the gate of the NMOS transistor M4 and the circuit output terminal 3 is connected between the output terminal N1 and the circuit output terminal 3. Connected between Therefore, the driving pulse φ2 is synchronized with the voltage change of the voltage V2 caused by passing through the capacitor Co1 of the conventional circuit.
The fluctuation of the output voltage is canceled by the fluctuation of the output voltage synchronized with the voltage change of the opposite phase of the voltage V2 (change of the voltage V1) caused by passing through the capacitor Co4 at the same time, and the output voltage VOUT is always constant. Becomes However, it is assumed that the load capacitance existing at the output terminal N1 and the output terminal 2 is sufficiently smaller than the capacitors C1 and C2.

Also in this case, the size of the NMOS transistor M3 and the size of the NMOS transistor M4 are made the same as much as possible so that the overlap capacitance Co1,
Co4 becomes equal to each other, and the canceling effect is further improved.

[0022]

As described above, according to the present invention, a plurality of first transistors each having a gate and a drain connected to each other are connected in series between a power supply and an output terminal with the drain on the power supply side. A charge pump type booster circuit configured to alternately apply opposite-phase drive pulses to respective common connection points of adjacent first transistors, further comprising a second transistor having a gate and a drain connected,
A drain of the second transistor is connected to a common connection point of the second and third first transistors from the output terminal; a source of the second transistor is connected to the output terminal; Is applied to each common connection point between the adjacent first transistors via a capacitor.

Therefore, the effect of the voltage change of the driving pulse supplied to the drain of the first transistor appears on the voltage of the output terminal through the gate-source overlap capacitance of the first transistor connected to the output terminal. Even so, this effect is due to the gate-
It is canceled by the influence of the voltage change of the opposite-phase drive pulse supplied to the drain of the second transistor, which appears through the overlap capacitance between the sources, and as a result, no voltage fluctuation occurs at the output terminal.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an example of a charge pump type booster circuit according to the present invention.

FIGS. 2A to 2C are timing waveform charts showing the operation of the embodiment.

FIG. 3 is a circuit diagram showing an example of a conventional charge pump type booster circuit.

FIGS. 4A to 4C are timing waveform charts showing the operation of the charge pump type booster circuit of FIG. 3;

[Explanation of symbols]

1, 2 ... power supply, 3 ... circuit output terminal, 16 ... charge pump type booster circuit, C1, C2 ... capacitor, CL
... Load capacitance, Co1, Co4. Gate-source overlap capacitance, M1, M2, M3, M4.
Transistor, 102 ... Charge pump type booster circuit.

Claims (5)

(57) [Claims] A plurality of first transistors each having a gate and a drain connected to each other so that a drain is on a power supply side;
A charge pump type booster circuit configured to be connected in series between a power supply and an output terminal, and to apply alternately opposite-phase drive pulses to respective common connection points of the adjacent first transistors. And a drain of the second transistor connected to a common connection point of the second and third first transistors from the output terminal, and a second transistor connected to the second transistor. Source connected to the output terminal
And the driving pulse is applied to the adjacent first transistor.
The charge pump type booster circuit is applied via a capacitor to the common connection point of each other data, characterized in Rukoto. 2. The charge pump type booster circuit according to claim 1, wherein said first and second transistors connected to said output terminal are formed to have substantially the same size. 3. The method according to claim 1, wherein the first and second transistors are N
3. The charge-pump type booster circuit according to claim 1, wherein each of the transistors is a drain type MOS transistor, and a drain of each transistor is connected to a power supply side. 4. The charge pump type booster circuit according to claim 1, wherein the charge pump type booster circuit is incorporated in a solid-state imaging device as a power supply. 5. The three first transistors are connected in series between the power supply and the output terminal, and the driving pulse is a first driving pulse and a second driving pulse having a phase opposite to that of the first driving pulse. Wherein the second drive pulse is applied to a common connection point of the first and second first transistors from the output terminal, and the second and third first pulses from the output terminal. At the common connection point of the transistors
2. The charge pump type booster circuit according to claim 1, wherein said first drive pulse is applied.