JP3037059B2 - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JP3037059B2 JP3037059B2 JP6061049A JP6104994A JP3037059B2 JP 3037059 B2 JP3037059 B2 JP 3037059B2 JP 6061049 A JP6061049 A JP 6061049A JP 6104994 A JP6104994 A JP 6104994A JP 3037059 B2 JP3037059 B2 JP 3037059B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- voltage
- semiconductor integrated
- regulator circuit
- regulator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体集積回路装置に係
り、特にマイクロコンピュータを含むオーディオ機器等
の回路に安定に電源を供給する、リセット機能等の付属
回路を備えたレギュレータ回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a regulator circuit provided with an auxiliary circuit such as a reset function for stably supplying power to circuits such as audio equipment including a microcomputer.
【０００２】[0002]
【従来の技術】従来のリセット機能を備えたレギュレー
タ回路の回路図の一例を図５に示す。係るレギュレータ
回路１の出力ピン１１には、例えばオーディオ機器の制
御回路が接続され、その制御回路にはマイクロコンピュ
ータ１５が含まれている。マイクロコンピュータ１５
は、その電源電圧ＶDDがレギュレータ回路１の出力ピン
１１から供給され、そのリセット端子１６はレギュレー
タ回路１のリセット電圧出力ピン１３に接続されてい
る。マイクロコンピュータ１５は、電源電圧ＶDDが投入
され、一定電圧に達して、そのリセット端子にＶDD以下
のリセット電圧、つまりＶDDからリセット回路の電位降
下分の電圧が下がった電圧が与えられると、マイクロコ
ンピュータ１５はリセットされその制御動作を開始す
る。2. Description of the Related Art FIG. 5 shows an example of a circuit diagram of a conventional regulator circuit having a reset function. An output pin 11 of the regulator circuit 1 is connected to, for example, a control circuit of an audio device, and the control circuit includes a microcomputer 15. Microcomputer 15
The power supply voltage V DD is supplied from the output pin 11 of the regulator circuit 1, and the reset terminal 16 is connected to the reset voltage output pin 13 of the regulator circuit 1. When the power supply voltage V DD is supplied to the microcomputer 15 and reaches a certain voltage, a reset voltage equal to or lower than V DD , that is, a voltage lower than V DD by a potential drop of the reset circuit is applied to the reset terminal. , The microcomputer 15 is reset and starts its control operation.
【０００３】このレギュレータ回路１は脈流状態の入力
電圧ＶINから安定した定電圧ＶOUTを出力するもので、
この半導体集積回路装置のピン１２はパッド１８に接続
され、ＡＣ１００Ｖからトランスを介して全波整流の脈
流状態の電圧ＶINが入力される。入力電圧ＶINはオペア
ンプ２３及びＰＮＰ型の出力トランジスタ２４に電源電
圧を供給する。オペアンプの一方の入力端子（−）に
は、例えば１．２Ｖ程度の基準電圧源ＶREF が接続さ
れ、この電圧がレギュレータ回路１の一定の出力電圧Ｖ
OUT の基準となる。基準電圧ＶREF は、バンドギャップ
回路から構成され、温度特性が良好で電源電圧の依存性
の少ない安定した基準電圧を供給する。オペアンプ２３
の出力はＰＮＰ型の出力トランジスタ２４のベース端子
に入力され、レギュレータ回路１の出力電圧ＶOUT を供
給するとともに、その出力電圧ＶOUTはワイヤ接続２６
からセンスパッド２１を介して抵抗Ｒ1 及びＲ2 により
抵抗分割され、オペアンプの他方の入力端子（＋）に帰
還される。このような帰還回路によりオペアンプ２３の
２本の入力端子（＋）（−）は同一電圧となるように動
作し、レギュレータ回路１の出力電圧ＶOUT は目標の５
乃至１５Ｖ程度の一定の安定化された定電圧となる。The regulator circuit 1 outputs a stable constant voltage V OUT from the pulsating input voltage V IN .
The pin 12 of this semiconductor integrated circuit device is connected to a pad 18, and a pulsating voltage V IN of full-wave rectification is input from AC 100V via a transformer. The input voltage V IN supplies a power supply voltage to the operational amplifier 23 and the PNP type output transistor 24. A reference voltage source V REF of, for example, about 1.2 V is connected to one input terminal (−) of the operational amplifier, and this voltage is a constant output voltage V of the regulator circuit 1.
It becomes the standard of OUT . The reference voltage V REF is composed of a bandgap circuit and supplies a stable reference voltage having good temperature characteristics and little dependence on the power supply voltage. Operational amplifier 23
Is input to the base terminal of a PNP-type output transistor 24 to supply the output voltage V OUT of the regulator circuit 1, and the output voltage V OUT is connected to a wire connection 26.
Is divided by the resistors R 1 and R 2 via the sense pad 21 and is fed back to the other input terminal (+) of the operational amplifier. With such a feedback circuit, the two input terminals (+) and (-) of the operational amplifier 23 operate so as to have the same voltage, and the output voltage V OUT of the regulator circuit 1 becomes the target voltage of 5 V.
It becomes a constant stabilized constant voltage of about 15 V.
【０００４】このレギュレータ回路１に付属したリセッ
ト回路２は、その電源線２５がＰＮＰ型の出力トランジ
スタ２４の出力端子に接続され、飽和電圧分だけＰＮＰ
型出力トランジスタ２４の出力電圧から低減された電圧
がリセットパッド２０を介してマイクロコンピュータ１
５をリセットするリセット電圧として出力ピン１３から
供給される。The reset circuit 2 attached to the regulator circuit 1 has a power supply line 25 connected to the output terminal of a PNP type output transistor 24, and the PNP output transistor 24 has a saturation voltage.
The voltage reduced from the output voltage of the type output transistor 24 is applied to the microcomputer 1 via the reset pad 20.
5 is supplied from the output pin 13 as a reset voltage for resetting 5.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、上述の
ように構成されたリセット機能付レギュレータ回路にお
いては、レギュレータ回路１の出力電圧ＶOUT よりもリ
セット電圧の方が高くなってしまう場合がある。係る場
合には、例えばレギュレータ回路１に接続されたマイク
ロコンピュータ１５においては、電源電圧ＶDDよりもリ
セット電圧が高くなることとなり、ラッチアップ等の問
題が生じるおそれがある。このようなリセット電圧がレ
ギュレータ回路の出力電圧ＶOUT よりも高くなるという
現象は、レギュレータ回路の出力電流が例えば１Ａ程度
の大電流の場合に発生する。ＰＮＰ型出力トランジスタ
２４から出力ピン１１に至る半導体チップ上の金属配
線、その金属配線と金属ワイヤとの接触抵抗、及び金属
ワイヤとピンとの接触抵抗等の合成抵抗による電圧ドロ
ップが大きくなり、上述の逆転現象が生じるものと考え
られる。However, in the regulator circuit with the reset function configured as described above, the reset voltage may be higher than the output voltage V OUT of the regulator circuit 1 in some cases. In such a case, for example, in the microcomputer 15 connected to the regulator circuit 1, the reset voltage becomes higher than the power supply voltage V DD , and a problem such as latch-up may occur. Such a phenomenon that the reset voltage becomes higher than the output voltage V OUT of the regulator circuit occurs when the output current of the regulator circuit is a large current of, for example, about 1A. The voltage drop due to the combined resistance such as the metal wiring on the semiconductor chip from the PNP type output transistor 24 to the output pin 11, the contact resistance between the metal wiring and the metal wire, and the contact resistance between the metal wire and the pin increases. It is considered that a reversal phenomenon occurs.
【０００６】本発明は上述の事情に鑑みて為されたもの
であり、付属回路の出力電圧がレギュレータ回路の出力
電圧よりも高くなる逆転現象を防止することのできる半
導体集積回路装置を提供することを目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides a semiconductor integrated circuit device capable of preventing a reversal phenomenon in which an output voltage of an attached circuit becomes higher than an output voltage of a regulator circuit. With the goal.
【０００７】[0007]
【課題を解決するための手段】本発明の半導体集積回路
装置は、脈流状態の入力電圧から安定化した定電圧を出
力するレギュレータ回路と、該レギュレータ回路から電
源が供給され該レギュレータ回路の出力電圧よりも僅か
に低い電圧を供給する前記レギュレータ回路の付属回路
とを備えた半導体集積回路装置において、前記付属回路
の電源線は、前記半導体集積回路装置のチップ上に新た
に配置したボンディングパッドに接続され、該パッドを
介して前記レギュレータ回路の出力ピンにワイヤ接続さ
れたことを特徴とする。According to the present invention, there is provided a semiconductor integrated circuit device comprising: a regulator circuit for outputting a constant voltage stabilized from an input voltage in a pulsating state; an output of the regulator circuit supplied with power from the regulator circuit; And a power supply line of the auxiliary circuit, the power supply line of the auxiliary circuit being connected to a bonding pad newly arranged on a chip of the semiconductor integrated circuit device. Connected to the output pin of the regulator circuit via the pad.
【０００８】[0008]
【作用】付属回路の電源線は従来のような出力トランジ
スタの出力端子ではなく、出力ピンに直接接続されてい
るので、レギュレータ回路の出力トランジスタと出力ピ
ンの間に生じる抵抗に大電流が流れることによる電圧ド
ロップ分の影響を受けない。従って、付属回路の出力電
圧は、常にレギュレータ回路の出力電圧よりも僅かに低
いものとなる。[Function] Since the power supply line of the accessory circuit is directly connected to the output pin instead of the output terminal of the conventional output transistor, a large current flows through the resistor generated between the output transistor and the output pin of the regulator circuit. Is not affected by the voltage drop. Therefore, the output voltage of the accessory circuit is always slightly lower than the output voltage of the regulator circuit.
【０００９】[0009]
【実施例】以下、本発明の一実施例について添付図面を
参照しながら説明する。なお、各図中同一又は相当部分
には同一の符号を付して重複した説明を省略する。An embodiment of the present invention will be described below with reference to the accompanying drawings. In the drawings, the same or corresponding portions have the same reference characters allotted, and duplicate description will be omitted.
【００１０】図１は、本発明の第１実施例のリセット機
能付レギュレータ回路を示す。本実施例においては、リ
セット回路２の電源線２５は、新たに設けられた半導体
集積回路チップ上のボンディングパッド２２に配線接続
されている。そしてこのボンディングパッド２２は出力
ピン１１にワイヤ接続されている。係る構成により、リ
セット回路２の電源線２５には、出力ピン１１の電圧Ｖ
OUT がそのまま供給される。したがって、リセット回路
２の出力であるリセット電圧ＶRESET は、電源線からト
ランジスタ１段の飽和電圧分だけ低いものとなるので、
常にリセット電圧ＶRESET は出力電圧ＶOUT よりも低い
ものとなる。尚、ワイヤと出力ピンの抵抗成分はチップ
内部の配線抵抗に比べて２桁〜３桁小さく、これによる
電圧ドロップ分は無視できるレベルである。FIG. 1 shows a regulator circuit with a reset function according to a first embodiment of the present invention. In the present embodiment, the power supply line 25 of the reset circuit 2 is connected to the bonding pad 22 on the newly provided semiconductor integrated circuit chip. The bonding pad 22 is connected to the output pin 11 by wire. With such a configuration, the voltage V of the output pin 11 is
OUT is supplied as is. Therefore, the reset voltage V RESET that is the output of the reset circuit 2 is lower than the power supply line by the saturation voltage of one stage of the transistor.
The reset voltage V RESET is always lower than the output voltage V OUT . Note that the resistance components of the wires and the output pins are two to three orders of magnitude smaller than the wiring resistance inside the chip, and the voltage drop due to this is negligible.
【００１１】図２は、本発明の第２実施例のリセット機
能付レギュレータ回路を示す。本実施例においては、リ
セット回路２の電源線２５は、既在の半導体集積回路チ
ップ上のボンディングパッド２１に配線接続されてい
る。そしてこのボンディングパッド２１は出力ピン１１
にワイヤ接続されている。係る構成により、リセット回
路２の電源線２５には、出力ピン１１の電圧ＶOUT がそ
のまま供給される。したがって、リセット回路２の出力
であるリセット電圧ＶRESET は、電源線２５からトラン
ジスタ１段の飽和電圧分だけ低いものとなるので、常に
リセット電圧ＶRE SET は出力電圧ＶOUT よりも低いもの
となる。FIG. 2 shows a regulator circuit with a reset function according to a second embodiment of the present invention. In the present embodiment, the power supply line 25 of the reset circuit 2 is connected to the bonding pad 21 on the existing semiconductor integrated circuit chip. The bonding pad 21 is connected to the output pin 11
Wire. With such a configuration, the voltage V OUT of the output pin 11 is supplied to the power supply line 25 of the reset circuit 2 as it is. Accordingly, the reset voltage V RESET is an output of the reset circuit 2, since the power supply line 25 becomes lower by saturation voltage of the first stage transistor, becomes lower than the output voltage V OUT is always reset voltage V RE SET .
【００１２】本実施例では、リセット回路２の電源線２
５はセンス電圧のパッド２１に配線接続されている。セ
ンス電圧のパッド２１からはレギュレータ回路の出力ピ
ン１１にワイヤ接続されていることは従来の技術におい
て説明した図４の回路と同様である。係る構成により、
上述の第１実施例と同様に、リセット回路２の電源線２
５には出力電圧ＶOUT が与えられるので、１Ａ程度の出
力電流を出力ピン１１から外部に供給しても、ＰＮＰ型
の出力トランジスタ２４の出力端子と出力ピン１１間に
生じる電圧ドロップの影響を受けることなく、リセット
回路の出力電圧ＶRESET は常にレギュレータ回路の出力
電圧ＶOUT よりも低くなる。尚、パッド２１には帰還電
流とリセット回路の電流が流れるが、この電流は両者を
合わせても数十μＡ〜数ｍＡしか流れないので、電位降
下による影響は無視できる。In this embodiment, the power supply line 2 of the reset circuit 2
Numeral 5 is connected to the sense voltage pad 21 by wiring. The connection from the sense voltage pad 21 to the output pin 11 of the regulator circuit by wire is similar to the circuit of FIG. 4 described in the prior art. With such a configuration,
As in the first embodiment, the power supply line 2 of the reset circuit 2
5 is supplied with the output voltage V OUT , the effect of the voltage drop generated between the output terminal of the PNP type output transistor 24 and the output pin 11 even if an output current of about 1 A is supplied from the output pin 11 to the outside. Without being received, the output voltage V RESET of the reset circuit is always lower than the output voltage V OUT of the regulator circuit. The feedback current and the current of the reset circuit flow through the pad 21. Since the current flows only tens of μA to several mA even when both are combined, the influence of the potential drop can be ignored.
【００１３】図３は、本発明の第３実施例の充電電圧検
出機能付きバッテリ充電回路を示す。本実施例は、例え
ば携帯電話の電源であるバッテリ３４をチャージ（充
電）するレギュレータ回路３０と、付属回路であるバッ
テリの充電状態を検出して、出力電圧ＶOUT が一定値を
越えるとＬＥＤランプ３２を点灯させる充電電圧検出回
路３１とから構成される。FIG. 3 shows a battery charging circuit having a charging voltage detecting function according to a third embodiment of the present invention. In this embodiment, for example, a regulator circuit 30 for charging a battery 34 as a power source of a mobile phone, and a charge state of a battery as an accessory circuit are detected, and when an output voltage V OUT exceeds a certain value, an LED lamp is used. And a charging voltage detection circuit 31 for turning on the charging voltage.
【００１４】本実施例においても、充電電圧検出回路３
１の電源線３５は、センス（帰還電圧）パッド２１に接
続され、ワイヤ２６を介して出力ピン１１に接続され、
出力電圧ＶOUT がそのまま供給される。電圧検出回路３
１の電源線３５には、僅かな電流しか流れないので、レ
ギュレータ回路３０の出力トランジスタ２４の出力端子
から大電流が流れ、出力ピン１１との間に合成抵抗分に
よる電圧ドロップが生じても、電圧検出回路の電源線３
５には、常にバッテリ３４の充電電圧ＶOUTが供給さ
れ、正確な電圧検出を行うことができる。Also in this embodiment, the charging voltage detecting circuit 3
One power supply line 35 is connected to the sense (feedback voltage) pad 21 and connected to the output pin 11 via a wire 26.
The output voltage V OUT is supplied as it is. Voltage detection circuit 3
Since only a small current flows through one power supply line 35, a large current flows from the output terminal of the output transistor 24 of the regulator circuit 30, and even if a voltage drop due to the combined resistance occurs between the power supply line 35 and the output pin 11, Power supply line 3 of voltage detection circuit
5, the charging voltage V OUT of the battery 34 is always supplied, and accurate voltage detection can be performed.
【００１５】図４は、本発明の第４実施例の充電電圧検
出機能付きバッテリ充電回路を示す。基本的な回路構成
は図３と同様である。本実施例では、チップ上に新たに
パッド３６を設け、充電電圧検出回路３１の電源線３５
は、チップ上に新たに設けたパッド３６に接続され、ワ
イヤ３７を介して出力ピンに接続され、出力電圧がその
まま供給される。かかる構成により、充電電圧検出回路
３１の電源線３５には、常にバッテリ３４の充電電圧Ｖ
OUT が供給され、正確な電圧検出を行うことができる。FIG. 4 shows a battery charging circuit with a charging voltage detecting function according to a fourth embodiment of the present invention. The basic circuit configuration is the same as in FIG. In this embodiment, a new pad 36 is provided on the chip, and the power supply line 35 of the charging voltage detection circuit 31 is provided.
Is connected to a pad 36 newly provided on the chip, is connected to an output pin via a wire 37, and the output voltage is supplied as it is. With this configuration, the power supply line 35 of the charging voltage detection circuit 31 always has the charging voltage V
OUT is supplied, and accurate voltage detection can be performed.
【００１６】なお、上述の実施例はレギュレータの付属
回路としてリセット回路を備えたものと、バッテリ充電
回路における充電電圧検出回路の例について説明した。
本発明の趣旨は、このような実施例に限定されるもので
なく、広く安定化した定電圧を出力するレギュレータ回
路と、そのレギュレータ回路から電源が供給される付属
回路を備えた半導体集積回路装置に適用可能である。In the above-described embodiment, an example in which a reset circuit is provided as an accessory circuit of a regulator and an example of a charging voltage detection circuit in a battery charging circuit have been described.
The gist of the present invention is not limited to such an embodiment, and a semiconductor integrated circuit device including a regulator circuit that outputs a widely stabilized constant voltage and an accessory circuit to which power is supplied from the regulator circuit Applicable to
【００１７】[0017]
【発明の効果】以上に説明したように、本発明によれば
安定化した定電圧を出力するレギュレータ回路とそのレ
ギュレータ回路から電源が供給される付属回路とを常に
安定に動作させることができ、負荷側の回路にラッチア
ップ等の問題を引き起こす恐れがない。また、バッテリ
充電回路の充電電圧検出回路に本発明を適用すれば、バ
ッテリの充電電圧と検出電圧との差を縮めて、正確な電
圧検出を行うことができる。As described above, according to the present invention, a regulator circuit that outputs a stabilized constant voltage and an auxiliary circuit to which power is supplied from the regulator circuit can always operate stably. There is no possibility of causing a problem such as latch-up in the circuit on the load side. Further, if the present invention is applied to the charging voltage detection circuit of the battery charging circuit, the difference between the charging voltage of the battery and the detection voltage can be reduced, and accurate voltage detection can be performed.
【図１】本発明の第１実施例のリセット機能付レギュレ
ータ回路の回路図。FIG. 1 is a circuit diagram of a regulator circuit with a reset function according to a first embodiment of the present invention.
【図２】本発明の第２実施例のリセット機能付レギュレ
ータ回路の回路図。FIG. 2 is a circuit diagram of a regulator circuit with a reset function according to a second embodiment of the present invention.
【図３】本発明の第３実施例の充電電圧検出回路付バッ
テリ充電回路の回路図。FIG. 3 is a circuit diagram of a battery charging circuit with a charging voltage detection circuit according to a third embodiment of the present invention.
【図４】本発明の第４実施例の充電電圧検出回路付バッ
テリ充電回路の回路図。FIG. 4 is a circuit diagram of a battery charging circuit with a charging voltage detection circuit according to a fourth embodiment of the present invention.
【図５】従来のリセット機能付レギュレータ回路の回路
図。FIG. 5 is a circuit diagram of a conventional regulator circuit with a reset function.
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 27/04 H01L 21/60 301 H01L 21/822 ──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. 7 , DB name) H01L 27/04 H01L 21/60 301 H01L 21/822
Claims (6)
圧を出力するレギュレータ回路と、該レギュレータ回路
から電源が供給され該レギュレータ回路の出力電圧以下
の電圧を供給する前記レギュレータ回路の付属回路とを
備えた半導体集積回路装置において、前記付属回路の電
源線は、前記半導体集積回路装置のチップ上に新たに配
置したボンディングパッドに接続され、該パッドを介し
て前記レギュレータ回路の出力ピンにワイヤ接続された
ことを特徴とする半導体集積回路装置。1. A regulator circuit that outputs a stabilized constant voltage from an input voltage in a pulsating state, and an auxiliary circuit of the regulator circuit that is supplied with power from the regulator circuit and supplies a voltage equal to or lower than an output voltage of the regulator circuit. Wherein the power supply line of the accessory circuit is connected to a bonding pad newly arranged on a chip of the semiconductor integrated circuit device, and a wire is connected to an output pin of the regulator circuit through the pad. A semiconductor integrated circuit device which is connected.
圧を出力するレギュレータ回路と、該レギュレータ回路
から電源が供給され該レギュレータ回路の出力電圧以下
の電圧を供給する前記レギュレータ回路の付属回路とを
備えた半導体集積回路装置において、前記付属回路の電
源線は、前記半導体集積回路装置のチップ上の前記レギ
ュレータ回路の帰還電圧のパッドに接続され、該パッド
を介して前記レギュレータ回路の出力ピンにワイヤ接続
されたことを特徴とする半導体集積回路装置。2. A regulator circuit for outputting a stabilized constant voltage from an input voltage in a pulsating state, and an auxiliary circuit of the regulator circuit supplied with power from the regulator circuit and supplying a voltage equal to or lower than the output voltage of the regulator circuit. A power supply line of the accessory circuit is connected to a feedback voltage pad of the regulator circuit on a chip of the semiconductor integrated circuit device, and an output pin of the regulator circuit is connected via the pad. A semiconductor integrated circuit device, which is connected by wire.
から電源を供給される他の半導体集積回路をリセットす
るリセット電圧を供給するものであることを特徴とする
請求項１又は２記載の半導体集積回路装置。3. The semiconductor integrated circuit according to claim 1, wherein the auxiliary circuit supplies a reset voltage for resetting another semiconductor integrated circuit supplied with power from the regulator circuit. apparatus.
圧を出力してバッテリ充電を行うレギュレータ回路と、
該レギュレータ回路の出力端子の電圧を検出して前記バ
ッテリの充電状態を監視する付属回路とを備えた半導体
集積回路装置において、前記付属回路の検出ラインは、
前記半導体集積回路のチップ上に新たに配置したボンデ
ィングパッドに接続され、該パッドを介して前記レギュ
レータ回路の出力ピンにワイヤ接続されたことを特徴と
する半導体集積回路装置。4. A regulator circuit for outputting a stabilized constant voltage from an input voltage in a pulsating state to charge a battery,
An auxiliary circuit for detecting the voltage of the output terminal of the regulator circuit and monitoring the state of charge of the battery, a detection line of the auxiliary circuit,
A semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is connected to a bonding pad newly disposed on a chip of the semiconductor integrated circuit, and is wire-connected to an output pin of the regulator circuit via the pad.
圧を出力してバッテリ充電を行うレギュレータ回路と、
該レギュレータ回路の出力端子の電圧を検出して前記バ
ッテリの充電状態を監視する付属回路とを備えた半導体
集積回路装置において、前記付属回路の検出ラインは、
前記半導体集積回路のチップ上の前記レギュレータ回路
の帰還電圧のパッドに接続され、該パッドを介して前記
レギュレータ回路の出力ピンにワイヤ接続されたことを
特徴とする半導体集積回路装置。5. A regulator circuit for outputting a stabilized constant voltage from an input voltage in a pulsating state to charge a battery,
An auxiliary circuit for detecting the voltage of the output terminal of the regulator circuit and monitoring the state of charge of the battery, a detection line of the auxiliary circuit,
A semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is connected to a feedback voltage pad of the regulator circuit on a chip of the semiconductor integrated circuit, and is wire-connected to an output pin of the regulator circuit via the pad.
により外部接続した表示素子を駆動するための駆動回路
であることを特徴とする請求項４又は５記載の半導体集
積回路装置。6. The semiconductor integrated circuit device according to claim 4, wherein said auxiliary circuit is a drive circuit for driving a display element connected externally when said battery is fully charged.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6061049A JP3037059B2 (en) | 1994-03-30 | 1994-03-30 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6061049A JP3037059B2 (en) | 1994-03-30 | 1994-03-30 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07273289A JPH07273289A (en) | 1995-10-20 |
| JP3037059B2 true JP3037059B2 (en) | 2000-04-24 |
Family
ID=13159984
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6061049A Expired - Fee Related JP3037059B2 (en) | 1994-03-30 | 1994-03-30 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3037059B2 (en) |
-
1994
- 1994-03-30 JP JP6061049A patent/JP3037059B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07273289A (en) | 1995-10-20 |
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