JP3034515B2 - Array substrate and liquid crystal display device using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention is, in a matrix
Drive the transistors connected to the arranged scanning lines and signal lines.
Operating timing control circuit is formed on the array substrate.
In particular, when applied to liquid crystal display elements ,
Using the array substrate and the same constituted by a thin film transistor having the same structure in the timing control circuit and is on the same substrate
And it relates to a liquid crystal display element.

[0002]

2. Description of the Related Art Generally, a liquid crystal display device has features such as light weight, thinness, and low power consumption as compared with a display device such as a cathode ray tube, and is often used as a display element of a television, a portable information terminal, a graphics display, or the like. ing.

This liquid crystal display device includes a thin film transistor (Thin Film Transistor) that operates as a switching element.
or: an active matrix type liquid crystal display device in which TFTs are arranged. This active matrix type liquid crystal display device has excellent high-speed response and is suitable for high definition, and has been attracting attention as a device that realizes high image quality, large size, and color imaging of a display screen required in the future. .

In recent years, the width of a frame portion (frame) covering the periphery of a liquid crystal panel used for a personal computer, a liquid crystal television, or the like has been reduced. It is also required to be thin, small-sized, and high-definition of a small screen. A drive circuit-integrated liquid crystal display device having a built-in drive circuit has been proposed.

The liquid crystal display device integrated with a driving circuit is characterized in that a signal line driving circuit and a scanning line driving circuit are arranged on the same substrate.

FIG. 5 shows an example of a conventional signal line drive circuit configuration. FIG. 6 shows an example of the driving waveform.

The signal line driving circuit comprises a plurality of shift registers 1a, 1b,... 1n, and a plurality of buffer circuits 2a, 2
2n, a plurality of analog switch groups 3a,... 3n and a plurality of video bus lines 4a, 4b,.

The writing of the video signal to the display area 5 is achieved by charging the voltage charged in the video bus line 4 to the signal line 6 through the analog switch 3.

[0009] A large number of signal lines 6 are connected to the video bus line 4 via an analog switch 3. The analog switches 3 are opened and closed by operating a plurality of switches as a group at the same time (hereinafter, a unit that opens and closes at the same time is referred to as a block). For this reason, the video signal voltage is simultaneously charged to some of the signal lines 6, and the video signal is written to the display area 5. The opening / closing timing is performed by the shift register 1.

The shift register 1 receives a control signal (start pulse) XST and two types of control signals (clock signals) XCK and / XCK having different phases. As shown in FIG. 6, the control signal XST is the control signal X
The shift data is sequentially shifted in synchronization with the falling edge of CK. The shift register output (shift data)
Opens and closes the analog switch 3 as the analog switch control signal a. Note that the video signal application voltage b is applied so as to reach a target voltage level when the analog switch control signal a is closed.

In the above-described liquid crystal display device integrated with a driving circuit, since a driving element such as a TFT is formed on a glass substrate, the characteristics are more likely to vary as compared with an element formed on a silicon semiconductor substrate.

[0012] This variation in characteristics causes circuit delay and waveform rounding, and overlaps with the rise and fall (switch open / close time) of the adjacent analog switch control signal. Due to this overlap, an image is reflected on an adjacent block pixel (hereinafter, referred to as a ghost).

Next, the cause of the ghost will be described.

FIG. 7 shows an analog switch control signal waveform a having no overlapping portion between the waveforms and a video signal applied voltage waveform b.

In this state, since the analog switch control signal of the preceding stage is closed before the analog switch control signal of the next stage is opened, a target voltage can be written in the video signal, and no ghost occurs.

FIG. 8 shows an analog switch control signal waveform a having an overlapping portion between the waveforms, a video signal applied voltage waveform b input to the signal line driving circuit, and the next block before the horizontal cycle. 5 shows a voltage waveform c and a video signal applied voltage waveform d actually written.

As described above, writing to a signal line is performed as follows.
The voltage charged in the video bus line is performed via an analog switch. At this time, if an overlap occurs in the analog switch control signal waveform a, the voltage charged in the signal line c of the next-stage block is applied to the block in which the writing is performed, because the analog switch is opened. Through the video bus line.

As a result, when the analog switch control signal 91 shown in FIG. 8 is closed, the video signal applied voltage has a voltage waveform 92 affected by the next block voltage, and the signal line is charged with the voltage waveform at this time. Therefore, a ghost one horizontal cycle earlier appears in the display area.

If the circuit delay is constant and the overlap of the analog switch control signals is constant, the overlap can be eliminated by adjusting the phases of the control signals XCK and / XCK. However, in practice, variations in TFT characteristics cause variations in circuit delay time and waveform rounding, and variations also occur in overlapping analog switch control signals. In this case, the ghost cannot be eliminated by adjusting the phase of the control signals XCK and / XCK.

As described above, when the analog switch control signal overlaps, ghost occurs, and the display level is significantly deteriorated.

[0021] As a countermeasure to prevent occurrence of ghost like this, for example, in Japanese Laid-5-216441, JP-
A horizontal scanning circuit has been proposed in which the leading end of the next-stage shift pulse is trimmed until the fall timing of the previous-stage shift pulse to eliminate the overlapping portion.

FIG. 9 shows a schematic configuration based on the publication, and FIG. 10 shows signal waveforms in the configuration.

In this configuration, a two-terminal input NOR circuit serving as a fixed pattern removing circuit is added to each output signal end of the shift register S / R.

In this circuit, for example, a shift pulse (shift register output signal) Dn + 1 output from the shift register is converted into a primary pulse signal Bn + by NANDn + 1.
Inverted to 1.

A primary pulse signal Bn + 1 is input to one input terminal of NORn + 1 on the line, and a pulse for operating the switching transistor S output from the preceding delay circuit DLYn is input to the other end. The signal Φn branches and is input.

The NORn + 1 outputs a secondary pulse signal Cn + 1 which is the negative OR of the primary pulse signal Bn + 1 and the pulse signal Φn. The secondary pulse signal Cn + 1 is delayed by a predetermined time t by the delay circuit DLYn + 1, and a pulse signal Φn + 1 is output.

That is, the portion A of the primary pulse signal Bn + 1, which is the overlapping portion of the shift register output signal, is removed until the fall of the secondary pulse signal at the preceding stage, and further delayed by a predetermined time t by the delay circuit DLY.

Therefore, as shown in FIG. 10, the switching transistor Sn and the switching transistor Sn + 1
Pulse signal (analog switch control signal) Φ
By removing the portion A where n and the pulse signal Φn + 1 overlap and delaying by a predetermined time t, the occurrence of ghost is ideally suppressed.

[0029]

However, in practice, the shift pulse Dn, which is the output signal of the shift register, that is, the analog switch is as shown in FIG. 11 with respect to the input start pulse XST.

The shift pulse Dn (solid line) is output as a waveform obtained by differentiating the square wave start pulse XST due to the internal delay of the flip-flop circuit included in the register shown in FIG.

The rising characteristic of the shift pulse Dn mainly depends on the voltage-current characteristic of the pch TFT constituting the clocked inverter inside the flip-flop, while the falling characteristic depends on the voltage-current characteristic of the nch TFT. I have.

In general, the mobility of an nch TFT is higher than the mobility of a pch TFT. Therefore, the absolute amount of variation in characteristics is larger in the nch TFT. Furthermore, nch TFT
When a so-called LDD (Lightly Doped Drain) structure is adopted, the manufacturing process becomes more complicated than that of the pch TFT, and there is a relationship that a circuit element is formed on a glass substrate. Variations in characteristics due to the process increase.

Therefore, the variation in the transient characteristics of the shift pulse Dn is larger at the falling edge n than at the rising edge m. In the conventional technique in which the sampling timing of the analog switch is determined by the fall of the pulse signal φn, the synchronization between the sampling operation of each analog switch and the video signal is caused due to the variation in the characteristics of each flip-flop circuit. And the desired video signal may not be written. As a result, the ghost may not be able to be kept within an allowable level.

Therefore, the present invention prevents the occurrence of ghosts and liquid crystal pixels, and prevents the display level from deteriorating.
An array substrate and a timing control circuit for driving the liquid crystal pixels are formed on the same substrate.
It is an object to provide a liquid crystal display element used .

[0035]

In order to achieve the above object, scanning lines and signal lines arranged in a matrix on a substrate are provided.
Signal line and each intersection of the scanning line and the signal line.
And a transistor connected to the scanning line and the signal line.
A signal line driving circuit for applying a video signal to the signal line;
A timing control circuit formed in the signal line driving circuit;
Wherein the timing control circuits are connected in series with each other.
The shift pulse is sequentially transferred to the next stage, and is shifted in parallel.
Multiple shift registers that output shift register output signals
Synchronized with the rising edge of the next stage shift register output signal
And the overlapping portion with the adjacent shift register output signal
And a plurality of detection circuits for detecting
A plurality of output circuits to which the data output signal is input,
An output circuit outputs the next signal from the shift register output signal.
Eliminates the overlap with the shift register output signal of the stage
An array substrate for outputting a control signal is provided. Further
The scanning lines and signals arranged in a matrix on the substrate
Placed at each intersection with the line, and
And a liquid crystal pixel connected through a
A timing control circuit for performing the timing control.
The circuits are cascaded together to generate shift pulses.
Transfer to the next stage in synchronization with a fixed clock signal, and
Consists of multiple flip-flop circuits that output in columns
A shift register that will be, the flip the adjacent
The output pulse of the flop circuit is input and these output pulses
A duplication detection circuit that generates and outputs the inverted AND signal of
Of the flip-flop circuits adjacent to each other
Output pulse from the flip-flop circuit of
The inverted AND signal is input, and the output pulse and the inverted logic
An output circuit for generating and outputting a logical product signal with the product signal.
Provided is a liquid crystal display element provided. A constructed as described above
The timing circuit formed on the ray board
Detect the overlapping part of the output signal of the
Forcibly switch off the output signal of the shift register
Control is performed. In addition, the liquid crystal display element detects an overlap of output signals of adjacent shift registers by a logic circuit, and forcibly switches on / off an analog switch control signal based on the detected signal, thereby detecting an analog signal of an adjacent block. A time gap is provided between the switch control signals, and the timing is controlled so that the analog switches do not open at the same time, and even if the overlap time of the analog switch control signals varies, the analog switches correspond to the time. Control of the control signal is performed.

[0036]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows an example of a liquid crystal display element according to a first embodiment of an array substrate and a liquid crystal display element using the same according to the present invention, and a signal line driving circuit mounted with a timing control circuit for driving the liquid crystal display element. Is shown and described.

In this embodiment, the technology to which the invention belongs
As described in the previous section, the shift
The transistor, detection circuit and output circuit are
It is composed of Thin film transformer that constitutes the timing circuit
The transistor is, for example, a polycrystalline silicon thin film transistor.
Become. In the present embodiment, a plurality of serially connected (cascaded) shift registers 11 (11a, 11b,.
1n) and the plurality of video bus lines 12 (12a, 12a).
12n), a NAND circuit 13 (13a, 13b,... 13n) for inputting two shift register output signals of adjacent shift registers 11 (for example, shift register 11a and shift register 11b), and the shift register 11 , A buffer circuit 14 (14a, 14b,... 14n) for inputting each shift register output signal of
Adjacent NAND circuits 13 (eg, 13a and 13b)
AND circuit 15 that receives the output of the buffer circuit 14 and the output of the buffer circuit 14 (eg, the buffer circuit 14b)
(15a, 15b,... 15n) and the AND circuit 15
Switch group 16 that opens and closes according to an analog switch control signal (timing control signal) output from
(16a, 16b,..., 16n), a display area 17 in which liquid crystal pixels are arranged in a matrix, and a signal for providing a video signal to each liquid crystal pixel (not shown) in the display area 17 through the analog switch group 16. And a line 18. Including analog switch group 16 and video bus line
The signal line drive circuit is composed of thin film transistors
You. This thin film transistor has the nch
Falling characteristics that depend on the voltage-current characteristics of the transistor
To solve the problem, pch silicon thin film transistor
It is configured by using data. Here, the configuration of the display area is the same as the configuration of FIG. 3 described later, and the liquid crystal display element includes a liquid crystal cell L and a thin film transistor (active element) TFT.
And further includes a vertical scanning unit, which is not shown in FIG. Note that only the AND circuit 15a has no output from the preceding NAND circuit, and one NAND circuit 1
3a and the buffer circuit 14a.

The AND circuit 15 includes a buffer circuit 14
Front and rear ends of the shift register output signals outputted from the respective removed on the basis of the output signals of NAND circuits 13 arranged in the drawing both sides is output as Anal log switch control signal (timing control signal). The trailing end of the shift register output signal is removed when the leading end of the subsequently output shift register output signal rises (turns on).

FIG. 2 shows a driving waveform in the signal line driving circuit shown in FIG. 1 and the operation will be described. In this figure, control signals XST, XCK and / XCK, shift register output signal e, NAND circuit output signal f, AND circuit output signal, ie, analog switch control signal a, and video signal applied voltage waveform b are shown. ing.

This signal line driving circuit includes a control signal XS
Three types of control signals T, XCK and / XCK are input. The control signal XST is sequentially shifted in synchronization with the fall of the control signal XCK. However, the shift register output signal e is delayed later than the fall of the control signal XCK due to a circuit delay or a rounded waveform. A shift pulse delay occurs at the rising edge (arrow A) and falling later than the falling edge of the next control signal XCK (arrow B).

This shift pulse delay is caused by the internal delay of the shift register as described as a conventional problem, and is caused by the characteristic variation of the TFT generated at the time of manufacturing.
The fall time of the shift register output signal e varies more than the rise time.

Therefore, as shown in FIG. 2, the pulse width of the NAND circuit output signal f to which the adjacent shift register output signal e is input reflects the delay amount of the shift pulse (arrows C and D). . However, when there is no overlap between the adjacent shift registers 11, the NAND circuit output signal f has a constant high voltage level.

In this embodiment, each NAND circuit output signal f
Is a signal waveform that reflects the delay and rounding of the shift register 11 at each stage. The H and L levels of the analog switch control signal a are generated using this signal waveform, that is, on / off. To perform the switch (arrow E),
In the AND circuit output signal shown in FIG. 2, that is, the analog switch control signal a, a gap corresponding to the pulse width is formed between the signals, and even if they are adjacent to each other, they do not overlap.

In other words, the sampling timing of each analog switch is determined by using a rising waveform with little variation in transient characteristics, so that variation in the amount of delay with respect to the clock can be suppressed.

Therefore, according to the present invention, the adjacent analog switches 16 do not open simultaneously, and the voltage of the next block charged one horizontal cycle before leaks through the adjacent analog switches 16. Is prevented,
It is possible to appropriately charge the desired video signal application voltage to the signal line, and ghost does not occur in the display area 17.

Next, FIG. 3 shows an example of the configuration of a liquid crystal display device according to a second embodiment of the present invention, which will be described.

The AND circuit 15 of the first embodiment described above
In, for example, three signals, the output of the shift register 11 (the output of the buffer circuit 14b) and the respective outputs of the adjacent NAND circuits 13a and 13b, were input to the AND circuit 15b. For this reason,
As shown in the NAND output signal of FIG. 2, the overlapped portion of the shift register output signal e is removed, so that the first analog switch control signal and the subsequent analog switch control signal are separated by the interval of the overlapped portion. It will be.

However, in practical use, there is no need to leave a space between the analog switch control signals as long as the signals do not overlap with the subsequent analog switch control signals.

Therefore, in the second embodiment, as shown in FIG. 3, the NAND circuits 13 (13a, 13b,.
, The shift register output signals e output from two adjacent shift registers 11 (for example, 11a and 11b) are input, and the two-terminal input AN of the preceding stage is input.
Only the D circuit 19 (for example, 19a) has the NAND circuit 13
The output signal f of a is input.

[0050] Thus, AND circuit 19, buffer 1 4
Is output to the analog switch group 16 based on the logical product of the output signal of the NAND circuit 13 and the output signal of the NAND circuit 13.

The plurality of liquid crystal cells arranged in the display area 17 are arranged, for example, in a matrix, and each liquid crystal display element includes a liquid crystal cell L and a thin film transistor (active element) TF.
And a vertical scanning unit 20.

Thin film transistor constituting signal line drive circuit
And the transistor in the display area are the same on the same substrate
It is formed in a laminated structure. FIG. 4 shows each signal waveform of the signal line driving circuit of the present embodiment.

In this figure, when the shift register output signal e (for example, e1 and e2) has an overlapping portion, the NA of the shift register output signal e2 rises when the shift register output signal e2 rises.
The output signal f of the ND circuit 13 falls. At that time, the analog control signal a1 (the shift register output signal e1 from which the rear end has been removed) falls.

At the same time as the analog control signal a1 falls, the analog control signal a2 (shift register output signal e2) rises.

As described above in detail, according to the present invention, even if successive shift register signals overlap and the amount of overlap varies, the preceding analog switch control signal is activated by the subsequent rise of the analog switch control signal. By forcibly falling the signal, it is possible to remove the overlapping portion.

In the analog switch control signal,
By removing the trailing end, which has a large variation in the falling edge, and performing signal switching based on the rising edge with a small variation, the variation in the delay amount between the trailing edge of the analog switch control signal (shift register output signal) and the clock signal. The switching timing can be adjusted only by matching the phases of the analog switch control signal and the video signal.

[0057]

As described above in detail, according to the present invention, it is possible to prevent the occurrence of a ghost and a display level and to improve the display level by improving the liquid crystal pixel and the timing control for driving the liquid crystal pixel. forming a circuit on the same substrate
An array substrate and a liquid crystal display device using the same can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a schematic configuration example of a signal line driving circuit including a timing control circuit for driving a liquid crystal display element according to a first embodiment of the present invention.

FIG. 2 is a diagram showing waveforms for explaining the operation of the signal line driving circuit shown in FIG. 1;

FIG. 3 is a diagram illustrating a schematic configuration example of a signal line driving circuit equipped with a timing control circuit for driving a liquid crystal display element according to a second embodiment of the present invention.

FIG. 4 is a diagram showing waveforms for explaining the operation of the signal line driving circuit shown in FIG. 3;

FIG. 5 is a diagram showing a schematic configuration of a conventional signal line drive circuit.

FIG. 6 is a diagram showing waveforms for explaining the operation of the conventional signal line driving circuit.

FIG. 7 is a diagram showing an analog switch control signal and a video signal voltage waveform when there is no overlap with a conventional analog switch control signal.

FIG. 8 is a diagram showing an analog switch control signal and a video signal voltage waveform when there is an overlap with a conventional analog switch control signal.

FIG. 9 is a diagram illustrating an example of a configuration of a conventional signal line driving circuit that prevents overlapping of analog switch control signals.

FIG. 10 is a diagram showing waveforms for explaining the operation of the signal line driving circuit shown in FIG. 8;

FIG. 11 is a diagram for explaining variation due to rising and falling in a video signal applied voltage waveform of a shift register.

[Explanation of symbols]

 11, 11a, 11b,... 11n... Shift register 12, 12a, 12b, .about.12n. , 〜15n AND circuit 16, 16a, 16b, １６16n Analog switch group 17 Display area 18 Signal line

Claims (19)

(57) [Claims] A scanning line and a signal line arranged in a matrix on a substrate; a transistor disposed at each intersection of the scanning line and the signal line, and connected to the scanning line and the signal line; A signal line driving circuit for applying a video signal to a signal line; and a timing control circuit formed in the signal line driving circuit, wherein the timing control circuits are connected in series with each other, and sequentially transfer shift pulses to the next stage. A plurality of shift registers that output shift register output signals in parallel, and a plurality of detection circuits that detect overlapping portions of adjacent shift register output signals in synchronization with the rise of the next-stage shift register output signal. And a plurality of output circuits to each of which the shift register output signal is input, wherein the output circuit outputs the next signal from the shift register output signal. The overlapping array substrate and outputs a control signal to remove portions of the shift register output signals. 2. The output circuit to which the next-stage shift register output signal is input outputs a signal obtained by removing the overlapped portion with the previous-stage shift register output signal from the next-stage shift register output signal. The array substrate according to claim 1, wherein: 3. The array substrate according to claim 1, wherein said detection circuit comprises a NAND gate. 4. The array substrate according to claim 1, wherein said output circuit comprises an AND gate. 5. The liquid crystal display device according to claim 1, wherein the shift register, the detection circuit, and the output circuit are constituted by thin film transistors. 6. The thin film transistor comprises a polycrystalline silicon thin film transistor.
An array substrate according to item 1. 7. The array substrate according to claim 5, wherein in the array substrate, the signal lines and the timing control circuit are formed on the same substrate. 8. The array substrate according to claim 1, wherein said signal line drive circuit is formed by a thin film transistor. 9. The liquid crystal display device according to claim 8, wherein the thin film transistor comprises a p-channel silicon thin film transistor. 10. The array substrate according to claim 8, wherein the thin film transistors constituting the signal line driving circuit and the transistors are formed on the same substrate in the same laminated structure. 11. The array substrate according to claim 1, wherein in the signal line drive circuit, an analog switch group is driven in units of a predetermined group of blocks. 12. A scanning line and a signal line arranged in a matrix on a substrate; a scanning line driving circuit for supplying a driving signal to the scanning line; a signal line driving circuit for supplying a video signal to the signal line; A liquid crystal pixel connected to a scanning line and the signal line via a thin film transistor; and a timing control circuit for driving the liquid crystal pixel, wherein the timing control circuits are connected in series with each other, and sequentially transfer shift pulses to the next stage. A plurality of shift registers that output shift register output signals in parallel, and a plurality of detection circuits that detect an overlapping portion between adjacent shift register output signals in synchronization with the rise of the next stage shift register output signal. And a plurality of output circuits to each of which the shift register output signal is input, wherein the output circuit is configured to output the shift register output signal. A liquid crystal display element, wherein a control signal is output from the signal, in which the overlapped portion with the next-stage shift register output signal is removed. 13. The output circuit to which the next-stage shift register output signal is input outputs a signal in which the overlapped portion with the previous-stage shift register output signal has been removed from the next-stage shift register output signal. The liquid crystal display device according to claim 1, wherein: 14. The liquid crystal display device according to claim 12, wherein the liquid crystal pixel, the shift register, the detection circuit, and the output circuit are formed on the same substrate. Liquid crystal display element. 15. An analog switch group formed on the substrate and opened and closed by the control signal sequentially output from the output circuit, the signal line drive circuit being connected to the analog switch group, wherein the video signal 13. A liquid crystal display device according to claim 12, further comprising: a video bus line for transmitting the signal to a plurality of liquid crystal pixels. 16. The liquid crystal display device according to claim 15, wherein the signal line driving circuit is constituted by a thin film transistor. 17. The thin film transistor according to claim 1, wherein the thin film transistor comprises a p-channel silicon thin film transistor.
7. The liquid crystal display device according to 6. 18. A liquid crystal pixel arranged at each intersection of a scanning line and a signal line arranged in a matrix on a substrate, and connected to the signal line via a transistor, and a timing for driving the liquid crystal pixel. And a plurality of flip-flop circuits that are cascaded with each other, sequentially transfer shift pulses to the next stage in synchronization with a predetermined clock signal, and output in parallel. A shift register, an overlap detection circuit that receives output pulses of the flip-flop circuits adjacent to each other, generates and outputs an inverted AND signal of the output pulses, and a flip-flop at a preceding stage among the adjacent flip-flop circuits. An output pulse output from the circuit and the inverted AND signal are input, and the output pulse and the inverted AND The liquid crystal display element characterized by comprising an output circuit for generating and outputting a logical product signal of the items. 19. A liquid crystal pixel arranged at each intersection between a scanning line and a signal line arranged in a matrix on a substrate, and connected to the signal line via a transistor, and a timing for driving the liquid crystal pixel. A shift register configured by a flip-flop circuit that sequentially transfers a shift pulse to a next stage in synchronization with a predetermined clock signal and that outputs a shift register output signal in parallel. A shift register unit connected in series, and two signals of a shift register output signal on the input side and a shift register output signal on the output side are input to each of the shift registers, and an output signal indicating an overlapping portion of the signals is output. , A shift register output signal from a previous stage shift register, and an output signal of the NAND gate unit. Enter a, from the previous stage of the shift registers connected in series in the shift register output signal, when the shift register output signal from the subsequent stage of the shift register is output, the NA
An AND gate unit that generates a timing control signal in which a shift register output signal output from the preceding shift register is turned off based on an output signal from the ND gate unit, and sequentially drives the switch unit. A liquid crystal display device characterized in that: