JP3034385B2 - Tone control information gradual change circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tone control circuit for an electronic musical instrument, such as a synthesizer or an electronic organ, which is used for gradually changing tone control information.

[0002]

2. Description of the Related Art When changing cutoff data, volume data, etc. of a filter of an electronic musical instrument, if the change is suddenly made, there is a problem that an unpleasant sound is generated. Therefore, conventionally, as shown in FIG. Control has been performed in which the control value is gradually changed from a current value to a target value. As an arithmetic circuit for this purpose, a circuit as shown in FIG. 7 has been employed.

This conventional arithmetic circuit comprises a first comparison circuit 101 to which a current value and a target value are inputted, and an exclusive circuit to which a judgment result of the first comparison circuit 101 and a predetermined change width are inputted. Shiv or circuit group (hereinafter referred to as ExOR group)
103, an adder 105 to which the output of the ExOR group 103 and the current value are input, a second comparison circuit 107 to which the output of the adder 105 and the target value are input,
Exclusive NOR circuit (hereinafter referred to as ExN) to which each determination result of the comparison circuit 107 and the first comparison circuit 101 is input.
OR) 109 and a selector 111 that selects and outputs one of the output from the adder 105 and a target value using the output of the ExNOR 109 as a select signal. Note that the determination result of the first comparison circuit 101 is a carry input of the adder 105. Also,
The ExOR group 103 is a group in which ExORs corresponding to the number of bits of the change width are arranged in parallel.

According to this conventional arithmetic circuit, the first comparator 101 outputs "1" when the current value is larger than the target value, and outputs "0" otherwise. . Therefore, if the current value is larger than the target value, the ExOR group 103 outputs “one's complement” in which the signal of each bit of the change width is inverted, and otherwise outputs the change width itself. You.

When the current value is greater than the target value, "1" is a carry input in the comparator 105, so that "1's complement" for the change width is converted to "2's complement". It is added to the current value in the state. That is, the change width is subtracted from the current value. On the other hand, when current value ≦ target value, the change width is added to the current value as it is.

Further, it is determined whether or not the magnitude relationship between the target value and the output of the adder 105 is the same as the magnitude relationship of the comparison result in the first comparison circuit 101 via the second comparison circuit 107 and ExNOR 109. Is done. That is, it is determined whether or not the value after addition / subtraction has exceeded the target value.

If the target value has not been exceeded, the result of the addition / subtraction in the adder 105 is output as a new current value. If the target value has been exceeded, the target value is output as it is. . As a result, the instruction output is changed as shown in FIG. If this conventional arithmetic circuit is used, the present value can be gradually changed toward the target value, and it is preferable that the target value is not excessively increased. However, there are the following problems.

[0008]

According to this conventional arithmetic circuit, a comparison circuit, an adder, a selector and various types of circuit elements must be used, and panpot data, loudness data, and cutoff data of a filter must be used. In an electronic musical instrument having a large number of such arithmetic circuits for changing various data such as pitch bend data, portamento data, etc. in response to a switch operation, etc., there is a problem that the design of each IC becomes complicated.

Accordingly, the present invention has been completed with the aim of facilitating the design of an arithmetic circuit capable of gradually changing such tone control information with a simpler circuit configuration.

[0010]

SUMMARY OF THE INVENTION In order to achieve the above object, a tone control information gradual change circuit of the present invention is provided with a subtraction section for finding a difference between a current value and a target value related to tone control, and the subtraction section. The addition / subtraction unit that adds or subtracts a predetermined change width to or from the difference according to the sign of the difference obtained by the unit, and a subtraction unit that reduces the difference. If the sign is positive, the result of adding the operation result of the addition / subtraction unit to the target value is output. If the sign of the operation result of the addition / subtraction unit does not match the sign of the difference obtained by the subtraction unit, the target value itself is output. And a result output from the adding unit is set as a new current value.

The tone control information gradual change circuit of the present invention first obtains the difference between the current value and the target value (hereinafter, referred to as a first operation), and then reduces this difference by the change width (hereinafter, referred to as a second operation). Then, this reduced difference is added to the target value (hereinafter, referred to as a third calculation), and this is set as a new current value. However, in the case where the sign is reversed in the first operation and the second operation, nothing is added to the target value in the third operation (or “0” is added). In this way, the current value is gradually approached to the target value without overrunning the target value. This operation is expressed by the following equation, where E is the current value, Eo is the target value, and ST is the change width.

[0012]

(Equation 1)

By the way, the tone control information gradual change circuit of the present invention can be realized as the following specific circuit. That is, as described in claim 2, the subtraction unit performs a complement conversion circuit that converts one of a current value and a target value to a complement, a current value or a target value that is complemented by the complement conversion circuit, A first adder to which a target value or a current value that has not been made a complement by a complement conversion circuit is input, and the addition / subtraction unit inputs a difference and a variation width obtained by the subtraction unit, According to the carry output of the first adder,
A second adder for adding or subtracting a change width to or from the difference obtained by the subtraction unit is provided.
The positive / negative judgment is made in accordance with the match / mismatch of the carry output of the second adder, and the output of the second adder is added to the target value only when the positive / negative match is obtained. The tone control information gradual change circuit according to claim 1, characterized in that the circuit is constituted by a third adder.

According to the musical tone control information gradual change circuit of the present invention, the main part of the musical tone control information gradual change circuit of the present invention can be constituted only by an adder. Therefore, it can be further configured as follows.

That is, as described in claim 3, the first
The third adder is constituted by a single adder, and either one of a certain target value or a change width and the complement of the target value or the change width are input to the adder. A first input circuit that can be switched, a second input circuit that can switch and input the operation result or current value of the adder to the adder, and a switching control of the first and second input circuits. By doing so, the complement of the target value and the current value are input to the adder at the first timing, and the calculation result of the adder and the complement or change of the change width at the first timing are input at the second timing. And a time-sharing control means for inputting only the target value and the target value and the operation result of the adder at the second timing or the target value at the third timing. Whether to enter the complement or the variation itself, and the third
Of the adder at the second timing at the timing of
Whether the result is input or not is determined by a carry output at a timing before each timing in the adder, and it can be configured as a tone control information gradual change circuit according to claim 2.

In this case, one adder can perform the functions of the subtraction unit, the addition / subtraction unit and the addition unit according to the first aspect of the present invention by the time division control by the time division control means. it can.

[0017]

Next, an embodiment of a tone control circuit of a synthesizer to which the present invention is applied will be described. As shown in FIG. 1, a synthesizer 1 of the embodiment includes a keyboard 3 and an operation panel 5.
, A tone generator 7 and a speaker 9.
1, a musical tone is generated while controlling the volume, tone quality, tone color and the like by the ROM 13 and the RAM 15. These tone control conditions such as volume, tone quality, and tone are set according to operations of a volume switch, a slide switch, and the like on the operation panel 5.

As shown in FIG. 2, the tone generator 7 has a waveform data generator 21, a digital filter 23 for filtering an output signal of the waveform data generator 21, and an envelope signal for an output of the digital filter 23. Multiplier 25 for multiplying, and D / A converter 27 for D / A converting the multiplication result
And Then, a cutoff frequency indicator 31 for instructing the cutoff frequency is provided to the digital filter 23.
Is connected to the multiplier 25, and an envelope generator 33 is connected to the multiplier 25. The cutoff frequency indicator 31 and the envelope generator 33 gradually change the tone control information from the current value to the new target value in accordance with the operation of the operation panel 5 or the touch detection signal of the keyboard 3 or the like. It is configured as a circuit that changes to

FIG. 2 shows a part of the tone generator 7, which is actually a circuit for balancing left and right speakers based on panpot data and a circuit for controlling volume based on loudness data. Are also configured as circuits for gradually changing the tone control information.

Next, a specific configuration of the cutoff frequency indicator 31 will be described as a typical example of a circuit for gradually changing the tone control information. As shown in FIG. 3, the cut-off frequency indicator 31 receives the current value E relating to the cut-off frequency, sets “1” as a carry input, and sets the positive / negative determination value of the addition result as a carry output. 1 adder 41 and an inverter circuit group 43 for converting the target value Eo into a “1's complement” and inputting it to the first adder 41
And the output ΔE of the first adder 41 is input, the carry output of the first adder 41 is used as the carry input, and the positive / negative judgment value of the addition result is the carry output. And an ExOR group 47 for obtaining an exclusive OR of the carry output of the first adder 41 and the variation width ST, and inputting the result to the second adder 45; An ExNOR 49 for calculating the negation of the exclusive OR between the carry outputs of the adders 41 and 45 of the ExNO
AND circuit (hereinafter referred to as AND) 51 for calculating the logical product of the output of R49 and the output △ e of the second adder 45
And a third value for adding the output of the AND 51 and the target value Eo.
And a circuit for setting the output of the third adder 53 to a new current value E ′.

According to the cutoff frequency indicator 31, in the first adder 41, the current value E is changed to the target value Eo.
"1's complement" and carry input "1" are added.
As a result, the subtraction of △ E = E−Eo is executed. At this time, the circuit is configured such that if the difference ΔE is positive, the carry output of the first adder 41 is “1”, and if the difference ΔE is negative, the circuit is configured to be “0”.

Therefore, if the difference ΔE is positive, the ExOR group 47
Has the same effect as the inverter circuit group, and has a variation width ST
To “one's complement”. At this time, the second adder 4
The carry input of 5 is “1”. As a result, the second adder 45 subtracts △ e = △ E-ST.

On the other hand, if the difference ΔE is negative, the first adder 41
Carry output becomes “0”. Therefore, if the difference ΔE is negative, the ExOR group 47 is the same as “none”,
The change width ST is output as it is. At this time, the carry input of the second adder 45 is “0”. As a result, the second
Adder 45 performs the addition of △ e = △ E + ST.

In this way, the difference ΔE becomes a small value (shrinkage difference) Δe of the absolute value by the change width ST and is input to the AND 51. Similarly to the first adder 41, the second adder 45 outputs a carry output of “1” if the contracted difference Δe is positive, and outputs “0” if the contracted difference Δe is negative. The circuit configuration is as follows. Then, the carry output of the second adder 45 is input to the ExNOR 49 together with the carry output of the first adder 41.

Therefore, based on the respective carry outputs from the first and second adders 41 and 45, the ExNOR 49 outputs “1” if the positive and negative of both operation results △ E and △ e match, Otherwise, "0" is output. As a result, the AND 51 outputs the first and second adders 41 and 45.
If the sign of the calculation results △ E and △ e in match, the contracted difference △ e is output, and if not, “0” is output. Then, the output from the AND 51 is added to the target value Eo by the third adder 53 to become a new current value E ′. This new current value E 'is input again to the first adder 41 as the current value E, and thereafter, the same processing is repeated, and the cutoff frequency is gradually and without excessively changed to the target value Eo. Is done.

In this manner, the cutoff frequency indicator 31 employed in the synthesizer 1 of the embodiment can execute the operation represented by the above-described formula 1 by a combination of only the adders. As a result, it is not necessary to use a comparison circuit and a selector as in the related art.
The design work of the C circuit has also become easier.

Next, a second embodiment will be described. This second embodiment is also a cutoff frequency indicator used in the synthesizer as described above. The cutoff frequency indicator according to the second embodiment is configured as shown in FIG.
The cutoff frequency indicator 61 includes one adder 63,
A current value data memory 65 provided in the RAM 15 for storing a current value E relating to the cutoff frequency control; 1 flip-flop circuit 67,
A second flip-flop circuit 69 for holding the value held by the first flip-flop circuit 67 last time; A register 73 for holding the output of the adder 63; and a first selector 7 for selecting and outputting one of the output of the register 73 and the current value output from the current value data memory 65.
5, the output of the first selector 75 and “1” or “0”
And an AND group 77 for calculating a logical product of the above and a target value Eo and a change width ST, and selecting and outputting any of them.
And the ExOR group 8 for calculating the exclusive OR of the output of the second selector 79 and “1” or “0”
1 to the adder 63. The adder 63 has a circuit configuration for inputting the output of the AND group 77 and the output of the ExOR group 81, and further has first and second selectors 75, 79,
A predetermined timing control circuit (not shown) time-divisionally controls the carry inputs of the AND group 77, the ExOR group 81, and the adder 63. The target value Eo and the change width ST are also stored in the target value data memory 85 and the change width data memory 87 provided in the RAM 15.

This timing control circuit is configured to perform time division control as follows. At a first timing, the first selector 75 is instructed to select the current value E, the second selector 79 is instructed to select the target value Eo, and the AND group 77 and the ExOR group are selected. “1” is input to both the carry input of 81 and the adder 63.

At the next second timing, the first
The selector 75 is instructed to select the output from the register 73, the second selector 79 is instructed to select the change width ST, and “1” is input to the AND group 77. The signal F1 of “1” or “0” held in the first flip-flop circuit 67 is input to both the ExOR group 81 and the carry input of the adder 63.

At the third timing, the first selector 75 is instructed to select the output from the register 73, and the second selector 79 is instructed to select the target value Eo. The ExOR group 81 and the adder 63
"0" is input to both carry inputs, and the AND group 7
7 is "1" output from the exclusive NOR 71.
Alternatively, a signal X of “0” is input. Then, at the last timing (fourth timing), the output from the register 73 is written to the current value data memory 65, and the rewriting of the current value E is instructed.

FIG. 5 shows an algorithm of the operation of the cutoff frequency indicator 61 as the second embodiment. First, the adder 63 calculates the target value E from the current value E.
The difference ΔE is obtained by subtracting o (S10). Then, the difference ΔE is written into the register 73, and the value of the positive / negative judgment bit in the operation of S10 is set as a carry output, and the carry output is held by the first flip-flop circuit 67 as the held value F1 (S20). Here, the positive / negative determination bit is “1” when positive and “0” when negative. The above is the first timing.

Next, the timing control circuit determines whether or not the hold value F1 of the first flip-flop circuit 67 is "1" (S30). If the determination is “YES”, the change width ST is subtracted from the difference ΔE (S4).
0), if “NO”, the difference ΔE is changed by the change width ST
Is added (S50). By executing the processing in S40 or S50, the difference ΔE is reduced by the change width ST.

Then, the operation result Δe of S40 or S50 is written into the register 73, the value F1 held by the first flip-flop circuit 67 is sent to the second flip-flop circuit 69, and the On the other hand, the value of the positive / negative judgment bit in the operation of S40 or S50 is held as the carry output as the hold value F1 (S6
0). The above is the processing content at the second timing.

Next, as a process of the third timing, the timing control circuit determines the value F1 of the first flip-flop circuit 67 and the value of the second flip-flop circuit 69.
It is determined whether or not the stored value F2 matches (S7).
0). If this determination is "YES", the process proceeds to S40.
Alternatively, the reduced difference Δe is added to the target value Eo in S50 (S8
0), if "NO", "0" is added to the target value Eo (S90).

Then, the operation result E 'of S80 or S90 is written into the register 73 (S100). Finally,
When the processing of the first to third timings is completed in this way,
At the last timing, the contents E 'of the register 73 are written to the current value data memory 65 (S110).

As described above, according to the second embodiment, the instruction value of the cutoff frequency can be gradually changed with only one adder 63. Therefore, it has become more convenient both in terms of parts management and IC circuit design work. Although one embodiment of the present invention has been described above, the present invention is not limited to this, and various embodiments can be adopted without departing from the gist of the present invention.

For example, in the embodiment, the case where the present invention is applied to a cutoff frequency indicator has been described. However, various indicators such as a panpot data indicator, a loudness data indicator, a pitch bend data indicator, and a portamento data indicator are used. Of course, it can be applied to the part of. In particular, if the configuration of the present invention is applied to each of these parts,
It is extremely convenient in parts management, standardization of IC design, and the like, and can promptly cope with a need to change the design.

Also in the envelope generator, the envelope curve is approximated as a set of short line segments,
The target value is determined as the first, second,... Corresponding to each line segment.
When the second target value is reached, the second target value is set. When the second target value is reached, the third target value is set, and the target value is sequentially changed. Can be applied. In this case, as shown in FIG. 6, the process is executed substantially in the same manner as the algorithm of FIG. 5, and when the result of step S70 in the middle is NO, after the process of S90, the target value Eo is changed to a new target value Eonext. It may be configured to rewrite (S200).

[0039]

As described above in detail, the tone control information gradual change circuit of the present invention can gradually change the tone control information with a simple circuit configuration, thereby facilitating circuit design. it can. With the circuit configuration described in claim 2, only an adder can be configured as a main part. With the circuit configuration described in claim 3, the tone control information gradual change circuit can be configured with only one adder. Can be designed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a synthesizer of an embodiment.

FIG. 2 is a configuration diagram of the musical sound generator.

FIG. 3 is a circuit configuration diagram of a cutoff frequency indicator as a first embodiment.

FIG. 4 is a circuit configuration diagram of a cutoff frequency indicator as a second embodiment.

FIG. 5 is a flowchart illustrating an algorithm of a calculation process according to the second embodiment.

FIG. 6 is a flowchart illustrating an algorithm of a calculation process when the second embodiment is applied to an envelope generator.

FIG. 7 is a circuit configuration diagram of a conventional tone control information gradual change circuit.

FIG. 8 is an explanatory diagram showing how the output signal of the tone control information gradual change circuit changes.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Synthesizer, 3 ... Keyboard, 5 ... Operation panel, 7 ... Tone generator, 9 ... Speaker, 11
..CPU, 13 ROM, 15 RAM, 2
1 ... waveform data generator, 23 ... digital filter, 25 ... multiplier, 27 ... D / A converter, 31
... Cutoff frequency indicator, 33 ... Envelope generator, 41, 45, 53 ... Adder, 43
... Inverter circuit group, 47 ... Exclusive OR circuit group (ExOR group), 49 ... Exclusive NOR circuit (ExNOR group), 51 ... And circuit (AND), 61 ... Cut-off frequency indicator, 63
... adder, 65 ... current value data memory, 67,
69: flip-flop circuit, 71: exclusive NOR circuit (ExNOR), 73: register, 75, 79 ... selector, 77: AND circuit group (AND group), 81 ... Exclusive OR circuit group (ExOR group), 85: target value data memory, 8
7 ... Change width data memory.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G10H 1/00-1/46

Claims (3)

(57) [Claims] 1. A subtraction unit for calculating a difference between a current value and a target value related to tone control, and a predetermined change width is added or subtracted to the difference according to the sign of the difference obtained by the subtraction unit. An adding / subtracting unit for reducing the difference; and when the sign of the operation result of the adding / subtracting unit coincides with the sign of the difference obtained by the subtracting unit, a result obtained by adding the operation result of the adding / subtracting unit to a target value is output. An adder for outputting a target value itself when the sign of the operation result of the unit does not match the sign of the difference obtained by the subtractor, and a tone control for making the result output from the adder a new current value Information gradual change circuit. 2. A subtraction unit comprising: a complement conversion circuit for converting one of a current value and a target value into a complement; a current value or a target value which is complemented by the complement conversion circuit; and a complement by the complement conversion circuit. A first adder to which a target value or a current value that has not been input is input, and wherein the addition / subtraction unit inputs the difference and the change width obtained by the subtraction unit, A second adder for adding or subtracting a change width to or from the difference obtained by the subtraction unit according to the carry output, wherein the adder includes a carry output of the first and second adders. The positive / negative judgment according to the match / mismatch of
Only when the sign is positive, the second
2. The tone control information gradual change circuit according to claim 1, further comprising a third adder for adding and outputting the outputs of said adders. 3. A method according to claim 1, wherein the first to third adders are constituted by a single adder, and when a certain target value or a change width is input to the adder, the target value or the change width is input. A first input circuit that can be switched between when the complement is input, a second input circuit that can switch and input the operation result or current value of the adder to the adder, By controlling the switching of the second input circuit, the complement of the target value and the current value are input to the adder at a first timing, and the arithmetic operation of the adder at the first timing is performed at a second timing. Time division control means for inputting the result and the complement of the change width or the change width itself, and inputting only the target value and the operation result of the adder at the second timing or the target value at the third timing, Whether to input the complement of the change width at the second timing or the change width itself, and And determining whether or not to input the operation result of the adder at the second timing at the third timing based on a carry output at a timing before each timing in the adder. Item 2. The tone control information gradual change circuit according to item 2.