JP3027757B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION [Summary] Regarding an integrated circuit having a unit block structure, logic elements can be integrated at a high density, the configuration of a power supply system is simple, the degree of freedom of design is large, and it is suitable for automatic design such as CAD A semiconductor integrated circuit including a plurality of logic gates, having a first standard size in a first direction, and including a first hierarchical unit having a polycell structure. One hierarchical unit is
The plurality of logic gates are arranged over a second standard size in a second direction different from the first direction, and each of the first hierarchical units has a second direction in a second direction. A first main side extending over a standard size, a second main side facing the first main side and extending over a second standard size in a second direction, a first direction The first hierarchical unit defined by a first side extending over a first standard size and a second side extending over a first standard size in a first direction. Each includes a first power supply system extending in a second direction over the second standard size, the first power supply system supplying power to a logic gate, At least some of the hierarchical units are arranged in the first direction such that the first and second sides are aligned. And forming a plurality of second layer units each having a length in the first direction, wherein the plurality of second layer units are at least two second layer units of the second layer unit. The semiconductor integrated circuit further extends in the first direction, and intersects the first power supply system in each first hierarchical unit. Wherein the second power supply system is connected to the first power supply system and supplies power in each first hierarchical unit.
It is composed of a semiconductor integrated circuit.

[Industrial applications]

The present invention generally relates to a semiconductor integrated circuit, and more particularly to a large-scale integrated circuit having a unit block structure.

High speed operation is an essential requirement for integrated circuits, especially for integrated circuits used for logical operations. For this reason, a logic integrated circuit usually has a so-called ECL-connected ECL with bipolar transistors.
A circuit or a DCFL circuit using GaAs is used. ECL
Devices require a significant amount of current during high-speed operation, which makes it difficult to supply sufficient power to ECL devices in an integrated circuit as the integration density of the integrated circuit increases. . That is, supplying sufficient power to a logic circuit while maintaining a high integration density becomes a major problem when designing an integrated circuit using such an ECL circuit.

On the other hand, there is an increasing demand for so-called custom integrated circuits for producing various integrated circuits in small quantities according to individual purposes.
Generally, such a custom integrated circuit is constituted by, for example, a so-called gate array structure shown in FIG. Referring to FIG. 18, a number of logic gates having the same configuration and dimensions are formed on semiconductor chip 10 as an array of basic cells 12. The basic cell 12 may be formed as a plurality of columns as shown in FIG. 18th
Such chips or master slices shown in the figure are mass-produced, and only wiring between the basic cells 12 is formed according to individual purposes and functions.

In such an integrated circuit having a gate array structure, all the basic cells on the chip are not usually used, and some basic cells are not used. This is because extra gates are formed in advance on the chip in preparation for applications requiring a very large number of gates. As a result, in a gate array structure, the integration density is generally lower than the maximum integration density that is potentially possible as an integrated circuit, and the operation speed of the integrated circuit cannot be maximized. Occurs. Further, there is a problem that the average length of the wiring pattern on the chip becomes longer in proportion to the chip size. As the wiring length increases, the operating speed naturally decreases. Furthermore, as the integration density increases,
When a large macro cell having a wiring already in a library is arranged, it becomes increasingly difficult to find a path for a new wiring thereon. Further, in the gate array structure, since the chip is provided as a master slice, it is generally difficult to secure a memory and other areas not having the gate array structure on the chip.

On the other hand, as a method of configuring a custom integrated circuit,
A technique called a standard cell method using a polycell shown in the drawing is known. In the standard cell method, a logic element such as an inverter, a NOR gate, or a flip-flop is patterned as a polycell 16a having a constant and standardized height in the Y-direction. The polycell is X
The-direction has various lengths depending on its purpose and function. Further, the polycells are arranged in the X-direction with their top and bottom sides aligned with adjacent polycells, forming a polycell column 16 shown in FIG. A large number of such polycell columns are formed on the chip, and interconnections between the polycells are made within the cell columns, by utilizing spaces or channel regions between the cell columns, or across the cell columns. By using such a polycell structure, the integration density of each polycell can be maximized, and the operation speed can be maximized. In a standard cell integrated circuit, a mask is produced each time an integrated circuit is newly designed, and the design can be optimized. Also, due to this feature, megacell areas M for memories and other logic units can be easily formed.

The polycell structure is currently used in MOS and CMOS integrated circuits. This is because MOS and CMOS devices consume very little power, and especially have almost zero power in the steady state. However, the operation speed is slow. In such an integrated circuit with low power consumption, there is no problem in power supply, and power supply to each polycell can be performed by treating a power supply pattern in the same manner as a signal transmission pattern. .

FIG. 20 shows an example of supplying power in such a CMOS or MOS integrated circuit. In the figure, a power supply conductor 17 connected to a main power supply conductor 18 comprising a terminal pad itself or a conductor connected to the terminal pad is commonly connected to each polycell 16a in a polycell column 16. Is done. In such a configuration, power is supplied to the terminal pads from the outside, and then distributed to each polycell 16a via the conductor 17. As shown, each power supply conductor 17 extends orthogonally to the main power supply conductor 18 and is connected via a power via hole 18a. Since the current flowing through the power supply conductor 17 is very small, the width of the conductor 17 is not particularly limited, and the type and number of logic gates included in the polycell column 16 can be freely selected.

[Problems to be solved by the invention]

When such a polycell structure is applied to a bipolar integrated circuit having bipolar logic gates such as ECL and CML, it becomes difficult to supply sufficient power to each logic gate in the integrated circuit. . This is because bipolar logic gates such as ECL and CML used in integrated circuits consume a large amount of power during high-speed operation. Therefore, in the configuration of FIG. 19, it is necessary to increase the width of the power supply conductor. If the width is insufficient, conductor 17
The current supplied through the cell is limited, so that the number of polycells included in one polycell column must be reduced. This leads to a reduction in integration density. on the other hand,
When the width of the conductor 17 is increased, the required width of the conductor greatly exceeds the width of the polycell column 16 and easily becomes 2-3 times or more. Therefore, conductor 17
When the width of the chip is increased in this manner, a substantial portion of the area on the chip is covered by the conductor, resulting in a decrease in the integration density and the necessity for wiring between the polycell columns. There is a problem that the channel area is reduced.

In order to solve this problem, it is conceivable to use a multilayer power supply wiring structure, but in this case, a via hole required for interlayer connection occupies a considerable area, and the problem of a decrease in channel region is as follows. I can't solve it. as a result,
The degree of freedom of wiring between the polycell columns is substantially lost. Also, fixed orthogonal power supply systems such as those used in gate array structures do not necessarily have the regularly repeated conductor pattern of such power supply systems in an array of polycells having different widths in the polycell columns. Cannot be used because they do not match.

When a megacell region M as shown in FIG. 19 is formed in the integrated circuit, the pattern of the power supply system is
A problem arises in that it must be changed in the vicinity of the area M. That is, when the megacell region M is formed,
A number of power supply conductors 17 must be connected to the main power supply conductor 18 around the area M as shown in FIG.
Therefore, the width of the conductor 18 is inevitably increased. As a result, the area on the chip where the megacell area M can be formed is greatly limited. A similar problem occurs in the main power supply conductor 18 formed around the chip. These problems of changing the power supply system, coupled with the limited area on the chip that can form a megacell area,
Makes it difficult to apply an automatic design process for integrated circuits using

Also, in a typical integrated circuit automatic design process using CAD, when designing a polycell structure, a channel router and a compaction are combined, but in such a case, the formed polycell column extends over the entire length of the entire chip. Because of the extension, the channel region used for wiring also extends along the entire length of the chip along the polycell column. In such a long channel region, the usage rate of the channel region due to the wiring often differs depending on the location even in the same channel, and therefore, the average channel usage rate is often about 30 to 40%. this is,
This means that the total wiring length in the integrated circuit becomes longer and the operating speed is reduced.

The present invention has been made in view of the above points, and can integrate high-speed and high-power logic elements at a high density, has a simple power supply system configuration, has a large degree of freedom in design, and is suitable for automatic design such as CAD. It is an object to provide a high-speed large-scale integrated circuit.

[Means for solving the problem]

The present invention solves the above problem by providing a semiconductor integrated circuit including a plurality of logic gates, having a first standard size in a first direction, and including a first hierarchical unit having a polycell structure, One hierarchical unit has the plurality of logic gates arranged in a second direction different from the first direction over a second standard size, and each of the first hierarchical units has a second direction. A first main side extending over a second standard size, and a second main side facing the first main side and extending over a second standard size in a second direction. And a first side extending in a first direction over a first standard size, and a second side extending in a first direction over a first standard size; Each of the first tier units extends in a second direction over the second standard size. Wherein the first power supply system supplies power to a logic gate, and at least a part of the first hierarchical unit has a first direction and a second level. Sides are arranged so as to be aligned to form a plurality of second layer units each having a length in the first direction, wherein the plurality of second layer units are at least two of the second layer units. Are arranged at different positions in the second direction, further extend in the first direction, and intersect with the first power supply system in each first hierarchy unit. A second power supply system, wherein the second power supply system is connected to the first power supply system in each first hierarchical unit, and supplies power, To achieve.

[Action]

According to the present invention, since the first hierarchical unit has a standardized size, the power consumption is almost constant, and therefore, a large number of first hierarchical units are provided on the chip where and in what arrangement. As described above, it is possible to supply sufficient operating power to each logic gate in each hierarchical unit using a fixed power supply system. Further, since each hierarchical unit has a polycell structure, a high integration density is maintained regardless of the arrangement on the chip.

When the first hierarchical unit is assembled to form the second hierarchical unit, the layout layout of the second hierarchical unit is performed by an automatic design process such as CAD so that the integration density can be freely reduced without sacrificing the integration density. Efficient integrated circuit design becomes possible. In addition, it is possible to freely form a megacell region used for a RAM, a ROM, or an ALU.

When a large number of first hierarchical units are assembled to form a second hierarchical unit, a gap formed between the second hierarchical units is used as a channel for wiring connecting the second hierarchical units. It is possible to use. Such wiring is for wiring between logic gates included between different second hierarchical units, but such wiring is provided outside the second hierarchical unit, and therefore also for the first hierarchical unit. By forming on the outside, the wiring is not connected to the polycell,
It is possible to eliminate a layout that simply passes through, eliminating the need for a channel region for passing such wiring provided in a conventional polycell. As a result, the integration density is further improved.

In the present invention, by forming the first current supply system along the first and second main sides of each first hierarchical unit, sufficient power is supplied to each polycell in each first hierarchical unit. To
This can be done with a fixed second power supply system. For example, by forming the second power supply system as first and second conductors extending in the first direction and regularly repeating in the second direction, all poly cells on the chip are Whether the polycell is included in the isolated first layer unit, or included in the first layer unit which collectively forms the second layer unit, the conductor forming the second power supply system They can always be crossed and connected.

〔Example〕

First, the concept of a unit block forming the basis of the present invention will be described with reference to FIG.

The unit lock 22 shown in FIG. 1 has a constant height H in the Y-direction and is formed by arranging polycells 22a having a height H in the X-direction. Each of the polycells is OR, AND
Logic gates, each having a width W, W 'in the X-direction.
Etc. In each unit block 22, the polycells are arranged such that the length of the unit block in the X-direction becomes a constant standard length L. For example, a typical unit block 22 includes 10-20 polycells and is about 600-800
It has a length L in microns. A typical value for the height H is 78 microns.

Each unit block 22 also has parallel power supply conductor systems 22b and 22c along its upper and lower sides. In other words, in the unit block 22, each polycell 22
a shares the power conductor system 22b, 22c with another polycell, and the polycell is supplied with operating power from the pair of power conductor systems 22b, 22c. As described below, these power conductor systems
Each of 22b and 22c need not consist of a single conductor piece,
It may be composed of a plurality of conductor pieces corresponding to different power supply voltages.

Before describing the arrangement of the unit blocks 22 on the chip, the contents of the polycell 22a will be described.

FIG. 2 shows a polycell 22 forming a unit block 22.
Here is an example of a. In this example, the logic gate is a typical ECL
FIG. 3 is a circuit diagram of a NOR gate having a configuration.

Referring to FIGS. 2 and 3, NOR gate, the transistors Tr1, Tr2 which is supplied with the input signal A1, A2, is supplied with a reference voltage V _BB to the base, the transistors Tr1, Tr2
And another transistor Tr3, combined with to form a current switch.

Referring to the equivalent circuit diagram of FIG.
Tr2 has commonly connected collectors, which are connected via load resistors R1, R2, R3, R4 and R6 to power supply conductor system 22b at ground level. Transistor T
r1 and Tr2 also have commonly connected emitters, which are connected to the emitter of transistor Tr3. On the other hand, transistor Tr3 has load resistances R1, R2, R3,
It has a collector connected to the power supply conductor system 22b via R4. Further, a constant bias voltage V _CS is supplied to the base, the load resistors R7 and R8 are connected to the emitter, and another transistor Tr4 connected to the emitter of the transistors Tr1, Tr2 and Tr3 with the collector shared with the emitter. Provided. Load resistors R7, R8 are connected in parallel, are connected to one conductor pieces 22c ₁ constituting the power supply conductor system 22c, supplies the power supply voltage V _EE to the emitter of the transistor Tr4.

Further, another transistor Tr5 is provided corresponding to the output stage. The base of the transistor Tr5 is the transistor T
connected to the connection node between the collectors of r1 and Tr2 and the resistor R6,
The connector is connected to the power supply conductor system 22b at the ground level,
The emitter is connected to another conductor pieces 22c ₂ constituting the power supply conductor system 22c via a resistor R5.

During operation, when a low-level input signal is input to the input terminals A1 and A2, the transistors Tr1 and Tr2 are turned off while the transistor Tr3 is turned on. In addition, transistor Tr5
Is turned on, a high-level output is obtained from the output terminal. On the other hand, when the input signal to one or both of the input terminals A1 and A2 is at a high level, the transistors Tr3 and Tr5 are both turned off. As a result, a low-level output signal is obtained from the output terminal OUT. Thus, the illustrated circuit operates as a NOR gate.

Next, the actual configuration of the NOR gate shown in FIG. 3 will be described with reference to FIG. 2, elements corresponding to those in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 2, a hatched rectangular portion represents a contact hole.

In FIG. 2, the emitter, base, and collector of the transistor Tr1 are represented by E1, B1, and C1, respectively. Also, the emitter, base and collector of the transistor Tr2 are E2, B2, C2
Expressed by As is clear from the figure, the collectors C1 and C2 are provided in common, and the emitters E1 and E2 are also provided in common. That is, the transistors Tr1 and Tr2 are transistors having a multi-emitter, multi-collector configuration.
On the other hand, the transistors Tr3, Tr4, Tr5 are provided separately, and they are respectively represented by E3-E5, B3-B5, C3-C5. In the figure,
Collector C5 is not shown.

To operate the logic gate at high speed and high power,
R1-R4 are connected in parallel to the power supply conductor system 22b at the ground level GND. In other words, a large current flows through the transistors Tr1, Tr2, Tr3 due to the parallel connection of the resistors R1-R4.
The power supply conductor system 22b is constituted by a single conductor piece, and extends in the unit block 22 in the X-direction as shown in FIG. Similarly, resistors R7, R8 are also connected in parallel to power supply conductor strips 22c ₁ supplies a power supply voltage V _EE. Furthermore, to configure the power supply conductor system 22c with the power supply conductor strips 22c _1, the power supply conductor strips 22c ₂ for supplying a power supply voltage V _T is the emitter of the transistor Tr5, is connected via a resistor R5.

By configuring the logic gate in this manner, the power of the gate, and thus the operating speed, can be increased by simply increasing the size of the gate in the X-direction. FIG. 4 shows such a logic gate having a pattern extended in the X-direction. The logic gate of FIG. 4 has the same structure as the logic gate of FIG. 2 and therefore comprises the same components.

By configuring the logic gate in this way, the power consumption of the logic gate is proportional to its X-direction dimension. In other words, when the polycell is configured in this manner, the power consumption or power density per unit area is substantially constant regardless of the size of the polycell. Also, in a unit block in which a large number of polycells configured as described above are arranged in the X-direction, the power consumption per unit area is kept constant, and the sizes in the X and Y directions are standardized. The power consumption of the unit block is substantially constant.

FIG. 5 shows another polycell structure having a polycell 22a 'forming a latch circuit. Also in this polycell structure, current flows in the substantially Y-direction between the power supply conductor systems 22b and 22c, and the terminals of the various transistors Tr extend in the X-direction.
Therefore, also in this case, by increasing the size of the transistor in the X-direction, the power consumption of the polycell can be increased while the power consumption per unit area is kept constant. Figure 2, extends in the X- direction at a predetermined position of the fourth diagram of poly cell 22a or bias voltage V _CS in poly cell 22a 'of FIG. 5, the conductor 22d supplies the V _BB,, 22e is Y- direction This makes it possible to systematically supply various bias voltages to the polycells in the unit block. The wiring of the logic circuit is completed in each polycell by, for example, a conductor 22f extending in the X-direction.
The size L of the unit block 22 is determined in consideration of the power required by the unit block, the loss at the time of setting a polycell in the unit block, the ease of applying an automatic design method such as CAD, and the like. The power consumption increases as the size L of the unit block 22 increases.
Therefore, if the value of L is too large, it is necessary to use a power supply conductor piece having a very large width as the power supply conductor system 22b, 22c.
Will increase. Such an increase in the height of the unit block causes a decrease in the integration density. On the other hand, if the length L of the unit block 22 is too small, the rate of polycell loss in the unit block increases. For example, when the length L of the unit block is
When the number of tertiles is reduced to three, the proportion of the loss area that occurs when the area of the unit block 22 is not completely filled with polycells increases. Such a ratio of the loss area reaches at most one polycell. However, there is no further increase. Length L of unit block 22
Is small, the ratio of the loss area to the area of the unit block becomes large. For example, if the length L is about twice as long as the average polycell length in the X-direction, a loss of up to 50% occurs in the worst case. In this embodiment, the length L of the unit block 22 is preferably about 600 microns, corresponding to an average of 10-20 polycells. Therefore, the loss in this case is about 5-10%.

Next, a first embodiment of the integrated circuit according to the present invention will be described with reference to FIG. In FIG. 6, a chip area 21 is formed on a semiconductor chip 20, and an input / output area 21a including an input / output buffer circuit and a terminal pad is provided so as to surround the chip area 22. In the chip area, a large number of unit blocks 22 are collected.
A large number of unit block aggregates or mini macro blocks 23 are formed. In each mini-macro block 23,
The unit blocks 22 are arranged in the Y-direction. In other words, in the mini macro block, the short pieces of each unit block extending in the Y-direction are aligned in a straight line in the Y-direction. The number of unit blocks included in each mini-macroblock, and therefore the size of each mini-macroblock in the Y-direction, differs for each mini-macroblock. On the other hand, the size of the mini-macroblock in the X-direction is an integral multiple of the length L of each unit block 22 in the X-direction. Furthermore, on the chip area 21, RAM or R
A megacell region 24 for a functional block such as OM or ALU is formed. The mini-macro block 23 may be divided into a plurality of mini-macro blocks as needed, for example, when a channel for wiring is desired.

When the mini-macro blocks 23 are arranged on the chip 20, a number of channel regions 25 are formed between adjacent mini-macro blocks. In the embodiment shown in FIG. 6, the mini-macro block 23 has a chip 20 except that its orientation is regulated so that the extending direction of the unit block included in the mini-macro block always becomes the X-direction. Freely placed on top. Some of the mini-macroblocks may be isolated, for example, as in the mini-macroblock 23a, and may be arranged collectively in the X-direction as in the mini-macroblocks 23b, 23c, or 23d, 23e. You may. Further, as shown in the mini macroblocks 23d and 23e, adjacent macroblocks do not necessarily have to have the same size.

The mini-macro blocks 23 are further assembled together and completed wiring is performed to form a macro block 100 that acts as a complete functional block such as an ALU on a chip. The mini-macroblock itself does not normally form such a complete functional block. The macro block 100 constitutes an intermediate layer in designing a hierarchical layout of an integrated circuit.

An important feature of the present invention is that multiple mini-macroblocks 23
Are arranged in the X-direction with or without the channel region 25 therebetween, so that two or more mini-macro blocks are located on the chip region 21.
They are arranged at different positions in the X-direction. On the other hand, the position of the mini-macro block in the Y-direction can be freely selected. The mini-macro blocks need not necessarily be arranged so that the top and bottom sides of the included unit blocks 22 are aligned with adjacent mini-macro blocks. For example, even if the mini-blocks are shifted as indicated by L 'and L ", Good.

In each of the unit blocks 22, the wiring between the polycells is completed except for the terminals used for connection with the polycells in other unit blocks. In each mini-macro block 23, the interconnection between the unit blocks is completed except for terminals for connection to other unit blocks included in other mini-macro blocks.
As described above, the interconnect speed that affects the operation speed of the logic gate is confined within each mini-macro block 23 and each unit block 22, that is, within the macro block 100, thereby maximizing the operation speed of the integrated circuit. It becomes possible to do. On the other hand, other wirings connecting different unit blocks 22 belonging to different macroblocks 100 are made using gaps 25 formed between mini-macroblocks 23 and called channel regions or global channels.

In the global channel 25, no terminal or other structure that interferes with the interconnection wiring is provided, so that wiring connecting different macroblocks can be efficiently performed. In addition, such global channels
Since the wiring passing through 25 does not pass through another polycell on the way, it was conventionally provided in the polycell,
A region only for passing such wiring is unnecessary,
The integration density of integrated circuits is further improved.

FIG. 7A shows an example of a wiring pattern used in the integrated circuit of the present invention. Integrated circuit is a mini macro block
23, thus a large number of unit blocks 22 ₁ constituting the macro block 100 consists of 22 _2, 22 _3, etc., the global channel 25 is formed between the mini-macroblock 23. In each polycell 22a forming the unit block 22, the wiring inside the polycell is completed by a first-level conductor pattern (not shown), and a terminal region T for connection to another polycell is formed. Furthermore, the terminal region T in the unit block 22 _1, 22 _2, 22 ₃ in poly cell 22a, the power conductor system 22a, the level 22b is formed of, or above the second level, the wiring provided in the third level Are connected to each other by the conductor pattern 22x. The conductor pattern 22x is used for wiring that affects the operation speed of the integrated circuit. On the other hand, in the global channel 25, another wiring conductor pattern 25x for connecting the poly cells 22a belonging to different mini-macro blocks is provided at the first or second level. This wiring pattern 25x is used for wiring that does not affect the operation speed of the integrated circuit. In other words, unit block 22
When designing the _1, 22 _2, 22 ₃ of the sequence, the logic circuit so as to affect the operating speed of the integrated circuits in each macroblock are arranged close to each other.

By configuring the unit block and the macro block in this manner, the present invention achieves high-speed operation of the integrated circuit and free layout at the same time.

On the other hand, FIG. 7B shows a conventional CMOS or MO.
A wiring example of an S integrated circuit having a polycell structure is shown. In this case, the polycell forms a polycell column 16 as described in FIG. 2, and the wiring of the integrated circuit is a wiring pattern 22 for wiring between relatively closely arranged polycells.
x and wiring pattern 2 for wiring between poly cells that are relatively far apart
Made with 5x. In order to pass through the wiring pattern 22x, the feedthrough channel CH is provided in the polycell column 16.
Is formed, which takes up a considerable area of the polycell. It should be noted that FIGS. 7 (a) and 7 (b) are shown on the same scale. This means that the integration density of each polycell is unnecessarily reduced only for passing the wiring pattern 25x, and the operation speed of the integrated circuit is necessarily reduced. Further, since the length of the wiring pattern 22x increases due to the presence of the feedthrough channel CH, a reduction in speed due to this is inevitable.

In the present invention, since both the unit block 22 and the mini-macro block 23 have the standardized size L in the X-direction or a size of an integer multiple thereof, the macro block 10
It becomes easy to design and layout 0 by CAD. In other words, by designing the integrated circuit using the concept of the unit block 22 and the macro block 100 disclosed in the present invention, automatic design (DA) of the integrated circuit is facilitated. Since the layout of the mini-macro block 23 is substantially free, a megacell structure such as a RAM, a ROM, or an ALU can be freely formed at a desired position on the chip area 21. Further, in the integrated circuit according to the present invention designed based on the unit block 22 and the mini macro block 23, a fixed power supply system is used because the power density per unit area on the chip 20 is kept almost constant. It becomes possible.

FIG. 8 shows a second embodiment of the present invention. In the present embodiment, a fixed width is set over the entire chip area 21 corresponding to an arbitrary pair of mini-macro blocks 23 adjacent in the X-direction.
A global channel 25 having a W _CH is formed linearly along the Y-direction. In other words, in this embodiment, a large number of mini-macroblock 23, to form a plurality of mini-macroblock column 23 _1, 23 _2, 23 ₃ extending to each Y- direction,
Each mini-macroblock column is separated by a distance equal to the constant width W _CH in the X- direction. On the chip 20, there may also be an isolated unit block 22. By making the layout of the mini-macroblock columns in the X-direction regular in this manner, power can be supplied by a fixed power supply system having a corresponding regularity. Such a fixed power supply system is very suitable for supplying high power. Hereinafter, power supply to the integrated circuit will be described.

FIG. 9 (a) shows a book in which a number of parallel, linear global channels 25 are repeated in the X-direction at intervals or pitches corresponding to the unit block length L, as shown in FIG. An example of a power supply system applied to the second embodiment of the invention is shown. In Figure 9 (a), the global channel 25 _1, 25 _2, 25 _3, power bus 30 _1, 30 ₂ with respect ...,
30 ₃ , ... are provided, and these power buses are common to the corresponding power supply conductor systems 22 b, 22 c of the unit block 22 included in each mini macro block column 23 ₁ , 23 ₂ , 23 ₃ , ... Connected to. Here, the power supply conductor systems 22b and 22c are shown in FIG. 9 (b).
As shown in the figure, a power bus is provided at a second level above the first level at which wirings completed in the unit block 22 are provided, and a power bus is further provided above the power supply conductor systems 22b and 22c. There are three levels. Power bus 30 ₁ , 30
₂ while being connected power supply conductor system 20b BU 22 and 20c respectively, power bus 30 _2, 30 ₃ 'power conductor system 22b' of the adjacent unit blocks 22 which are respectively connected to 22c '.

Furthermore, the power bus 30 ₁ -30 _3, the fourth level X-
Main power bus 31 provided to extend alternately in the direction
_1, 31 ₂ are connected by the via holes formed at the intersection of the power bus 30 ₁ -30 ₃ and the main power bus 30 _1, 30 _2, the power supply voltage V _EE, is supplied with V _CC. The first, second, third and fourth level conductors are separated by an insulating layer not shown.

In particular, the fourth level conductor, as shown in FIG.
By being configured to extend contiguously and alternately with a small gap therebetween, the fourth level of the chip is substantially covered by the main power bus, creating a very powerful power supply system Is done. Any unit block 22 on the chip 20, no matter where it is on the chip, has a suitable power bus 30
₁ , 30 ₂ , 30 ₃ ,..., Thus ensuring a sufficient power supply. In the illustrated example, the power supply voltage is two kinds of V _EE and V _CC , but the power supply system of the present invention uses three or more power supply voltages by increasing the number of power buses or conductors at each level. Can be easily adapted.

In addition, by providing the power bus at the third level, the first level of the global channel 25 can freely use the wiring of the polycells between different mini-macro blocks, and can freely design the integrated circuit. More often. Wiring between different unit blocks in the same mini-macro block is performed by providing a wiring conductor extending in the Y-direction at the third level.

Next, power supply when the layout of mini-macro blocks is more general will be described with reference to FIG. In the layout in this case, the mini-macro blocks 23 and 23 'adjacent in the Y-direction have offset positions in the X-direction. Therefore, in this case, the global channels on both sides of the mini-macro block 23 or 23 'do not extend linearly over the entire surface of the chip.

In such a case, the power bus is formed by power buses 30 ₁ and 30 ₂ provided for each of the channel regions 25 between the pair of mini-macro blocks 23 and 23 ′ shown in FIG.
Power supply to these power bus is similarly made from the main power bus 31 _1, 31 ₂ and Figure 9. From a fixed power supply system with a fixed layout of the main power bus, in any mini-macroblock on the chip area 21, in order to reliably supply power, the main power bus 31 _1, 31 repetition pitch P ₁ of _2, the chip area 21 is smaller than the minimum height H ₂₃ of the macro blocks present above. Here, the pitch P ₁ is the main power bus 31
It is equal to the sum of the widths of the conductor pieces constituting a and 31b. By setting the pitch of the main power bus in this manner, even if the layout of the power supply system is fixed, and regardless of the arrangement of the mini macro block 23 on the chip area 21, the unit block in the mini macro block Power can be reliably supplied to the macro block 100
It can be done freely using AD. At this time, detailed design such as routing of the wiring conductor can be easily performed.

FIG. 11 shows another example of a power supply system. Also in this example, the mini-macro blocks 23 are freely arranged on the chip area 21 as in the case of FIG. 8, and the main power bus is formed in the Y-direction. However, in this example, the power buses 30 ₁ and 30 ₂
Are omitted, and the main power buses 31 ₁ and 31 ₂ are connected to the unit block 2
It is directly connected to the two power supply conductor systems 22b and 22c. The main power bus 31 _1, 31 ₂ formed in contact with the phase across the chip area 21, also the repetition pitch P ₂ to the time the X- direction, set substantially smaller than the length L of the BU 22 it allows any unit blocks in mini macroblock 23 can be formed so as to intersect with the macro block where the long, either the main power bus 31 _1, 31 _2, therefore, which unit block on the chip area 21, And any of the polycells in it, the via hole shown "POWE
Power can be reliably supplied via RVIA.

FIG. 12 shows a third embodiment of the integrated circuit according to the present invention, in which different types of unit blocks 22 ₁ , 22 ₂ having different standard heights H22b are assembled on the chip area 21 and various types are shown. The mini-macro blocks 23, 23 ', and 23 "are formed. Alternatively, the mini-macro blocks may be formed of isolated unit blocks. For simplicity, the power supply conductor systems 22b and 22c of each unit block are shown in the figure. This configuration is advantageous when different types and different types of polycells must be used on the same chip.

In this embodiment, the polycells are classified according to their height H into those having a height H22a, those having a height H22b, etc., and are assembled according to height to form various unit blocks. In other words, in this embodiment, there are a plurality of types of unit blocks having different heights.
However, the length of the unit block in the X-direction is common,
L. The unit blocks are assembled to form mini-macro blocks 23, 23 ', etc., and by laying out the mini-macro blocks, the semiconductor integrated circuit can be freely designed by CAD. Also in this case, the power or power density supplied to the unit area of the chip is constant. This means that the power supply system described in FIGS. 10 and 11 can be used.

FIG. 13 shows a fourth embodiment of the integrated circuit of the present invention. No.
As in the case of Fig. 12, the power supply conductor system of each unit block
Illustration of 22b and 22c is omitted. In the present embodiment, the degree of freedom regarding the size of the unit block is further expanded, and X-
The length L of the unit blocks in the direction is optimized for each unit block. In other words, a plurality of unit blocks having different lengths L are present on the same chip. As in the case of FIG. 12, in the same unit block, the polycells have the same height H, but this height H differs between unit blocks. Furthermore, unit blocks having the same length, for example, unit blocks 22 ₁ , 22 ₂ , 22 ₃ , or unit block 2
2 ₁ ′, 22 ₂ ′, 22 ₃ ′ or unit block 22 ₁ ″, 22
₂ ", 22 _3" is allowed to set, X- direction length different mini-macroblocks 23, 23 ', in. Mini macroblock 23 23 "is formed, the unit blocks 22 _1, 22
_2, 22 ₃ have the same length L _23, mini-macroblock 23 '
, The unit blocks 22 ₁ ′, 22 ₂ ′, 22 ₃ ′ have the same length L ₂₃ a, and in the mini macro block 23 ″, the unit blocks 22 ₁ ″, 22 ₂ ″, 22 ₃ ″ are the same. Length L ₂₃ b
Having. Also, the Y of the mini macro blocks 23, 23 ', 23 "
The lengths H ₂₃ , H ₂₃ a and H ₂₃ b in the − direction need not be the same. In the illustrated example, although the height H ₂₃ a mini macroblock unit height H ₂₃ a and mini macroblock units 23 23 'is the same, the height H ₂₃ b mini macroblock 23 "is different Fig. 13 shows a power supply system applied to this embodiment, which is also applicable to the embodiment of Fig. 12. The power supply system is substantially the same as that of Fig. 10. to the same, the main power bus 31 ₁ of double-, 31 ₂ are provided in parallel in the X- direction. in this power supply system, the repetition pitch P ₃ of the power bus 31 _1, 31 _2, satisfying the following relationship Is set to

P ₃ <H ₂₃ a P ₃ <H ₂₃ b In other words, the pitch P ₃ is set smaller than the minimum height of the mini-macro block on the chip. By setting the pitch in this way, in any of the mini-macroblock from the main power bus 31 _1, 31 _2, ensures it is possible to supply electric power. FIG. 14 shows a fifth embodiment of the present invention. In this embodiment, unit blocks having different sizes in the X-direction are freely assembled to form mini-macro blocks. In this case, the sides of the mini-macro block in the Y-direction are not always aligned. Even in such a case, the power buses 30 ₁ and 30 ₂ are adjusted so that the repetition pitch P _{4 in the} Y-direction is smaller than the minimum length L in the X-direction of the unit block included in the mini-macro block. By forming, a fixed power supply system can be used. That is, the pitch P ₄ is selected to satisfy the following relation.

P ₄ <L ₂₃ c P ₄ <L ₂₃ d P ₄ <L ₂₃ e P ₄ <L _min where L ₂₃ c, L ₂₃ d, L ₂₃ e is the X of each mini macroblock
L _min represents the minimum size of the mini macroblock in the X-direction.

FIGS. 15 and 16 show an example of supplying power to the megacell 24 shown in FIG. Referring to FIG. 15, the power bus
30 ₁ and 30 ₂ are provided on both sides of the mini-macro block 23 corresponding to the global channel 25 as in the previous embodiment, and power is supplied in the same manner as in FIGS. 9 (a), 10 and 13. Similarly, it is done by providing the main power bus 31 _1, 31 ₂ in the X- direction. As described above, megacell 24 has RA
Elements such as M, ROM, and ALU are formed.

For supplying power to each element in the megacell 24, the power supply conductor 24a is formed on megacell 24, 24b is formed in the Y- direction, the power is the main power bus 31 _1, 31 ₂ from the power supply conductor 24a, to 24b, the main power bus 31 _1, 31 ₂ and the power supply conductor 24a, is supplied through a via hole formed at the intersection of 24b. Repeating pitch P of that time, the power bus 31 _1, 31 ₂ of the Y- direction
5 the power conductors 24a, by setting the following length LV to 24b of Y- direction and megacell 24 will be formed anywhere on the chip, the power bus 31 _1, 31 ₂ from the power supply conductor 24a, and 24b Electric power can be supplied reliably.

FIG. 16, the power to megacell 24, Y- from the power bus 31 _1, 31 ₂ extending in a direction, the power supply conductor extends in the X- direction 2
The case of supplying via 4a, 24b is shown. Power conductors 24a, 24b
Roh X- in the direction of the length LH, by setting the repetition pitch P ₆ or more to the power bus 31 _1, 31 ₂ in the X- direction, the power to megacell 24, megacell 24 matter where on the chip Can be reliably supplied.

Next, a flowchart showing a layout process applied to the semiconductor integrated circuit according to the present invention will be described with reference to FIG.

In step 1 of FIG. 17, a schematic circuit diagram of a logic circuit to be formed on the chip 20 is provided, and a logic simulation and a timing simulation are performed in the following step 2. Further, in step 3, connection information of the logic circuit is extracted in the form of hierarchized logical netlist data, and in step 4, the information is expanded hierarchically. In step 5, parameters such as a critical path and the type and number of functional blocks formed on the chip are formed. Steps 1-3 are the same as those used in the conventional semiconductor integrated circuit design. On the other hand, steps 4 and 5
An intermediate step for matching with the subsequent layout process is formed. Next, in step 6, the layout of the macroblock at the hierarchical level is started.

In step 6, the size and configuration of the macroblock 100 are estimated using the boundary data registered in the library. In step 7, the initial placement of megacells 24 and macroblocks 100 is determined, and step 8
, The necessary global channel 25 is estimated. In step 9, an estimation is made of the global feedthrough channel that needs to be formed in the macroblock.
Further, in step 10, the delay of the signal transferred via the global channel 25 and the drivability of various logic gates are evaluated, and the initial arrangement of the macroblock is appropriately changed in step 12 according to the result of step 10. .

Then, the process of Step 2 to Step 10 is executed again, and is repeated until the drivability of the logic circuit is confirmed.

In parallel with steps 8 and 9, in step 11 the distribution of the amount of supply current and the generated voltage drop is evaluated, and based on the result, the arrangement is changed in step 12 and step 8-11 is performed.
Is repeated.

Further, in step 14, the unit block 23 is arranged in the macro block 100 and the macro block 1
A field-through path is set in 00, and input / output cells are formed in the macro block 100 in step 15. Further, the cell arrangement in the macro block 100 is executed in step 16. In each step between step 14 and step 17, a semiconductor pattern registered in the cell library is used. Steps 14 to 17 are macro blocks
The layout within 100 is shown.

Subsequent to the step 17, the steps from the step 7 to the step 11 are repeated using the macroblock designed in this way until the layout is completed for all the macroblocks 100.

After the layout has been completed for all macroblocks 100, global routing using the global channel 25 and the global field-through channel generated in step 9 is performed in step 19,
In step 21, mask data is generated. In step 20, a voltage drop compensation pattern may be generated. Subsequent to step 21, the actual wafer manufacturing process is started.

Further, the present invention is not limited to the following embodiments, but includes various modifications.

〔The invention's effect〕

As described above, according to the semiconductor integrated circuit of the present invention, a high-speed, high-power bipolar logic element can be integrated on an integrated circuit chip at a high density by a unit block structure, and a large-capacity fixed power supply system can be used. By forming macroblocks using unit blocks, layout by automatic design means such as CAD can be easily and effectively applied.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining the concept of a unit block used in the present invention. FIG. 2 is a diagram showing an example of a NOR gate having a polycell structure constituting the unit block of FIG. FIG. 4 is an equivalent circuit diagram corresponding to the semiconductor pattern of FIG. 2, FIG. 4 is substantially the same as that of FIG. 2, but shows an example of a NOR gate with increased power, FIG. FIG. 6 is a diagram showing an example of a latch circuit constituting a unit block. FIG. 6 is a diagram showing an integrated circuit layout pattern according to a first embodiment of the integrated circuit of the present invention. FIG. 7 (a) is FIG. FIG. 7 (b) is a plan view showing a wiring pattern used in an integrated circuit having a conventional polycell structure, and FIG. 8 is a plan view showing a wiring pattern used in an integrated circuit of the present invention. The layout pattern of the integrated circuit according to the second embodiment is 9 (a) is an enlarged view showing a pattern of a power supply system of the integrated circuit in FIG. 8, FIG. 9 (b) is an enlarged view of a unit block shown in FIG. 9 (a), FIG. 10 is a diagram showing an example of power supply connection of the integrated circuit of FIG. 6 corresponding to the first embodiment of the present invention. FIG. 11 is a diagram showing another example of a power supply system of the integrated circuit of FIG. FIG. 12 is a diagram showing an integrated circuit layout pattern of a third embodiment of the integrated circuit of the present invention. FIG. 13 is a diagram showing an integrated circuit layout pattern of the fourth embodiment of the integrated circuit of the present invention. FIG. 14 is a diagram showing an integrated circuit layout pattern of a fifth embodiment of the integrated circuit of the present invention together with its power supply system pattern. FIG. 15 is a power supply system pattern used in the embodiment of FIG. FIG. 16 is a diagram showing another example of the power supply system pattern of the embodiment of FIG. 6, and FIG. FIG. 18 is a flowchart showing a design process applied to the integrated circuit of the present invention. FIG. 18 is a plan view showing a typical gate array used in a conventional logic integrated circuit. FIG. 19 is a MOS or CMOS device. FIG. 20 is a plan view showing a logic integrated circuit having a conventional polycell structure constituted by a conventional MOS or CMOS integrated circuit.
FIG. 3 is a diagram showing a configuration for connecting a power supply conductor to a power terminal. In the figure, 20 is an integrated circuit chip, 21 chip region, 22 unit blocks 22a are poly cell, 22b, 22c are power supply conductor system, 23 mini-macroblock, 23 _1, 23 _2, 23 ₃ mini macroblock column , 24 mega cell, 24a, 24b are power supply conductor system megacell, 25 _1, 25 _2, 25 ₃ global channel, 30 _1, 30 ₂ power bus, 31 _1, 31 ₂ main power bus, the 100 Indicates a macroblock,.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shigenori Ichinose 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Taketo Doi 2-1844-2 Kozoji-cho, Kasugai-shi, Aichi Prefecture Fujitsu VSI In-company (56) References JP-A-64-53430 (JP, A) JP-A-62-262641 (JP, A) JP-A-61-156751 (JP, A) JP-A-1-309353 (JP, A) (58) Fields surveyed (Int. Cl. ⁷ , DB name) H01L 21/82 H01L 27/118

Claims (15)

(57) [Claims] A first side and a second side extending in a first direction and having a first standard size, and a second side extending in a second direction.
A first main side and a second main side having a standard size, and including a unit block having a first power supply system extending in the second direction as a hierarchical unit, The first power supply system includes a second power supply system extending in the first direction.
A plurality of logic gates each having a size substantially proportional to power consumption are arranged in the second direction in each of the unit blocks. 2. A first unit block group in which at least two or more unit blocks are arranged adjacent to each other in the first direction such that the first sides and the second sides are aligned. The semiconductor integrated circuit according to claim 1, comprising: A first unit block group having at least two or more first unit block groups disposed apart from or adjacent to at least one of the first direction and the second direction; The semiconductor integrated circuit according to claim 2, comprising two unit block groups. 4. The semiconductor integrated circuit according to claim 1, wherein said logic gate has a current path extending substantially in a first direction. 5. In each of the unit blocks, the first power supply system includes a plurality of conductors that are separated from each other in the first direction and extend in parallel with the second direction. The semiconductor integrated circuit according to claim 1, 2 or 3, wherein 6. The power supply system according to claim 1, wherein the second power supply system is provided above the first power supply system.
The semiconductor integrated circuit according to claim 2. 7. The second power supply system includes at least two types of conductors extending in the first direction, wherein the conductors are shorter than the second standard size in the second direction. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is arranged repeatedly at a pitch. 8. The semiconductor device according to claim 1, wherein the conductor is repeatedly arranged in the second direction, and has a dimension set in the second direction so as to substantially cover the entire surface of the semiconductor integrated circuit. The semiconductor integrated circuit according to claim 7. 9. At least one pair of the first unit block groups are arranged in the second direction by a gap region extending in the first direction, and are arranged in the second direction. At least a portion of the conductor is provided in the gap region, and extends at least over a length of the pair of first unit blocks that extends in the first direction. The conductor includes the first unit. 4. The semiconductor integrated circuit according to claim 2, wherein each of the unit blocks included in the block group is connected to the first power supply system. 5. 10. In the case where there are a plurality of void regions, each of the plurality of void regions has the same length in the second direction, and the plurality of void regions are linear in the first direction. 10. The semiconductor integrated circuit according to claim 9, wherein the semiconductor integrated circuit extends in the second direction and is regularly arranged in the second direction. 11. A wiring conductor of a first type for wiring between logic gates included in the first unit block group separated from each other is provided in the gap region. A semiconductor integrated circuit according to claim 9. 12. The semiconductor integrated circuit according to claim 11, wherein the first type of wiring conductor is provided below the second power supply system on the gap region. 13. The semiconductor device according to claim 13, further comprising:
A third power supply system extending in the second direction and intersecting with the second power supply system, wherein the third power supply system includes a second power supply system and the first power supply. 4. The semiconductor integrated circuit according to claim 1, wherein power is supplied to the logic gate via a supply system. 5. 14. The third power supply system extends in the second direction and is shortest in the first direction within the first unit block group existing in the semiconductor integrated circuit. 14. The semiconductor integrated circuit according to claim 13, comprising at least two types of conductors repeatedly arranged in the first direction at intervals shorter than the length. 15. The semiconductor device according to claim 15, wherein the conductor is repeatedly arranged in the first direction, and has a dimension in the first direction set to substantially cover the entire surface of the semiconductor integrated circuit. 15. The semiconductor integrated circuit according to claim 14.