JP3026581B2 - Data signal demodulator - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a data signal demodulation device suitable for use in a video floppy playback device.

[Prior Art] FIG. 4 is a block diagram showing an example of a configuration of a conventional data signal demodulation device proposed by the present applicant as Japanese Patent Application No. 1-76324.

The disk 2 rotated by the motor 1 is reproduced by the head 3. The reproduced signal output from the head 3 is amplified by the preamplifier 4 and is a high-pass filter (HPF).
5, a low-pass filter (LPF) 8 and a tuning amplifier 10 respectively.

The high-pass filter 5 separates an FM luminance signal component from the input signal. The FM luminance signal separated by the high-pass filter 5 is input to a signal processing circuit 6, demodulated and processed, and then output to an encoder 7. Similarly, the FM color signal separated by the low-pass filter 8 is input to the signal processing circuit 9, demodulated and processed, and output to the encoder 7.
The encoder 7 adds the luminance signal and the chrominance signal and outputs the result as a composite video signal to a circuit (not shown).

On the other hand, the tuning amplifier 10 tunes to the DPSK signal frequency component of the input signal, separates it, and amplifies it. The output of the tuning amplifier 10 (FIG. 5B) is input to an envelope detection circuit 11, which detects the envelope. DPSK signal is
For example, if the data changes every 4H,
As apparent from comparison with the horizontal synchronization signal (Fig. 5A), 4H
Each time its phase changes, its envelope is also 4H
It changes every time. This change point is detected by the change point detection circuit 12. The detection output (FIG. 5C) of the change point detection circuit 12 is input to the demodulation data generation circuit 13. The demodulation data generation circuit 13 is composed of, for example, a flip-flop, and is triggered by the output of the change point detection circuit 12. As a result, the demodulated data generation circuit 13 generates DPSK demodulated data (D in FIG. 5) whose polarity is inverted each time a change point occurs.

The output of the signal processing circuit 6 is input to a synchronization separation circuit 14, which separates a vertical synchronization signal. The mono multivibrator 15 is triggered by this vertical synchronization signal and generates a reset pulse. Demodulated data generation circuit 13
Are reset by this reset pulse.

[Problems to be Solved by the Invention] As described above, the conventional device detects the change point of the envelope of the DPSK signal, triggers the flip-flop corresponding to the change point, and generates the DPSK demodulated data. Was. As a result, if there is a dropout in the DPSK signal (FIG. 5E), a change point corresponding to the dropout is detected (FIG. 5F), and there is a problem that erroneous demodulation is performed (FIG. 5). Figure G).

The present invention has been made in view of such a situation, and is intended to correctly demodulate a DPSK signal without being affected by dropout.

[Means for Solving the Problems] A data signal demodulation device according to the present invention includes a DPSK separation circuit that separates a DPSK signal from an input signal including a video signal and a DPSK signal, and an envelope that detects an envelope of an output of the DPSK separation circuit. A detection circuit, a change point detection circuit for detecting a change point of the output of the envelope detection circuit, and demodulated data for generating demodulation data of a DPSK signal whose polarity is inverted according to the change point based on the output of the change point detection circuit A generation circuit, a dropout detection circuit that detects a dropout of the DPSK signal based on the input signal, and a correction data generation circuit that generates correction data whose output level is inverted when the dropout is detected by the dropout detection circuit. , Performs an exclusive OR operation based on the demodulated data and the correction data to obtain corrected demodulated data that is not affected by dropout. And an exclusive OR circuit for outputting the same.

[Operation] In the data signal demodulation device having the above configuration, when dropout occurs in the DPSK signal, correction data is generated and combined with the demodulated data.

Therefore, the DPSK signal can be demodulated without being affected by dropout.

Embodiment FIG. 1 is a block diagram showing a configuration of an embodiment of a data signal demodulating apparatus according to the present invention. In FIG. 1, parts corresponding to those in FIG. Therefore, the description is omitted as appropriate.

In the present embodiment, the output of the preamplifier 4 is input to a dropout detection circuit 26, where a dropout is detected, and a D-type flip-flop 27 is
(Correction data generation circuit) is triggered. The output of the flip-flop 27 is an exclusive OR gate.
The output of the demodulation data generation circuit 13 is synthesized by 28 (synthesis circuit). The flip-flop 27 is reset by a reset pulse output from the mono multivibrator 15.

 Other configurations are the same as those in FIG.

Next, the operation will be described with reference to the timing chart of FIG.

As described above, the change point detection circuit 12 includes the tuning amplifier 10
When a phase change actually occurs in the output (FIG. 2B), a change point detection output (FIG. 2C) is generated. This change point detection output is input to the demodulation data generation circuit 13, and demodulation data (FIG. 2D) is generated.

This change point detection output (FIG. 2F) is a DPSK signal (2nd
FIG. E) also occurs when a dropout occurs. As a result, incorrect demodulated data (FIG. 2G)
Is generated.

On the other hand, if there is a dropout in the DPSK signal input from the preamplifier 4, the dropout detection circuit 26 detects this. When the dropout detection signal (FIG. 2H) is output from the dropout detection circuit 26, D
Type flip-flop 27 is triggered and its output level is inverted. Since the correction data output from the D-type flip-flop 27 is combined with the output of the demodulation data generation circuit 13 by the exclusive OR gate 28, the data output from the exclusive OR gate 28 (FIG. ) Is correct data.

Next, the reproduction operation of the DPSK demodulated data will be further described with reference to FIG.

The 4Hs of the first field of the DPSK signal, the 28H to the 32H, are the initial bits, the subsequent 32H to the 40H are provided with field or frame identification signals, and the 40H to the 68H are provided with track numbers. (Third
(Figures A and B). For example, in the example of FIG. 3, the DPSK signal (FIG. 3B)
The 32H, 44H, 48H, 56H of has a change point,
This change point is detected (FIG. 3C), and the waveform is shaped (FIG. 3D). A signal (E, F in FIG. 3) which is inverted to logic H or L is generated by this change point. The DPSK signal is read by calculating the exclusive OR of two consecutive logics.

[Effects of the Invention] As described above, according to the data signal demodulation device of the present invention, when a dropout occurs in a DPSK signal, correction data is generated and combined with demodulated data.
The DPSK signal can be demodulated without being affected by the dropout.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a data signal demodulator according to the present invention, FIGS. 2 and 3 are timing charts for explaining the operation of the embodiment of FIG. 1, and FIG. Block diagram showing a configuration of an example of a data signal demodulator,
FIG. 5 is a timing chart for explaining the operation of the example of FIG. 6, 9 Signal processing circuit, 10 Tuning amplifier, 11 Envelope detection circuit, 12 Change point detection circuit, 13 Demodulation data generation circuit, 14 Synchronization separation circuit, 26 Dropout Detection circuit 27 D-type flip-flop (correction data generation circuit) 28 Exclusive OR gate (synthesis circuit)

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/91-5/956 G11B 20/10

Claims (1)

(57) [Claims] 1. An input signal including a video signal and a DPSK signal.
A DPSK separation circuit that separates a DPSK signal; an envelope detection circuit that detects an envelope of an output of the DPSK separation circuit; a change point detection circuit that detects a change point of an output of the envelope detection circuit; and a change point detection circuit. A demodulation data generation circuit that generates demodulation data of the DPSK signal whose polarity is inverted according to the change point based on the output, and a dropout detection circuit that detects a dropout of the DPSK signal based on the input signal. A correction data generation circuit that generates correction data whose output level is inverted when a dropout is detected by the dropout detection circuit, and performs an exclusive OR operation based on the demodulated data and the correction data. An exclusive-OR circuit for outputting corrected demodulated data without the influence of dropout. Data signal demodulator.