JP3023339B2 - Message arrival notification method and system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD This application relates to a message processing system. Specifically, the present application relates to a method of notifying a message destination when a message arrives using a programmable interrupt initiated by the source and / or destination.

[0002]

Message processing system, such as multiprocessor data processing system 10 BACKGROUND OF THE INVENTION illustrated in Figure 1 for example, the processor 12 _1. . . It requires a reliable message communication path between each of the 12 _N processors. The system 10 illustrated in FIG. 1 uses an exemplary communication medium or switch network 20 commonly coupled to a processor 12. The processors communicate between each processor 12 and the media 20 with a respective connection 1.
6 ₁ . . . Each of the communication adapter 14 ₁ in order to control via the 16 _N. . . 14 _N may be required. Thus, for example, communication between software applications running on processor 12 of system 10 occurs over medium 20.

[0003] As each processor may support different asynchronous application software partitions, asynchronous message processing is a useful form of communication between the processors. In destination processor (eg, processor 12 _N), the incoming asynchronous message passing
It is buffered in the message reception queue in the usual manner . Thus, the application software running on the processor 12 _N is often message requires polling or monitoring of the queue to determine whether the incoming call. However, obtaining the status of such received messages can cause additional overhead due to unnecessary polling while waiting for the arrival of a particular message or any message. For some applications, this additional overhead does not significantly affect system performance and may therefore be acceptable.
However, in some applications, this additional overhead can have a significant effect on performance, making polling and monitoring of the message receive queue an unacceptable technique.

[0004] In addition to the problems described above with respect to polling or monitoring messages by a destination processor, an originating processor (eg, processor 12 ₁ ) explicitly notifies a message destination processor when a message of a particular type or priority arrives. Sometimes it is better to do that.

[0005]

Therefore, implementation hardware and software that provide each processor in the system and application software running thereon with the additional option of notifying the destination node when a message arrives. There is a need for a flexible method and system that includes data and data structures. The method and system, without forcing a specific notification method, and provides additional programmable call notification options, thereby to be able to select the best choice in terms of the requirements of a particular application .

[0006]

SUMMARY OF THE INVENTION A flexible message termination is provided by the present invention for a method, system, product containing program code, and data structure for notifying the destination node of the arrival of individual messages at the destination node. A notification technique is provided. The present invention provides programmable source and destination start interrupts for each message.

[0007] For example, first and second in any order, to which the two types of interrupt initiation of the present invention respectively apply.
Consider the message. For the first message,
The present invention provides for a source start interrupt (S) in a first message at a source node that is the source of the first message.
II) setting a field, and when the first message arrives at the destination node, the set S
Generating an interrupt at the destination node in response to the II field. In the case of a second message, the present invention comprises the steps of pre-setting the destination start interrupt (DII) field at the destination node and, upon arrival of the second message at the destination node, responding to the pre-set DII field. Generating an interrupt at the node.

[0008] Since the source node and the destination node can operate asynchronously, for a given message, eg, the first and second messages, both nodes set (redundantly) the interrupt field, and It is completely possible to trigger an interrupt by:

For other messages, the present invention may also include the step of polling a message reception queue at the destination node to determine whether another message has arrived at the destination node. If the polling determines that at least one message is arriving, the message is processed at the destination node.
Interrupt generation can be enabled and disabled using a programmable interrupt enable mask.

The process of setting the SII field can be incorporated into the actual transmission of the message from the source node to the destination node. This transmission may include the creation of a formatted transmission message descriptor (SMD) at the source node, where the SMD includes transmission control information for the message including the SII field. Presetting of the DII field at the destination node can be incorporated into the allocation of the message destination buffer at the destination node. Allocation of the buffer may include the creation of a formatted receive message descriptor (RMD) at the destination node, where the RMD contains the receive control information of the message including the DII field.

[0011] The message, transmitted message descriptor, and received message descriptor each include a formatted header data structure that includes a common field for the SII and DII fields, or both, and the programmable source of the present invention. Supports source and destination start interrupts.

The formatted message descriptors, message packets, and commands in the source and destination nodes also include the data structure portion of the present invention, and implement a system-wide source and destination start interrupt for each message. To facilitate.

Thus, the present invention provides an additional programmable option to notify a hardware or software application , for example, at a destination node, when a message arrives. The source and destination start interrupts of the present invention can be selectively invoked on a per-message basis (along with other standard approaches such as polling) to meet the performance requirements of a particular application.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS As mentioned above, FIG. 1 shows a plurality of processors 12 ₁ . . . Multiprocessor with 12 _N
An example of a message processing system in the form of a data processing system 10 is shown. Each processor may have a respective communication adapter 14 that operates a respective connection 16 with a common connection medium or switch network 20. The system can also include a storage medium 22 that holds or supports the application software and all associated data structures, protocols, and the like.

FIG. 2 shows the hardware / system of the system of FIG.
FIG. 3 is a software hybrid diagram, showing a message sending node 18;
₁ and the message destination node _18N are shown. As used herein, the term "node" is used broadly to mean any identifiable hardware and / or software that passes messages between them. In FIG. 2, the application software division of each node may or may not be associated. That is, it may or may not be a part of the common application. It is assumed that higher level hardware (eg, 12 in FIG. 1) also exists at each node, but is not shown. Also shown at each node are lower level communication system software (CSS), device drivers, and adapter hardware 14. Hereinafter, for simplicity of explanation, the application shall require that the message 40 is sent from the source node 18 ₁ through the switch network 20 to the destination node 18 _N. (However, in a practical system, all nodes are considered to include both the message sending and receiving functions described herein.)

In accordance with the present invention, the origination of the message 40 at the destination node 18 _N is such that the destination node hardware, higher-level application software, and communication system software (CSS) are immediately notified. An interrupt (SII) 50 and a destination start interrupt (DII) 60 are performed. When a message arrives, one or both of these two types of interrupts allow for immediate destination node notification. Both the source node and the destination node can determine when an interrupt is needed, and can initiate the necessary processing to interrupt the destination node when the associated message arrives.

As described in more detail below, source node 18
_The source start interrupt is set at 1 by setting the control field in the header data structure of the message 40. Therefore, the message 40 itself transmits the configured source interrupt field, and is thereby notified via hardware or software or interrupt both of the destination node when a message arrives at the destination node 18 _N. Furthermore, if the destination node has been allocated a buffer to receive incoming messages, the destination node itself can independently initiate a similar interrupt by pre-setting the same or similar fields.

If it is desired that the application not initiate an interrupt, the destination node can retain the ability to poll the incoming message queue.
However, applications are given flexibility as to whether and when to initiate an interrupt for a particular message or group of messages. The destination node may not only completely enable or disable the processing of the source or destination start interrupt, but may also include a programmable interrupt mask that enables or disables other types of interrupts.

As will be described, the system, software, commands, message packets, and data structures of the present invention are all necessary to support the programmable source and destination interrupts of the present invention on a message-by-message system-wide basis. Including features.

FIGS. 3-6 and the accompanying description disclose the hardware and software portions of an exemplary communication adapter 14 that facilitates source and destination start interrupts of the present invention. This is only an example, and those skilled in the art will recognize that other hardware and software techniques can be used to implement the present invention.

Referring to FIG. 3, the source node 1 of FIG.
8 ₁ and destination node 18 _N include an adapter memory 70 and a functional processor (eg, FIG. 1).
Processor interface controller 72 for interfacing with the processor 12), adapter flow control logic 74, and switch interface logic 7 for interfacing with the communication medium coupling the nodes (eg, switch network 20).
6 is included. Adapters generally perform the necessary functions of breaking a given communication into packets, if necessary, routing each packet through the switch network and reassembling the packet at the destination node later. Assemble the header information required for. In addition, the adapter can perform error detection, maintain tracking information to facilitate recovery from soft or hard errors during message transmission, and perform other necessary functions. In this specification,
The term "message" is used broadly to mean any type of communication between a source node and a destination node, and may include only a portion of the data for a larger message, May only include headers that have some usefulness to

As described above with reference to FIG. 2, there is a layer of software, referred to herein as CSS, between the application software that provides the necessary application software interface with the adapter hardware. CSS is a low-level device drivers may or may not be free Ndei than needed to operate the hardware subsystems in the adapter.
The CSS is preferably a CSS that is interrupted by a source or destination start interrupt of the present invention upon message arrival, which is handled in the CSS supervisor processing space. However, as shown in FIG. 2, the CSS can also interrupt the application software, or (if user-level interrupts are supported) can interrupt the application software directly upon the arrival of a message. And any of the appropriate hardware interrupt lines can also be carried out the necessary interrupt use.

[0023] According to the present invention, the transmission message descriptors in the source node 18 ₁ for the outgoing message is initially set, is maintained. Transmission message descriptor (SMD)
Is used to maintain the status of the message being sent. For each message sent, the CSS allocates the location of the SMD in the adapter memory 70 at the source node. The SMD is initialized by the adapter command and updated when the message is sent to the destination node and acknowledged by the destination node. SMD
Maintains the location of message data, the amount of message data, the destination of the message, and other important information needed for successful message transmission and recovery (if necessary). Similarly, the destination node 18 _N uses a received message descriptor (RMD) structure to maintain the status of the received message. For each message received, the CSS allocates an RMD location in adapter memory 70 at the destination node. RMD is initialized by an adapter command and updated when a message is received. (Note that the message descriptor may or may not include the actual message data to be sent or received. For larger messages, for example, over 1024 bytes, a separate buffer may be allocated and If the buffer in the descriptor
Access the buffer using the address field. However, for relatively short messages, the descriptor itself can serve as the buffer itself,
Real message data can be retained. ) RM
D maintains the location of the receive buffer, the size of the receive buffer, the expected source of the message, and other important information needed to receive and properly recover the message.

Examples of the transmission message descriptor and the reception message descriptor are shown below.

[Table 1]

[0025]

[Table 2]

According to the present invention, the header part of the message descriptor includes a CONTROL (control) area (the shaded part in the above figure). This control area includes a source start interrupt (SII) field and a destination start interrupt (DII) field (described above). As described below, the control area of this example can include 16 bits, of which 2 bits include the SII field and the DII field. Control area: Bit number Description 0 Kernel / -user message 1 Descriptor data / -DMA data 2 Application / -buffer space 3 Source start interrupt (SII) 4 Destination start interrupt (DII) 5 Pull response 6 Pull request 7 Recovery // Rendezvous 8 Retransmission 9 Rendezvous request 10 Undefined 11 Burst / -Non-burst 12 Reserved (0-identifier bit # 0) 13 Reserved (0-identifier bit # 1) 14 Reserved (0-identifier bit # 2) 15 Reserved ( 0-identifier bit # 3)

In this embodiment, separate fields are allocated to the SII field and the DII field in the control area. However, in an alternative embodiment, the message is generally transmitted regardless of which of the source node and the destination node has started the interrupt. These fields may be the same, since the same type of interrupt is generated at the destination upon arrival of the.

The control area described above in connection with SMD and RMD is an area of memory that is supported and replicated throughout many data structures and commands in the source and destination node adapters, and the system size per message. Of the present invention.

For example, referring to FIG. 4, a separate message packet 80 transmitted over the medium 20 (and thus necessarily maintained in each of the source and destination adapter memories 70) has a header portion 82 and a data portion 84. The header part 82 has a CII field in which the SII field and the DII field are allocated.
An ONCONTROL (control) area 86 is included. It is possible that only the SII field will be set before receiving the message at the destination node. The DII may or may not be preset in the destination node's receive buffer. The message packet 80 of FIG. 4 is reproduced as follows, as are other packet structures conforming to the universal header format including the SII and DII fields. For example, from the destination node, "Pull request message
In response, a "pull response message packet" containing data is transmitted from the source node. "Pull" packets are used to recover from previous transmission attempts of standard message packets.

[Table 3]

[0030]

[Table 4]

[0031]

[Table 5]

[0032]

[Table 6]

Similarly, the source node and destination node adapter commands also support a control region containing SII and DII fields. An example of the format of such a command is shown below.

[Table 7]

[0034]

[Table 8]

[0035]

[Table 9]

[0036]

[Table 10]

[0037]

[Table 11]

The "send message command" provides a mechanism for sending a message to the destination node via the adapter via the medium. This command contains all the parameters needed to create the aforementioned "Send Message Descriptor (SMD)". When the sending adapter receives the "send message command", the specified SMD is initialized in the adapter memory, leaving the selected fields blank and being filled by the actual send logic. At this point in the originating node process, S
A Source Start Interrupt (SII) field in the MD can be set to indicate a desire to interrupt the destination node when the associated message arrives at the destination node.

"Post message reception buffer (PM
The "RB)" command provides a mechanism at the destination node to post or allocate a buffer in the receiving adapter's memory for receiving messages arriving from the medium. This command includes the aforementioned “received message descriptor (RM
D)). All the parameters needed to create ") are included. When the PMRB command is invoked, the specified RMD is initialized in the adapter memory with the selected fields left blank for further processing. At this point in the destination node processing, DII
Fields can be preset. The PMRB command has a precedence property. That is, rather than being called in response to the actual presence of the message, it is called in anticipation of the arrival of the message at the destination node. This command is issued independently and asynchronously by the destination node software. Thus, the direct result is that a destination start interrupt can be invoked asynchronously on a message-by-message basis at the destination node, depending on the requirements of the particular application.

A list of posted buffers is maintained at the destination node's posted buffer index table. The posted buffer index table provides a mechanism for storing and retrieving posted receive buffers when a message is received.

The present invention can be implemented in combination with a polling technique to provide a high degree of application flexibility. If neither the SII field nor the DII field is set, polling can be used at the destination node. The received message is assigned to the posted RMD at the destination node and is assigned to the "User Message Receive Queue (UMRQ)" FIFO.
At the same time, the application program can poll to determine if a message has been received. Then, the earliest of the received messages, ie, the message at the output of the FIFO, is processed first at the destination node, and subsequent messages in the FIFO are processed later. An example of a UMRQ implementing a linked list of descriptors in the adapter memory is shown below. This UMRQ contains the descriptor index of the first descriptor, and also contains a count of the number of items in the UMRQ. (The linked list of descriptors is Q_ in each RMD.
This can be filled using the NEXT field, which contains the address of the next RMD in the linked list. )

[Table 12]

The polling of the UMRQ FIFO is performed using a "message receive queue fetch" command, the fields of which are as follows:

[Table 13]

Destination node 1 including adapter memory 70
4 If _N refers to the destination node the command and data flow diagram of Figure 5 is shown, the pointer points to the sequence of UMRQ FIFO 90 is _{RMD92 (RMD 1 ... RMD 4)} P1. . . It can be visualized as realizing the list of P4. Using the MRQF command 94, the UMRQ FIFO checks for incoming messages.
90 can be polled or monitored. However, if the interrupt operation, using the PMRB command 96 instead, the Source command (via message 40) so as to be the "message transmission command", SII in RMD ₄ is the next RMD Field or DII field or both can be set. The setting of the destination or source start interrupt is illustrated by paths 98 and 99 in FIG. When a message arrives and is successfully received by the UMRQ, the SII
By setting the field or the DII field, an interrupt 60 is performed in the destination node, and the destination node is notified of the arrival of the incoming message. UMR as in the example of FIG.
If there is a message before message 40 in the Q FIFO, the application program can immediately initiate a repeated MRQF command to empty the queue. In another example, if there is no message before this interrupt message in the UMRQ, the first MRQF command issued by the destination node software will retrieve the interrupt message.

Thus, the present invention provides the flexibility of notifying an application when a message arrives using standard polling techniques and / or selective source and destination start interrupts. These functions are provided to the system in the form of commands, descriptors, and message packets, all of which conform to the format required to support these functions on a system-wide basis. These functions can be selectively invoked on a per-message basis to meet the performance requirements of a particular application.

It may be a requirement of the system to completely disable certain types of interrupts. FIG. 6 illustrates a circuit 100 for enabling and disabling interrupts. This includes an interrupt pending register 10 containing the interrupt sources 110 of the M interrupts.
2 is included. Hardware or software
Providing a programmable interrupt enable mask 104 that is read / write accessible from a programming source 112 to provide any of a number (M) of interrupts in the system, including the SII and DII type interrupts described above. One can be completely disabled. In the circuit illustrated in FIG.
4 and the corresponding bit in the interrupt pending register 102 are ANDed, resulting in an overall O
Calculate R and generate interrupt 60. This is the S
Another interrupt programmability level provided by the present invention for completely disabling type II and DII type interrupt generation. (Even if the interrupt is disabled by the mask 104,
It is also possible that register 102 functions as a polled register. In that case, higher level software for register 102 may use a polling technique similar to that described above with reference to FIG. 5 to determine if an interrupt event has occurred. This may be particularly useful for software applications that do not support user-level interrupts. )

The present invention can be applied to, for example, the medium 22 shown in FIG.
5 may be incorporated into an article of manufacture (eg, one or more computer program products) having a computer usable medium, such as the adapter memory 70 of FIG. Within this medium, for example, computer readable program code means for providing and facilitating the features of the present invention are implemented. This article of manufacture can be incorporated as part of the system or sold separately. The present invention, whether incorporated in the above-described article of manufacture or contained in other memory components, also includes the formatted messages, descriptors, commands, and other data structures described above, which are also included in the present invention. Facilitates the inventive mechanism.

[0047]

[0048]

[Brief description of the drawings]

FIG. 1 illustrates an example of a message processing system having a plurality of processors coupled by a communication medium.

FIG. 2 is a hybrid hardware / software diagram illustrating a message source node and a message destination node, and a source and destination start interrupt when a message arrives, according to the present invention.

FIG. 3 is a diagram illustrating an example of a hardware subsystem of one of the communication adapters illustrated in FIGS. 1 and 2;

FIG. 4 is a diagram showing an example of a message packet data structure having a header portion including an interrupt control field and a data portion, and located in a memory of the communication adapter illustrated in FIG. 3;

FIG. 5 is a command and data flow diagram of a message destination node illustrating the relationship between an incoming message, a message reception queue, a message processing command, and a source and destination start interrupt according to the present invention.

FIG. 6 illustrates an example of a circuit for enabling and disabling source and destination start interrupts of the present invention using a programmable interrupt mask.

[Explanation of symbols]

 10 Multiprocessor Data Processing System 12 Processor 14 Communication Adapter 16 Connection 18 Node 20 Switch Network 22 Storage Medium 70 Adapter Memory 72 Processor Interface Controller 74 Adapter Flow Control Logic 76 Switch Interface Logic 80 Message Packet 82 Header section 84 Data section 100 Interrupt enable / disable circuit 102 Interrupt pending register 104 Interrupt mask

────────────────────────────────────────────────── ─── Continued on Front Page (72) Inventor Douglas James Joseph United States 06812 New Fairfield, Connecticut Rita Drive 54 (72) Inventor Francis A. Camp United States 05453 Essex Junction, Vermont Maine Street 1224 Apartment 102 (56) References JP-A-4-113442 (JP, A) JP-A-5-94421 (JP, A) (58) Fields studied (Int. Cl. ⁷ , DB name) G06F 15 / 177 676 G06F 13/00 353 H04M 3/42 EPAT (QUESTEL) INSPEC (DIALOG) JICST file (JOIS) WPI (DIALOG)

Claims (21)

(57) [Claims] 1. A method for notifying a destination node of the arrival of individual messages of a plurality of messages in a message processing system for each message, wherein the first message of the plurality of messages is the first message. In the source node that is the source of the message, the source start interrupt (SI
I) setting a field; generating a first interrupt at the destination node in response to the configured SII field when the first message arrives at the destination node; Pre-setting a destination start interrupt (DII) field at said destination node for said second message, responsive to said pre-set DII field upon arrival of said second message at said destination node. And generating a second interrupt at the destination node. 2. A message receiving queue is polled at the destination node for a part of the plurality of messages except the first and second messages, and one of the parts of the message arrives at the destination node. Determining at least one of a portion of the message to the destination node.
Processing the at least one message if it is determined from the polling that two messages are arriving. 3. The method of claim 2, further comprising using a programmable interrupt enable mask to enable generation of the first interrupt or generation of the second interrupt at the destination node. . 4. The method according to claim 1, further comprising the step of allocating a buffer at which the second message is to arrive at the destination node, during which the DII is allocated.
The steps of pre-setting the fields are performed;
The method of claim 1. 5. The step of allocating a buffer includes: at the destination node, creating a formatted receive message descriptor (RMD) holding receive control information for the second message including the DII field. The method of claim 4. 6. The method of claim 1, further comprising transmitting the first message from the source node to the destination node,
During the step of sending the first message, the SI
The method of claim 5, wherein said step of setting an I field is performed. 7. The method according to claim 7, wherein the step of transmitting a first message comprises: at the source node, a formatted transmission message descriptor (SMD) holding transmission control information for the first message including the SII field. The method of claim 6, comprising the step of creating. 8. The method according to claim 1, wherein each of the first message, the second message, the SMD, and the RMD is the SI message.
The method of claim 7, comprising a formatted header data structure including an I field and the DII field, and supporting source start and destination start interrupts in the message processing system. 9. The method of claim 8, wherein said SII field and said DII field include the same field in said formatted header data structure. 10. The method of claim 8, wherein said SII field and said DII field include different fields in said formatted header data structure. 11. A system for notifying a destination node of the arrival of each of a plurality of messages in a message processing system for each message, wherein the first message of the plurality of messages is the first message. In the source node that is the source of the message, the source start interrupt (SI
I) means for setting a field; means for generating a first interrupt at the destination node in response to the set SII field when the first message arrives at the destination node; Means for presetting a destination start interrupt (DII) field at said destination node; and responding to said preset DII field upon arrival of said second message at said destination node. Means for generating a second interrupt at the destination node. 12. A message receiving queue is polled at the destination node for a part of the plurality of messages except for the first and second messages, and one of the messages arrives at the destination node. Means for determining whether or not at least one of a portion of the message is sent to the destination node.
One of the messages that are coming is determined from the polling, further comprising a means for processing at least one message, system of claim 11. 13. The system of claim 12 , further comprising: means for using a programmable interrupt enable mask to enable the generation of the first interrupt or the generation of the second interrupt at the destination node. . 14. The means for presetting a DII field further comprises: means for allocating a buffer at which the second message should arrive at the destination node, wherein the DII field is preset in the means for allocating a buffer. The system of claim 11 , wherein said means is included. 15. The means for allocating a buffer includes: means for creating, at the destination node, a formatted received message descriptor (RMD) holding reception control information for the second message including the DII field. 15. The system of claim 14 , wherein: 16. The system further comprising: means for transmitting the first message from the source node to the destination node, wherein the means for transmitting the first message includes the means for setting an SII field. The system according to claim 15 . 17. The method of claim 1, wherein the means for transmitting a first message comprises: at the source node, a formatted transmission message descriptor (SMD) holding transmission control information for the first message including the SII field. 17. The system of claim 16 , including means for creating. 18. The method according to claim 18, wherein each of the first message, the second message, the SMD, and the RMD is
20. The system of claim 17 , including a formatted header data structure including an II field and the DII field to support source start interrupts and destination start interrupts in the message processing system. 19. including the same field of the SII field and the DII field is the formatted header data structure, the system of claim 18, wherein. 20. The system of claim 18 , wherein said SII field and said DII field include different fields in said formatted header data structure. 21. The message processing system consists multiprocessor data processing system, said source node and the destination node is comprised of each of the processing nodes of the multiprocessor data processing system of claim 11, wherein the system .