JP3019114B2 - Lock detection circuit of PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit used in, for example, a circuit for detecting a video signal or an audio signal, which is suitable for detecting a stable lock range.
The present invention relates to a lock detection circuit of an LL circuit.

[0002]

2. Description of the Related Art A synchronous detection system using a PLL circuit has been known as a detection circuit for a video signal or an audio signal.

In the case of this synchronous detection type detection circuit, PL
If the L circuit is not locked to, for example, the carrier of the input signal, a correct detection output cannot be obtained. For example, in the case of an audio signal, the detection output sound may be reproduced as a large noise, making it difficult to hear. .

Conventionally, by utilizing the fact that the PLL circuit IC has a lock / unlock output, the lock / unlock output allows the detection output in the unlock state where the PLL circuit is not locked. Is muted so that noise is not reproduced.

[0005]

SUMMARY OF THE INVENTION However, PLL
The lock / unlock output of the circuit IC enters a state indicating unlock after the PLL circuit has unlocked. Therefore, when the PLL circuit changes from the locked state to the unlocked state, a delay occurs until the lock / unlock output actually indicates the unlock state, and noise is generated during this delay period. Could not be avoided.

In particular, in the case of an in-vehicle or portable video monitor device or audio reproducing device, since the radio wave state changes greatly and is abrupt, the PLL circuit is easily unlocked, and the above-mentioned noise is reduced. The occurrence was a problem.

A first object of the present invention is to provide a lock detection circuit of a PLL circuit which can output information indicating that the lock has been released before the PLL circuit actually releases the lock.

A second object of the present invention is to provide a lock detection circuit of a PLL circuit which can always perform stable and faithful lock detection.

[0009]

In order to solve the above problems SUMMARY OF THE INVENTION The lock detection circuit of the PLL circuit according to the present invention, when the corresponding reference numerals of the embodiment described later, b to the input signal
A first comparison circuit 23 that compares an error voltage from a PLL circuit that outputs a locked signal with a first reference voltage V1;
A second comparison circuit 24 for comparing the error voltage with a second reference voltage V2, and a comparison output of the first and second comparison circuits 23 and 24, the first reference voltage V1 and the second The error voltage range between the reference voltage V2 and the reference
A circuit 27 for forming a lock detection output for bringing the L circuit into a locked state, and an error when the PLL circuit is locked.
Detection means 32 for detecting the voltage and the detection means
The first and second reference voltages based on the detected error voltage.
And a reference voltage setting means 30 including a determination means 33 for determining a pressure .

[0010]

In the above configuration, for example, the first reference voltage V
1 is set by the means 30 to a voltage, for example, ΔV lower than the error voltage V0 when the oscillation frequency of the PLL circuit is the oscillation center frequency f0, and the second reference voltage V2 is set to the oscillation frequency of the PLL circuit. Is set to a voltage V2 higher by ΔV than the error voltage V0 when the oscillation center frequency is f0. Then, the error voltage of the PLL circuit is compared with the first and second comparator circuits 23 and 24, locking the can <br/> error voltage from the circuit 27 is as between V2 from V1 state, it When it comes off, a lock detection output indicating an unlocked state is obtained.

Since the error voltage V0 is a value at the oscillation center frequency f0 of the PLL circuit, it is a value at the center of the lock range of the PLL circuit. Therefore, the lock detection output according to the present invention has a spread around the center of the lock range of the PLL circuit. For this reason, a stable and faithful lock detection range can always be obtained.

[0012]

1 is a block diagram showing an example of a main part of a portable television receiver using an embodiment of a lock detection circuit of a PLL circuit according to the present invention.

In FIG. 1, reference numeral 1 denotes a video intermediate frequency amplifier, and the amplifier 1 outputs a video intermediate frequency of 58.75 MHz.
z is obtained, which is the AGC amplifier 2
Is supplied to a detection circuit 3 composed of a balanced modulator.
The video intermediate frequency signal from the AGC amplifier 2 is
The oscillation signal is supplied to the L circuit 4 and an oscillation signal synchronized with the frequency and phase of the output signal of the AGC amplifier 2 is obtained from the PLL circuit 4. Then, the output signal of the PLL circuit 4 is supplied to the detection circuit 3.

From the detection circuit 3, the video signal is obtained by synchronous detection, supplied to the video amplifier 5, amplified, and supplied to the output terminal 7 via the muting circuit 6. The output terminal 7 is connected to a display device having a display element such as a liquid crystal display, and an output image is displayed on a screen of the display element. In the muting circuit 6, as will be described later, when the PLL circuit 4 detects that the lock is released, the video signal is not output from the circuit 6, and the output video signal is prevented from appearing at the output terminal 7. Things.

Further, the output signal of the video amplifier 5 is
Is supplied to the comparator circuit 8 for C. In this comparator circuit 8,
It is compared with the AGC reference voltage. Then, the comparison circuit 8
Is supplied to the AGC amplifier 2 via the AGC circuit 9, and the output signal level of the AGC amplifier 2 is controlled to be substantially constant.

The 54.25 MHz voice carrier component is supplied via an amplifier 11 to a detection circuit 12 configured as a balanced modulator. The output signal of the PLL circuit 4 is supplied to the detection circuit 12, from which an audio intermediate frequency signal of 4.5 MHz is obtained. Then, this audio intermediate frequency signal is supplied to the FM detection circuit 14 via the limiter circuit 13 and is subjected to FM demodulation.

The audio signal demodulated by the FM detection circuit 14 is led to an output terminal 16 via a muting circuit 15. The output terminal 16 is connected to, for example, a speaker to reproduce sound. Similarly to the muting circuit 6, the muting circuit 15 performs muting so that sound is not led out to the output terminal when the PLL circuit 4 described below is unlocked.

As a muting signal supplied to the muting circuits 6 and 15, a lock detection output of the PLL circuit 4 is used as described below.

That is, the PLL circuit 4 has an oscillation center frequency f0 (which is equal to the free-running frequency) of 58.75 MHz.
A variable frequency oscillator 41 of z is provided, and an oscillation output signal of the variable frequency oscillator (hereinafter referred to as VCO) 41 is supplied to a phase comparison circuit 42. On the other hand, the video intermediate frequency signal from the AGC amplifier 2 is supplied to the phase comparison circuit 42 via the 90 ° phase shifter 43 and is compared with the oscillation output signal of the VCO 41. The phase comparison error output of both input signals from the phase comparison circuit 42 is supplied to the VCO 41 via the low-pass filter 44, so that the oscillation output signal of the VCO 41 becomes the video intermediate frequency signal which is the output signal of the AGC amplifier 2. It is controlled to synchronize with.

The output voltage of the low-pass filter 44 is VC
An error voltage corresponding to the phase error between the output signal of O41 and the video intermediate frequency signal from the AGC amplifier 2. From the magnitude of this error voltage, the output signal of the PLL circuit 4, that is, the oscillation output signal of the VCO 41, It is possible to determine whether the signal is locked to the video intermediate frequency signal, which is the output signal of the AGC amplifier 2.

That is, in this example, the output error voltage of the low-pass filter 44 is
The DC error voltage ER is converted to a DC voltage by a smoothing circuit composed of an operational amplifier.
, And is also supplied to the other input terminal of the second comparison circuit 24, which also comprises an operational amplifier.

The other input terminal of the first comparison circuit 23 is connected to a reference voltage generation source 2 composed of an electronic volume.
5 is supplied. Also, the second
The other input terminal of the comparison circuit 24 is supplied with a second reference voltage V2 from a second reference voltage source 26 also formed of an electronic volume.

In this case, the first reference voltage V1 is selected so as to be smaller than the second reference voltage V2. Further, in the present invention, the output error voltage ER of the low-pass filter 44 when the oscillation frequency of the VCO 41 of the PLL circuit 4 is the oscillation center frequency f0, which is a free-running frequency, is set as the lock detection range setting center voltage V0, and V1 = V0-.DELTA.V It is selected so that V2 = V0 + .DELTA.V.

From the first comparison circuit 23, PL
When the error voltage ER of the L circuit 4 is higher than the first reference voltage V1, a high level output is obtained. Also,
From the second comparison circuit 24, an output which becomes high when the error voltage ER of the PLL circuit 4 is lower than the second reference voltage V2 is obtained. These first and second comparison circuits 2
The outputs of 3 and 24 are supplied to one and the other terminals of the OR circuit 27. Therefore, from this OR circuit 27,
When the error voltage ER of the PLL circuit 4 is V1 <ER <V2, the lock detection output signal LD (see FIG.
Is output to the output terminal 28, and the muting circuit 6 outputs a muting signal.
And 15.

The first and second comparators 23 and 24
The circuit composed of the OR circuit 27 and the OR circuit 27 is formed into an IC so that the influence of the temperature characteristic change does not occur in these circuits.

In this case, in the PLL circuit 4, when the frequency of the input signal is plotted on the horizontal axis and the error output voltage ER of the PLL circuit 4 is plotted on the vertical axis, the change of the error output voltage ER with respect to the frequency is shown by a solid line in FIG. 51.
In the characteristic curve 51 of FIG. 2, the oblique straight line portion where the error voltage changes with respect to the frequency change is the lockable range of the PLL circuit 4. The free-running frequency (= oscillation center frequency f0) of the PLL circuit used in the detection circuit of the television receiver in this example is selected so as to be the above-mentioned video intermediate frequency of 58.75 MHz.

The free-running frequency f0 of the VCO 41 of the PLL circuit
Is the free-run frequency and the oscillation center frequency. This frequency is, as is clear from FIG. 2 or, et al, PLL
It is at the center of the lockable range of the circuit 4. As described above, in this example, the PLL circuit 4 sets the oscillation center frequency f
Error voltage ER when locked against input signal at 0
Is the lock detection range setting center voltage V0 . Therefore, the lock detection range of the PLL circuit 4 is determined around the center of the lockable range of the PLL circuit 4, and the maximum dynamic range can be easily obtained.

That is, since the lockable range of the PLL circuit 4 is narrow when the electric field is weak, the lock detection range W needs to be set to fall within the narrowed lockable range when the electric field is weak. However, if the value of the error voltage ER when the PLL circuit 4 is at the oscillation center frequency f0 is not set to the center voltage V0, and the lock range is set around a voltage position shifted from this value, when the weak electric field is considered, Only a narrower lock range can be set.

For example, as shown in FIG.
Is the error voltage ER when E is the oscillation center frequency f0.
And this voltage E1 is used as the lock detection range setting center voltage V0.
In this case, the first and second reference voltages V1 = E2 and V2 = E3 at this time, and as is clear from FIG. 2, the lock detection range W1 is centered on the lockable range of the PLL circuit. Therefore, even when the lockable range is narrowed as shown by the one-dot chain line 52 in FIG. 2 during the weak electric field, the lock detection range W1 falls within this narrowed range.

On the other hand, for example, the voltage E4 shown in FIG.
, The first and second reference voltages V1 = E5, V5
2 = E6, the lock detection range is WE, and when the electric field is weak, the lock is detected, despite the fact that the lock is released.

As described above, by setting the value of the error voltage ER when the PLL circuit 4 is at the oscillation center frequency f0 as the lock detection range setting center voltage V0,
The lock detection range W of the LL circuit is determined around the center of the lockable range of the PLL circuit,
Lock detection can be performed stably and faithfully without detecting erroneous lock.

However, the value of the error voltage ER when the PLL circuit 4 is at the oscillation center frequency f0 is determined by one arbitrarily sampled PLL circuit IC, and the value at that time, for example, the voltage E1 is fixed. If the lock detection range setting center voltage V0 is set, the following problem occurs.

That is, since the ICs constituting the PLL circuit vary, the value of the output error voltage ER of the low-pass filter 44 at the free-running frequency f0 is
There are many cases where it differs depending on the L circuit IC.
For example, as shown in FIG.
When the error output voltage ER of the L circuit is set as V0 = E1 even though it is the voltage E7, the lock detection range becomes as shown by W1 in FIG. In the case of a weak electric field indicated by a chain line 52 in FIG.
The LL circuit 4 obtains a lock detection output indicating that the LL circuit 4 is still locked even though the lock is actually released. In this case, the noise as described at the beginning still occurs.

Therefore, in this example, the lock detection range setting center voltage V0 is set to the free running frequency f for each PLL circuit IC.
To set the value of the output error voltage ER at 0,
For example, it is set at the time of factory shipment.

That is, reference numeral 30 denotes a circuit for this purpose. The circuit 30 supplies the first and second reference voltages V1 and V2 to the detection circuit 32 for the set center voltage V0 and the electronic volumes 25 and 26. Memory, for example, RO
M34. The set center voltage V0 is obtained as follows.

That is, the VCO 41 of the PLL circuit 4 is oscillated by free running. And the switch 3 of the circuit 30
Turn 1 on. At this time, the error voltage of the low-pass filter 44 of the PLL circuit 4 is equal to the free-running frequency f of the VCO 41.
It is the error voltage when it is 0, and this is the V0 detection circuit 32
It is taken in.

The voltage V0 thus obtained is supplied to the first and second reference voltage setting circuits 33. This circuit 33
Calculates the first reference voltage V1 as a voltage lower by ΔV than the detected voltage V0, obtains the second reference voltage V2 as a voltage higher by ΔV than the voltage V0, and stores the respective values in the ROM 34. Then, the first and second reference voltages V1 and V2 stored in the ROM 34 are set in the electronic volumes 25 and 26. When the above settings are completed, the switch 31 is turned off and the product is shipped. At the time of use by the user, the reference voltage setting circuit 3
3 and the first and second reference voltages V stored in the ROM 34
1 and V2 are given to the electronic volumes 25 and 26.

The lock detection range set in this manner is a range in which the error output voltage ER = E7 of the PLL circuit at the free-running frequency f0 is set as the set center voltage V0 also in the case of the PLL circuit IC of FIG. W0.

As described above, the lock detection output LD obtained from the OR circuit 27 is always in the range set with the error voltage at the frequency f0 as the center. And lock detection can be performed faithfully. Therefore, muting can be performed reliably, and when the present invention is used in a detection circuit of an in-vehicle or portable video monitor device or audio playback device, even if the radio wave condition is large and changes rapidly, In addition, generation of unpleasant noise can be reliably prevented.

In the above example, means for muting a video signal and an audio signal includes:
The muting circuit is provided at the final output stage. Instead, the detector 3 or the amplifier 5 is controlled by the lock detection signal LD in the case of a video system, and the detector 12 and the amplifier 12 are controlled in the case of an audio system. The FM detector 14 may be controlled by a lock detection signal.

It should be noted that the present invention is not limited to the above-described detection circuit for a television receiver, but may be used for various electronic devices.
Needless to say, the LL circuit can be applied to the case where the lock detection range is detected.

[0042]

As described above, according to the present invention, since the lock detection output is obtained based on the error output voltage of the PLL circuit, the unlock state is set before the lock is actually released. If the lock detection output is used for a muting signal, the occurrence of noise as in the related art can be prevented.

Moreover, in the case of the present invention, the lock detection output is obtained by the first and second reference voltages set up and down around the error voltage at the oscillation center frequency. Even in the case where the electric field strength changes as in a portable television receiver, stable and faithful lock detection can be always performed.

[Brief description of the drawings]

FIG. 1 is a block diagram of an example of an electronic device using an embodiment of the present invention.

FIG. 2 is a characteristic diagram for explaining the present invention.

FIG. 3 is a characteristic diagram for explaining the present invention.

[Explanation of symbols]

 Reference Signs List 3 video signal detector 4 PLL circuit 6 muting circuit 12 audio signal detector 23 first comparison circuit 24 second comparison circuit 25 first electronic voltage for reference voltage supply 26 second electronic volume for reference voltage supply 27 OR circuit 32 V0 detection circuit 33 Reference voltage setting circuit 34 ROM for storing reference voltage

Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03L 7/095

Claims (3)

(57) [Claims] 1. A PL for outputting a signal locked to an input signal
A first comparison circuit for comparing the error voltage from the L circuit with a first reference voltage; a second comparison circuit for comparing the error voltage with a second reference voltage; and the first and second comparison circuits From the comparison output of
A circuit that forms a lock detection output that sets an error voltage range between the reference voltage of the second reference voltage and the second reference voltage to a locked state of the PLL circuit, and an error voltage when the PLL circuit is locked.
Detecting means that emits, and at the time of lock detected by this detecting means
The first and second reference voltages based on the error voltage
Lock detection circuit of the PLL circuit including a reference voltage setting means composed of a determining means for determining, a. 2. The detecting means of the reference voltage setting means,
The variable frequency oscillator of the PLL circuit has its oscillation center frequency
Error power when the PLL circuit is locked
Pressure, and the determining means of the reference voltage setting means includes the detecting means
With the error voltage detected at the center as the center, the first and the second
2. The method according to claim 1, wherein the second reference voltage is determined.
Lock detection circuit of the PLL circuit described above. 3. The method according to claim 2, wherein the reference voltage setting means is configured to determine the reference voltage .
A memory for storing information on the first and second reference voltages;
2. The lock detection circuit of a PLL circuit according to claim 1, wherein