JP3018336B2 - Information processing device - Google Patents

Description

The present invention relates to an information processing apparatus that performs processing using a CPU having at least two or more operation modes as a core. With the advancement of technology, microprocessors and peripheral control LSIs have been supplied at low cost, and a high-performance computer system can be constructed simply by combining them appropriately.
The 0286 has both a real mode and a protect mode. This processor is mounted on many small computers such as workstations, and has an operating system (OS) that operates in each mode. In real mode, it is fully compatible with 18086, so Microsoft M
The OS on a conventional personal computer, such as S-DOS, will be referred to as the real mode OS below. In the protected mode, the advanced functions of the processor are used to make the C-C
An OS with multi-process functions such as DOS286 is called a protected mode OS, but it is operating. Due to these differences in use, some general-purpose workstations run both a real mode OS and a protected mode OS. (Problems to be solved by the invention) In this case, conventionally, the real mode OS and the protected mode
OS switching was performed using a reboot method based on IPL (Initial Program Load), so switching time was enormous, and the OS environment before switching was completely destroyed. The present invention has been made in view of the above circumstances, and enables a real mode OS and a protected mode OS to be simultaneously resident on a memory and to switch at a high speed. , The state of peripheral devices, etc.) to continue the processing after switching. [Structure of the Invention] (Means and Actions for Solving the Problems) The present invention is an information processing apparatus including a main memory and a secondary storage device for realizing the above-mentioned object. In an information processing apparatus having a CPU executable in at least two operation modes depending on the size, an area in which an operation environment of the information processing apparatus is stored in each of a plurality of operation modes is provided in the main storage device, Generating a request to switch to the second operation mode while executing in the first operation mode; and, after the operation mode switching request is generated by the generation means, the information processing is performed in accordance with the transition from the first to the second operation mode. Disables device interrupts, and disables
Save the CPU context in the first operation mode area,
Means for switching the CPU to the second operation mode after saving the operation environment, restoring a CPU context in the second operation mode to which the CPU is switched, and the second operation mode after restoration by the restoration means Means for executing a program executable by the program. In the information processing apparatus of the present invention, when switching the CPU being executed in the first operation mode to the second operation mode, the interruption of the information processing apparatus is prohibited, and the operation environment in the first operation mode is set to the access speed. Saves the data in an area provided in the high-speed main storage device, and switches the CPU to the second operation mode after the storage. That is, in the information processing apparatus of the present invention, saving and restoring of the operating environment are executed by writing and reading to and from the main storage device having a high access speed. Generally, the main storage device has an access device composed of a high-speed semiconductor memory, and the access time is very small compared to a secondary storage device such as a disk. Therefore, the switching can be significantly speeded up as compared with the case where the operating environment is saved and restored using a secondary storage device such as a disk. In addition, by prohibiting the interruption of the information processing device, the destruction of the operating environment due to the transition of the operation mode is reliably prevented. (Example) Hereinafter, an example of the present invention is described in detail using drawings. Fig. 1 shows the real mode OS and protected mode
FIG. 5 is a diagram illustrating a memory arrangement when an OS is simultaneously resident. The real mode OS 11 is located at the lowest level of the memory in the same manner as the normal case loaded by the IPL. In the case of the real mode OS, since the address bus has 20 bits, the required area is at most 1 megabyte. Put protect mode OS12 in the memory area after that, but in the middle part,
A shared area 13 is provided. The shared area 13 has a real mode OS
And the environment storage areas 131 and 13 of the protected mode OS
2 and message storage area 132,1 exchanged when OS is switched
34 are provided. In the figure, R → P indicates switching from the real mode S to the protection mode S, and P → R indicates switching from the protection mode S to the real mode S. FIG. 2 is an operation conceptual diagram showing a control flow at the time of switching between a real mode OS and a protected mode OS. When transferring control from the protected mode OS21 to the real mode OS22, the real mode OS switching driver 23 on the protected mode OS21
Conversely, when transferring control from the real mode OS 22 to the protected mode OS 21, the protect mode OS switching driver 24 is called on the real mode OS 22. Each of the switching drivers 23 and 24 first saves the current OS environment, and then transfers control to the partner driver. The transferred driver resumes execution of the OS after restoring the OS environment. That is, the real mode OS switching driver 23 and the protected mode OS switching driver 24 operate as a coroutine. FIG. 3 is a diagram showing a configuration example of a personal computer to which the present invention is applied. In the figure, reference numeral 31 denotes a CPU, and in the embodiment of the present invention, a 16-bit microprocessor 180286 manufactured by Intel Corporation is used. Reference numerals 32 to 36 denote peripheral control LSIs, which are respectively a keyboard controller (KBC), a floppy disk controller (HDC), a hard disk controller (HDC), and a display controller (CRT).
C), a printer controller (PRTC), which is composed of commercially available LSIs and is connected to each peripheral device, that is, a mouse 37 / keyboard unit 38, a floppy disk device 39, a hard disk device 40, a display unit 41 and a printer Control 42.
43 is a DMA controller, and 44 is an interface controller (PIC) with a built-in register. Reference numeral 10 denotes a main memory, which has a memory structure shown in FIG. Each of the above blocks 10, 31 to 36 and 43, 44 is commonly connected to a system bus 45 having a plurality of lines for address, data, and control. Hereinafter, the operation of the embodiment of the present invention will be described in detail.
For convenience of explanation, the real mode OS is called RL-OS-22, and the protected mode OS is called PT-OS-21. First, RL-OS
A description will be given from the method of simultaneous residence of 22 and PT-OS21. First RL−
The OS-22 is loaded by a normal IPL. Next, under the control of the RL-OS 22, the PT-OS 21 is loaded with a margin after the RL-OS 22 for the shared area. This is performed by a PT-OS boot utility program on the RL-OS 22. The PT-OS boot utility loads PT-OS21 on the same principle as IPL,
Since the load address is not address 0 but (RL-OS size) + (shared area size), relocation is performed by adding this bias value to the segment base of each descriptor in the GDT global descriptor table. . Next, the principle of the control transfer between the RL-OS22 and the PT-OS21 will be described. First, the control transfer method from the RL-OS22 to the PT-OS21 will be described. PT-OS switching driver on RL-OS22
24 first saves the current environment (CPU context). After saving all register information except the control stack (CS) and instruction pointer (IP) registers in the driver that can be referenced at the destination address from CS: IP, restart the address CS, IP
Save the register in the RL-OS environment save area. This is because in real mode there is no protection, so at least CS and IP
This is because control can be transferred if the register is guaranteed. Registers other than CS and IP registers are RL on PT-CS21.
After the control is returned from the OS switching driver 23, the operation is restored in the environment restoration processing part. Next, the transition part to PT-OS21 is the GDT stored in the PT-OS environment storage area.
The control is transferred based on the information of the R, DS, ES, CS, and IP registers. Restoration of other registers is performed by the PT-OS environment restoring portion of the RL-OS switching driver 24 on the PT-OS 21. The following description shows the coding of the switching part.
This code is executed with the interrupts disabled even after the external circuit is set to the protect mode. Then the CPU switches to the protect mode. Intel's manual states that registers such as LDTR, TSSR, etc. must be guaranteed at this time, but here, only GDTR is guaranteed.
From to, using the CS register cache,
Continue running. Thus, the processor key prefetched in the real mode is cleared. , Recovers DS and ES from the stack, but uses a cache of SS registers. lgdt [bp + 6] smsw ax or ax, 1 lmsw as ... jmp prot ... prot: mov ds, [bp + 18] ... moves, [bp + 20] ... jmp [bp + 14] ... (indirect for jump) bp + 6], [bp + 1
8], [bp + 20], and [bp + 14] contain the PT-OS and GDTR, DS, ES, CS: IP register contents extracted from the environment storage area. Next, a control transfer method from PT-OS21 to RL-OS22 will be described. The RL-OS switching driver 23 on the PT-OS 21 saves information such as the current GDTR, LDTR, IDTR, TR and TSS in the C-DOS environment saving area in the environment saving part. After that, the contents of CS and IP in the MS-DOS storage area are set in the system start address area, and the CPU is reset. Control transfers to the system initialization routine in real mode, and the system initialization routine sets the system start address that has been set, that is, RL-OS.
The control is transferred to the PT-OS switching driver 21 above. Lastly, how to save the state of the peripheral device will be described. First, the disk device will be described. Normally, the OS has a write-through type disk cache in the memory to make disk access more efficient. However, if the OS is switched as it is, the contents of the cache differ from the contents of the disk, and the disk is destroyed. Flush out the cache before the switch and invalidate the cache. When the FDC 33 and the HDC 34 are in operation, the operation is switched when the operation is completed. Next, the register information of the CRTC 35 and the screen information of the CRT 41 are saved before the switching, and are restored after the switching. Printer 42, keyboard 38, mouse 37
For devices where data drop does not have a significant effect, reset the PIC44 when switching. [Effects of the Invention] As described above, according to the present invention, the following effects can be obtained. (1) Switching between the real mode OS and the protected mode OS can be performed at a higher speed than the conventional reboot method. (2) The state before switching is preserved in switching. (It is completely destroyed by the reboot method)

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a memory arrangement when a real mode OS and a protected mode OS are simultaneously resident in a main memory, and FIG. 2 is a switching operation between the real mode OS and the protected mode OS. FIG. 3 is a diagram showing a configuration example of a personal computer to which the present invention is applied. 11: Real mode OS resident area, 12: Protected mode OS resident area, 13: Common area, 23, 24 ... Switching driver.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Kinya Aoshima               2-9 Suehirocho, Ome City, Tokyo Stock               Company Toshiba Ome Factory                (56) References JP-A-60-97440 (JP, A)                 JP-A-58-181149 (JP, A)                 JP-A-62-133533 (JP, A)                 JP-A-64-4838 (JP, A)

Claims (1)

(57) [Claims] An information processing apparatus including a main storage and a secondary storage device, the information processing apparatus having a CPU executable in at least two operation modes depending on the size of an address space. An area in which an operation environment of the information processing apparatus is stored in the main storage device, a unit that issues a request to switch to the second operation mode while the CPU is being executed in the first operation mode; After the operation mode switching request is issued, the first
From the second operation mode, the interrupt of the information processing device is prohibited, the CPU context in the first operation mode is saved in the first operation mode area, and after saving the operation environment, Switching the CPU to the second operation mode,
Means for restoring a CPU context in a second operation mode of a switching destination; and means for executing a program executable in the second operation mode after restoration by the restoration means. Information processing device.