JP3017793B2 - Digital wireless communication device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a digital radio communication device, and more particularly to a receiving device used in a digital radio communication system in which at least one is a mobile station.

(Prior Art) Cellular wireless communication devices have rapidly spread since their practical use. In recent years, digital cellular radio communication devices have been developed in addition to conventional analog cellular radio communication devices.

In such digital mobile communication, when the data transmission speed is several tens of Kbps or more, the bit error rate is significantly deteriorated due to the influence of multipath propagation of radio waves. This is because the transmission wave follows various paths before reaching the receiver antenna, so various time delays occur depending on the paths,
This is caused by the fact that a transmission signal at a certain point in time is superimposed on a transmission signal (symbol) at a certain point in time and causes intersymbol interference.

It is conceivable to use an equalizer to prevent such signal degradation. The use of the equalizer makes it possible to compensate for waveform distortion caused by superimposing a waveform at an earlier time on a waveform at a certain time.

(Problems to be Solved by the Invention) However, when the influence of a delayed wave due to multipath propagation is small, such as when the receiving station is near the transmitting station,
The bit error rate may be lower when demodulation is performed by differential detection without passing through an equalizer than when demodulation is performed using the output of an equalizer.

The equalizer is CMOS (Complementary Metal Oxide Se
In the case where the equalizer is constituted by a micondvctor device, there is also a problem that a large amount of power is consumed if the equalizer is always operated.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a digital radio communication device that most preferably reduces a bit error rate of a received signal.

It is a further object of the present invention to provide a digital radio communication device which is adapted to reduce power consumption by an equalizer.

[Configuration of the invention]

(Means for Solving the Problems) A digital wireless communication apparatus according to the present invention comprises: a receiving unit for receiving a propagated digital modulation signal;
Equalizing means for reducing signal distortion in the received signal, demodulating means for demodulating the received signal by delay detection, and a signal whose signal distortion has been reduced by the equalizing means based on predetermined conditions. A switching unit for selectively switching the received signal to be demodulated by the demodulation unit or to be demodulated by the demodulation unit without passing through the equalization unit; and supplying an operation clock signal to the equalization unit. Supply means for controlling when the demodulation means does not demodulate the signal whose signal distortion has been reduced by the equalization means, so that the supply of the operation clock signal to the equalization means by the supply means is stopped. Control means.

According to another aspect of the present invention, there is provided a receiving means for receiving a propagated digital modulated signal, an equalizing means for reducing signal distortion in the received signal, and a demodulating means for demodulating the received signal by delay detection. And a signal whose signal distortion has been reduced by the equalizing means is demodulated by the demodulating means, or a received signal is demodulated by the demodulating means without passing through the equalizing means, based on predetermined conditions. Switching means for selectively switching, power supply means for supplying power to the equalization means, when the demodulation means is not demodulating the signal of which signal distortion has been reduced by the equalization means, And control means for controlling the power supply means to stop supplying power to the equalization means.

Further, another invention is a receiving means for receiving a digital modulation signal propagated by the time division multiplexing method, an equalizing means for reducing signal distortion in the received signal,
Demodulation means for demodulating a received signal by delay detection; and a signal whose signal distortion has been reduced by the equalization means according to a received electric field strength detected by the detection means, or the equalization means. While selectively switching control so that the received signal is demodulated by the demodulation means without passing through, and when receiving a signal in a slot period other than the one addressed to the own device, the received signal does not pass through the equalization means, And control means for setting to be demodulated by the demodulation means.

(Operation) In the present invention, compensation for signal distortion in a received signal by the equalizing means is performed or not performed according to the received electric field strength of the received digital modulation signal. That is, when the received electric field strength is strong, it is determined that the received signal is hardly affected by the delay wave, and the demodulation by the delay detection is performed without using the equalizing means. On the other hand, when the received electric field strength is weak, it is determined that the received signal is susceptible to the delayed wave, and the signal distortion in the received signal is reduced by the equalizing means, and then demodulation by delayed detection is performed. Therefore, demodulation is performed on the signal in which the signal distortion is most suitably reduced, and the bit error rate of the received signal can be suppressed low.

Further, for example, as described above, when the equalizing means is used or not used under predetermined conditions, the power supply to the equalizing means is stopped when the equalizing means is not used, or the equalizing means is used. By stopping the supply of the operation clock to the power supply, power consumption can be reduced.

(Example) Hereinafter, the present invention will be described in detail based on an example of the present invention. This embodiment is an example in which the present invention is applied to a digital cellular wireless telephone device.

FIG. 1 is a block diagram showing a main part of a digital cellular radio telephone according to the present embodiment. Antenna 100
Is input to the receiving unit 104 via the duplexer 102. The reception signal is demodulated from a signal in the frequency band of 800 to 900 MHz into a baseband signal by the reception unit 104, and the baseband signal is converted to an A / D conversion unit 106.
A / D conversion is performed. The A / D-converted received signal is subjected to quadrature demodulation by a quadrature demodulation circuit 107, passes through a low-pass filter 109, and is equalized according to a connection state of a switching unit 108.
The signal is input to the delay detection circuit 111 via 110 or without passing through an equalizer. 4-DP in the delay detection circuit 111
The digitally modulated signal differentially encoded by SK is demodulated by differential detection. This demodulated signal is channel decoder
Deinterleaving is performed by 112, and error correction is performed. Further, the encoded audio signal is decoded by the speech decoder 114, and the audio signal is output from the speaker 118 via the audio circuit 116.

Quadrature demodulation circuit 107, low-pass filter 109, synchronous clock recovery circuit 113, switching unit 108, and delay detection circuit 111
The modem demodulation unit 115 is constituted by
Can be realized by a single LSI device together with the modem modulator 125. The synchronization / clock recovery circuit 113 extracts a synchronization word and designated slot information from the received signal, and establishes synchronization and identifies a slot.

The audio signal input from the microphone 120 is transmitted to the audio circuit 1
It is input to the speech encoder 122 via 16. An error code is added to the audio signal encoded by the speech encoder 122 by the channel encoder 124 and interleaved. Further, the signal is differentially encoded by 4-DPSK by the modem modulator 125, quadrature-modulated, and D / A
D / A conversion is performed by the conversion unit 126. The D / A-converted signal is modulated into a transmission signal in the 800 to 900 MHz band in transmitting section 128, and transmitted via duplexer 102 and antenna 100.

The CPU 130 controls each unit via a bus 132 and an interface 134. The CPU 130 is connected to the ROM 136 for storing an operation program, the RAM 138 for storing various data, and the like via the bus 132.

The received electric field strength is detected in the receiving unit 104, the detected value is A / D converted by the A / D converter 140, and input to the CPU 130 via the interface 134 and the bus 132.
FIG. 2 is a block diagram showing a detailed configuration of the receiving unit 104. The received signal is mixed with the output signal of the first local oscillator 202 in a mixer 204, dropped to a first intermediate frequency, amplified by a first intermediate frequency amplifier 206, and then output from a second local oscillator 208. Mixer 2
Mixed at 10 and dropped to an intermediate frequency signal. This intermediate frequency signal is fed to several linear amplifiers 212.
Amplified by The outputs of these linear amplifiers 212 are taken out by a diode 214, and the analog value of the sum of them is input to an A / D converter 140 and A / D converted. The converted digital value, that is, the received electric field strength value is sent to the CPU 130 as described above.

The equalizer 110 is, for example, a non-linear equalizer composed of a feedforward filter with some tap coefficients and a feedback filter with some tap coefficients, which can be realized by CMOS logic elements. An operation clock signal source 142 is connected to the equalizer 110 to supply an operation clock which is a pulse signal of a predetermined frequency. The switch 144 is for stopping the supply of the operation clock to the equalizer 110.
Done under 30 controls. The power supply 146 is a battery for supplying power to the entire apparatus, and also supplies power to the equalizer 110. A switch 148 is also provided in the power supply path to the equalizer 110.
Done under 30 controls.

Next, the operation of the present embodiment will be described with reference to FIGS.

FIG. 3 is a diagram showing a format of a digital modulation signal sent by the time division multiplex method. For example, in an analog / digital compatible cellular radiotelephone system, the speech channel is divided into six slots as shown in FIG. Two slots (slot 1 and slot 4 in the figure) are used. A synchronization word and designated slot information are inserted into each slot, and these words are used to establish synchronization with a transmission signal and determine whether the slot is addressed to the own device.

FIG. 4 is a flowchart showing a processing algorithm for explaining the characteristic receiving operation of this embodiment. For example, a reception operation when one communication link is set by the above-described communication channel will be described as an example.

First, the equalizer 11 is controlled under the control of the CPU 130 in the initial state.
0 is supplied with the operation clock (step 400),
The switching unit 108 is connected so that the output of the equalizer 110 is input to the differential detection circuit 111, that is, the output B is selected (step 402).

The digitally modulated wave received by the antenna 100 is transmitted to the duplexer 102, the receiving unit 104, the A / D converter 106, and the equalizer 11
0 is input to the channel decoder 112. The synchronization / clock recovery circuit 113 extracts the synchronization word and the designated slot information from the received signal, establishes synchronization, and identifies whether the slot is addressed to the own device (step 404). If the slot is not addressed to the own device, the CPU 130 controls the switching unit 108 so that the output terminal A is connected to the channel decoder 112 and the switch 144 stops supplying the operation clock to the equalizer 110. Then, the switching unit 108 and the switch 144 are controlled (steps 406 and 408).

If it is determined in step 404 that the receiving slot is a slot addressed to the own device, the CPU 130
The received electric field strength detected in the step is compared with a threshold value preset and held in the EPROM 138 (step 410). If the received electric field strength is higher than the predetermined threshold value, the CPU 130 The switching unit 108 and the switch 144 are controlled such that the terminal A is connected to the channel decoder 112 and the supply of the operation clock to the equalizer 110 is stopped at the switch 144 (step
412, 414). Therefore, when the reception state of the digital modulation wave is good and the reception electric field strength is strong, the equalizer 11
Demodulation by delay detection is performed in the delay detection circuit 111 without passing through zero.

On the other hand, if the received electric field strength is equal to or less than the predetermined threshold value in step 410, the CPU 130 controls the equalizer 110 so that the operation clock is supplied to the equalizer 110. The switch 144 and the switching unit 108 are controlled so as to be connected to the circuit 111 (steps 416 and 4
18). Therefore, when the reception state of the digital modulation wave is not good and the reception electric field strength is weak, the signal distortion included in the reception signal is reduced by the equalizer 110, and then the demodulation by the delay detection is performed in the delay detection circuit 111.

According to this embodiment, if the electric field strength of the direct wave from the base station is sufficiently strong, for example, because the wireless telephone device is near the base station, the intensity of the delay wave due to multipath is relatively ignored. As much as possible, there is no need to consider the effects of delayed waves. In this case, demodulation is performed without using an equalizer. On the other hand, when the radiotelephone apparatus moves away from the base station, the reception electric field strength of the reception signal becomes weak, and the difference in intensity between the direct wave and the delayed wave in the reception signal also becomes small. Therefore,
Although it is difficult to distinguish a direct wave from a delayed wave, in this case, signal distortion is reduced by the equalizer 110, so that a received signal with less signal distortion can be demodulated.

When the equalizer 110 is not used, the operation clock is not supplied to the CMOS logic elements constituting the equalizer 110. Generally, power is consumed each time a CMOS logic element performs a switching operation, but no switching operation occurs unless an operation clock is supplied. Therefore, no power is consumed by the equalizer 110 while the equalizer 110 is not used.

Also, in this embodiment, the equalizer was not used or not depending on the received electric field strength, but other conditions, such as compensating signal distortion by the equalizer according to the bit error rate of the received signal, It may not be done. That is,
If the bit error rate is low, the received signal is demodulated by delay detection without using the equalizer, and if the bit error rate is high, the signal distortion of the received signal is reduced by the equalizer, and then the received signal is detected by delay detection. Demodulate. Even in this case, when the equalizer is not used, power consumption can be further reduced by not supplying the operation clock to the equalizer.

Next, the operation of another embodiment of the present invention will be described with reference to FIG. Steps of the same processing as in the above-described embodiment are denoted by the same reference numerals.

In the above embodiment, when the equalizer is not used, the supply of the operation clock to the equalizer is stopped. However, in the present embodiment, the power supply to the equalizer is stopped. Therefore, instead of steps 408 and 414 in FIG.
Steps 608 and 614 for stopping the power supply to the equalizer 110 by opening 8 are added, and steps 400 and 4
By closing switch 148 instead of 16, equalizer 1
Steps 600 and 616 for starting power supply to 10 are added.
According to this embodiment, when the equalizer 110 is not used, power consumption by the equalizer 110 is eliminated, and power can be saved.

〔The invention's effect〕

According to the present invention, the signal distortion in the received signal is corrected by the equalizing means as needed, so that the bit error rate of the received signal can be suitably reduced. Also,
When the equalizing means is not used, the supply of power or the operation clock to the equalizing means is stopped.
Power consumption by the equalizing means can be greatly reduced.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a digital radio telephone apparatus according to an embodiment of the present invention, FIG. 2 is a block diagram showing a receiving unit 104 in FIG. 1, and FIG. FIG. 4 is a diagram showing a format of a digital modulation signal according to a multiplexing method. FIG. 4 is a flowchart for explaining the operation of one embodiment of the present invention;
FIG. 5 is a flowchart for explaining the operation of another embodiment of the present invention. 100: antenna, 102: duplexer, 104: receiver, 106
…… A / D conversion unit, 108 …… Switching unit, 110 …… Equalizer, 112…
... channel decoder, 114 ... speech decoder, 116 ...
… Voice circuit, 118… speaker, 120… microphone, 122…
... Speech encoder, 124 ... Channel encoder, 1
26 D / A converter, 128 Transmitter, 130 CPU, 132
... bus, 134 ... interface, 136 ... ROM, 138 ...
... RAM, 140 ... A / D converter, 142 ... Operation clock signal source, 144 ... Switch, 146 ... Power supply, 148 ... Switch.

Continuation of the front page (56) References JP-A-4-77019 (JP, A) JP-A-3-177136 (JP, A) 1990 IEICE Autumn National Convention Lecture Papers, Volume 2, p. 2-281 (58) Field surveyed (Int. Cl. ⁷ , DB name) H04L 27/00-27/38

Claims (9)

(57) [Claims] 1. A receiving means for receiving a propagated digital modulation signal, an equalizing means for reducing signal distortion in the received signal, and a demodulating means for demodulating the received signal by delay detection. A signal whose signal distortion has been reduced by the equalizer is demodulated by the demodulator, or a received signal is demodulated by the demodulator without passing through the equalizer based on predetermined conditions. Switching means for selectively switching, supply means for supplying an operation clock signal to the equalization means, and when the demodulation means is not demodulating a signal whose signal distortion has been reduced by the equalization means, Control means for controlling supply of the operation clock signal to the equalization means by the supply means to be stopped. 2. The digital radio communication apparatus according to claim 1, wherein said equalizing means is constituted by a CMOS logic element. 3. The digital radio communication apparatus according to claim 1, wherein the digital modulation signal is a signal transmitted by a time division multiplex system. 4. The switching means switches so that a received signal is demodulated by the demodulation means without passing through the equalization means when at least a signal in a slot period other than the one addressed to the own apparatus is received. The digital wireless communication device according to claim (3). 5. A receiving means for receiving a propagated digital modulation signal, an equalizing means for reducing signal distortion in the received signal, and a demodulating means for demodulating the received signal by differential detection. A signal whose signal distortion has been reduced by the equalizer is demodulated by the demodulator, or a received signal is demodulated by the demodulator without passing through the equalizer based on predetermined conditions. A switching unit for selectively switching, a power supply unit for supplying power to the equalization unit, and the demodulation unit does not demodulate a signal whose signal distortion has been reduced by the equalization unit. Control means for controlling the supply of power to the equalization means by the power supply means to be stopped. 6. The digital radio communication apparatus according to claim 5, wherein said equalizing means is constituted by a CMOS logic element. 7. A digital radio communication device according to claim 5, wherein the digital modulation signal is a signal transmitted by a time division multiplex system. 8. The switching means, when receiving at least a signal in a slot period other than the one addressed to itself, switches so that a received signal is demodulated by the demodulation means without passing through the equalization means. Claim (7)
Digital radio communication equipment. 9. A receiving means for receiving a digital modulation signal propagated by a time division multiplex system, an equalizing means for reducing signal distortion in the received signal, and a means for demodulating the received signal by differential detection. Demodulation means, according to the received electric field strength detected by the detection means,
The signal whose signal distortion has been reduced by the equalizing means is demodulated, or the switching control is selectively performed so that the received signal is demodulated by the demodulating means without passing through the equalizing means. And control means for setting the signal to be demodulated by the demodulation means without passing through the equalization means when receiving the signal of the slot period.