JP3017160B2 - Over-input protection circuit of receiving amplifier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a base station receiving amplifier used in a mobile communication system, and more particularly to an FET amplifying element (hereinafter abbreviated as FET) used as a first stage of a receiving amplifier. The present invention relates to a means for preventing an FET from being damaged due to an excessive reception signal reaching a gate.

[0002]

2. Description of the Related Art Conventionally, a base station receiving amplifier used in a mobile communication system is premised on receiving and amplifying a transmission wave emitted from a mobile terminal of a specific system. Since the transmission wave power, that is, the reception signal level can be controlled to an appropriate value, no protection circuit or the like for an excessive input has been provided.

[0003]

However, in a mobile communication system using, for example, an 800 MHz band, since a plurality of mobile systems operate in adjacent frequency bands, the frequency permitted by a reception filter or the like is used. Although the band is limited to receive only the band, this receiving filter does not allow sharp band limitation, and the receiving amplifier is generally designed for a wide band, so that it cannot be used for other systems. A problem occurs that a transmission wave from a mobile terminal is erroneously received and amplified.

However, since a transmission wave from a mobile terminal of another system cannot be controlled by the own system, it is input to the receiving amplifier of the own system as an excessively high level reception signal, and the receiving amplifier of the own system is used. There was a problem of causing damage.

An object of the present invention is to provide a base station receiving amplifier for solving the above problems.

[0006]

SUMMARY OF THE INVENTION According to the present invention, a reception signal reaching a gate of an FET used in a first stage of a receiving amplifier is delayed for a predetermined time, and during the predetermined delay time, a signal of the first stage FET is delayed. By automatically controlling the gate voltage value, for example, even when the total power of the received signals from a plurality of mobile communication systems reaches a value exceeding the allowable input value of the receiving amplifier, the first-stage FET can be used. It is characterized in that it is not damaged.

More specifically, a received signal input from the input terminal of the receiving amplifier is input to a delay unit, and is input to the gate of the first-stage FET with a delay of a delay time calculated in advance by the delay unit. The input reception signal is amplified and supplied to an output terminal.

On the other hand, a part of the received signal input from the input terminal is input to the detection unit, converted into a detection voltage, and output to the switching unit. In the switching unit, the detection voltage is constantly compared with the reference voltage.If the received signal is equal to or less than the allowable value, the detection voltage value is small, so the reference signal output from the switching unit is equal to the reference voltage. A bias voltage is supplied from the control unit to the gate of the first-stage FET so that the drain voltage (ie, the drain current) is calculated in advance, and a stable constant current operation state is achieved.

When an excessively high received signal exceeding the allowable value is input, the reference signal output from the switching unit is switched to the detection voltage, so that the gate voltage of the first-stage FET is stabilized by the comparison control unit. By changing the value to a value larger than the state value, the operating point of the FET is changed (the gate bias is made more negative). At this time, the excessive-level reception signal is delayed by the delay unit and reaches the first-stage FET.Therefore, when the excessive-level reception signal is input to the gate of the first-stage FET, the operating point of the FET has already been changed. The FET is not damaged even if an excessive level of the received signal is input.

[0010]

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, a received signal input from an input terminal 1 is transmitted to a delay unit 3,
Part of the received signal is input to the detection unit 2 and detected, converted into a detection voltage 8 which is a DC voltage, and output to the switching unit 9.

The detection section 2 can be realized using, for example, a general CM coupler as shown in FIG.
That is, one end of the coupling pattern is connected to the terminating resistor 10.
1 and a part of the received signal induced at the other end is rectified by the detection diode 102, and the rectified current is
4 to generate an arbitrary DC voltage. A speed-up capacitor 103 is connected in parallel with the detection diode 102 to quickly adapt the detection output to the rise of the received signal, and a smoothing capacitor 105 is inserted to smooth the rectified current.

As the detection diode 102, a diode having a short turn-on time, that is, a diode capable of quickly adapting (detecting) without delaying the rise of a received signal is used.

The delay unit 3 has a delay time calculated in advance, and the received signal is input to the gate of the FET 5 via the input capacitor 4 inserted for DC cut with a delay of the delay time. You. As the delay unit 3, for example, a delay line LDH46A1 manufactured by Murata Manufacturing Co., Ltd.
03C (catalog name, chip component, issued in September 1997). By connecting a plurality of the delay lines in series, an arbitrary delay time can be easily set.

The applied + V is applied to the drain of the FET5.
A drain voltage 14, which is reduced by a voltage drop generated by a drain current calculated in advance by a voltage feedback resistor 13 from a voltage, is applied. Therefore, the input received signal is supplied to the output terminal 7 via the output capacitor 6 which is amplified by the FET 5 and inserted for DC cut. The drain voltage 14 is also used as a control signal, and is input to the plus terminal of the comparison control unit 12.

As shown in FIG. 3, the switching section 9 can be realized by a logical sum of a combination of a first diode 201 and a second diode 203. The speed-up capacitor 202 is inserted in order to quickly adapt to and transmit the sudden rise of the detection voltage 8. Furthermore, by using a diode having a short turn-on time as the first diode 201, it is possible to realize an output response characteristic with a small time delay of the output voltage with respect to a change in the input voltage.

The comparison control unit 12 constantly compares the reference signal 11 with the drain voltage 14, generates a gate voltage 15 by DC-amplifying the difference between the two, and applies the gate voltage 15 to the gate of the FET 5. The comparison control unit 12 can be realized by using a DC amplifier circuit using a general operational amplifier as shown in FIG. That is, the first input resistance 301
(Resistance value R ₃₀₁ ), second input resistor 302 (resistance value R ₃₀₂ ), feedback resistor 304 (resistance value R ₃₀₄ ), and operational amplifier 303.

Assuming that the potential difference between the minus input terminal and the plus input terminal of the comparison control unit 12 is ΔV, the output terminal 15
Output voltage V _G of, the V _G = direct current amplification gain × [Delta] V. The DC amplification gain is given by R ₃₀₄ / R ₃₀₂ , and this DC amplification gain is generally set to 100 or more.

As the operational amplifier 303, ANALOG
DEVICES AD8047 (catalog name 19
97 SHORT FORM DESIGNERS'G
Slew rate (listed in UIDE)
Rate; a unit having a high unit of V / μS) realizes an output response characteristic in which a time delay of an output voltage appearing at an output terminal is small with respect to a rapid change in a potential difference (ΔV) between input terminals. be able to.

Normally, when the total power of the received signal is equal to or less than the allowable value, the reference voltage 10 having a constant value is selected as the reference signal 11 input from the switching unit 9 to the comparison control unit 12, and is calculated in advance. Since the gate voltage 15 is set so as to be the drain voltage (that is, the drain current), the FET 5 is controlled to be in a stable constant current operation state. Therefore, in such a stable state, the received signal input to the FET 5 is amplified at a high frequency by a gain calculated in advance and supplied to the output terminal 7.

In such a constant current operation state, since the comparison control section 12 is in a balanced state, if the DC amplification gain is 100 or more, ΔV is almost zero.

On the other hand, when a received signal of an excessive level exceeding the allowable value is input, the switching unit 9 sends the comparison control unit 12
Since the detection voltage 8 is selected as the reference signal 11 to be inputted to the reference signal 11, the reference signal 11 has a value larger than the reference voltage 10. Is supplied (a large negative voltage), and the operating point of the FET 5 is changed so that its drain current becomes almost zero.

Thereafter, the excessively high level of the received signal delayed by the delay unit 3 is input to the gate electrode of the FET 5, but the operating point (bias) of the FET 5 has already been changed to correspond to the excessive input. Therefore, even if an excessive input voltage is applied, the FET 5 is not destroyed.

Next, with reference to FIG. 5, how the operating state of the FET 5 changes depending on the level of the received signal input to the input terminal 1 will be described. In FIG. 5, the horizontal axis is the gate-source voltage (VGS) of FET5.
, And the vertical axis indicates the drain current (ID). (A) and (A ') show the case where the received signal level is low, and (B) and (B') and (C) and (C ') show the case where the received signal level is high.

(A) and (B) show how the VGS changes in an alternating manner when a received signal is input with an arbitrary VGS (minus voltage) as the center voltage.
(B) and (B ') show how the ID changes AC as the VGS changes AC.

When the level of the received signal is low, the FET
Reference numeral 5 indicates that normal amplification is performed to perform the operations shown in (A) and (A '). On the other hand, when an excessively high level reception signal as shown in (B) is input to the FET 5, a part of the positive amplitude of the reception signal exceeds the zero potential of the VGS, so that the instantaneous potential of the VGS becomes a positive potential. . Accordingly, an infinite current tends to flow as the ID, but the ID is suppressed by the voltage feedback by the voltage feedback resistor 13, and at the same time, a distorted waveform such as (B ') is obtained.

Generally, an FET (GaAs FET, MO
In the case of an SFET or the like, when VGS becomes a positive potential, not only the ID increases but also a current flows between the gate and the source (GS) (shaded portion in FIG. 5). During the operation, that is, the FET is damaged. Therefore, when a received signal of an excessive level exceeding the allowable current value between G and S is input, VGS is set to a large negative voltage as shown in (C) and (C ') of FIG. Is changed, the current flowing between G and S can be completely eliminated, so that damage between G and S can be avoided.

FIG. 6 shows the characteristics of the received signal level of the detection unit 2 versus the detection voltage 8. FET5 when operating at constant current
Is the received signal level at which Px is damaged, and the detection voltage 8 at that time
Is Vx. The reference voltage 10 is set to a value slightly smaller than Vx, and when the received signal level is low, the + V voltage value and the voltage feedback resistor 13 are set in advance so that a constant current circuit for obtaining a desired ID is formed. Select a value.

For example, when an excessively high level reception signal is input to the input terminal 1 and the detection voltage 8 exceeds the reference voltage 10, the switching unit 9 cuts off the reference voltage 10 and turns off the reference signal 1.
The detection voltage 8 is selected as 1 and supplied to the comparison control unit 12. Therefore, the voltage difference between the reference signal 11 and the drain voltage 14 (Δ
V) was almost zero, but the balance was lost due to an excessive input, so that the comparison control unit 12 DC-amplifies (inverted amplifies) the difference (ΔV) between the two. (The same voltage as the negative power supply applied to the power supply 303). In this state, F
Although the high-frequency amplification function of the ET5 is stopped, there is no problem because it is already in an abnormal state.

On the other hand, the delay unit 3 has a delay time longer than the time until the detection unit 2 detects an excessive input, the switching unit 9 performs a switching process, and the comparison amplification unit 12 controls the gate voltage 15 to a large negative voltage. Is set to prevent the reception signal of an excessive level from being input to the FET 5 until the gate voltage 15 is controlled. When an excessively high level of the received signal is input, the gate voltage 15 is controlled before the excessively high level of the received signal reaches the FET 5, thereby preventing the FET 5 from being damaged.

[0030]

According to the present invention, a delay unit delays the time of reaching an FET when an excessively high level of a received signal is input, and controls the gate voltage of the FET to a large value in the minus direction within the delay time. Since the high-frequency current flowing between the gate and the source of the FET can be completely eliminated, even if an excessively high level of the received signal is input, it is possible to avoid damage to the amplifier (FET), particularly the first-stage amplifying element (FET) constituting the receiving amplifier. .

Also, since the circuit configuration is combined with a general constant current circuit, it is simple and can be realized at low cost.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration example of a detection unit 2 in FIG. 1;

FIG. 3 is a diagram illustrating a configuration example of a switching unit 9 in FIG. 1;

FIG. 4 is a diagram illustrating a configuration example of a comparison control unit 12 in FIG. 1;

FIG. 5 is a diagram for explaining the operation of the present invention.

FIG. 6 is a diagram for explaining the operation of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input terminal 2 Detection part 3 Delay part 4 Input capacitor 5 FET 6 Output capacitor 7 Output terminal 8 Detection voltage 9 Switching part 10 Reference voltage 11 Reference signal 12 Comparison control part 13 Resistance for voltage feedback 14 Drain voltage 15 Gate voltage 101 Termination resistance 102 Detection diode 103, 202 Speed-up capacitor 104 Load resistance 105 Smoothing capacitor 201, 203 Diode 301, 302 Resistance 303 Operational amplifier 304 Feedback resistance

Claims (5)

(57) [Claims] 1. A control for using a FET as a first stage of a receiving amplifier and supplying a DC voltage that changes according to the receiving input level as a gate bias voltage of the FET when a receiving input signal of a predetermined level or more is input. over the circuit and the receiving amplifier comprising a delay unit for the received input signal is delayed more than the response time of the control circuit outputs to the FET
In the input protection circuit, the control circuit detects a part of the received input signal.
Wave part, and the detection voltage output from the detection part
The set reference voltage is input and the larger voltage is
A switching unit that outputs a control signal,
FET drain voltage is input and according to the potential difference
Output voltage as a bias voltage to the gate of the FET.
And a comparison control unit to be supplied.
Over-protection circuit of the receiving amplifier . 2. The detecting section is terminated at one end with a terminating resistor.
And rectifies part of the received signal induced at the other end.
A coupler to which a wave diode is connected and the rectified detector.
And a smoothing capacitor for smoothing the wave output.
2. The over-input protection circuit for a receiving amplifier according to claim 1, wherein: 3. The switching unit according to claim 2, wherein the switching unit detects the detected voltage and the reference voltage.
It is composed of a logical sum circuit that inputs voltage and
2. The over-input protection of the receiving amplifier according to claim 1, wherein
Protection circuit . 4. The comparison control unit is connected to a minus input terminal.
The control signal is input via a first input resistor, and
The drain voltage via a second input resistor to the
Is input and feedback is provided between the output terminal and the positive input terminal.
Consisting of an operational amplifier connected to a resistor
2. The over-input protection of the receiving amplifier according to claim 1, wherein
Circuit . 5. The mobile communication system according to claim 5, wherein said receiving amplifier is a mobile communication system.
It is a base station receiving amplifier used for
2. The over-input protection circuit for a receiving amplifier according to claim 1, wherein: