JP3012609B1 - Phase locked loop circuit - Google Patents

Abstract

Kind Code: A1 Provided is a PLL circuit which locks up at high speed and consumes low power. A voltage controlled oscillator, a frequency divider for dividing the output of the voltage controlled oscillator, a reference frequency generator, and a phase for comparing the output of the reference frequency generator with the output of the frequency divider A phase-locked loop circuit having a comparator and a phase difference voltage conversion circuit including a charge pump and a low-pass filter for converting a phase difference signal output from the phase comparator into a control voltage of the voltage controlled oscillator; Means for comparing the phase difference obtained from the output of the detector with a reference value to determine the magnitude of the phase difference, and means for changing a power supply voltage supplied to the phase comparator and the charge pump based on the determination result. Provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit, and operates at a low voltage of, for example, about 1.5 to 3 V, which is mainly used for a digital tuning system used in a portable radio. The present invention relates to a phase locked loop circuit.

[0002]

2. Description of the Related Art Conventionally, in a phase locked loop circuit (hereinafter, referred to as a PLL circuit) used in a digital tuning system used in a portable radio or the like, a power supply voltage is low because a battery is used as a power supply. There is a problem that the variable range of the applied control voltage is narrowed and the frequency variable range cannot be widened. Therefore, in order to improve the characteristics of a PLL circuit that operates at a low voltage using a battery as a power source, a technique of changing a voltage supplied to some of the components of the PLL circuit to another voltage has been used.

For example, Japanese Patent Application Laid-Open No. 1-120132 discloses a technique for increasing the frequency variable range of a radio receiver by boosting a power supply voltage and supplying it to a charge pump circuit in a PLL circuit. . Further, Japanese Unexamined Patent Publication No.
Japanese Patent Application Laid-Open No. 162951 discloses that in a PLL circuit used in a portable wireless device, a charge pump and a voltage controlled oscillator are supplied with a boosted battery voltage to prevent a deterioration of a C / N value, and are provided to a phase comparator and a frequency divider. Describes a technique for suppressing power consumption of the entire PLL circuit by supplying a power supply voltage with a reduced battery voltage. The C / N value is a value indicating the ratio between the output frequency of the voltage controlled oscillator and the noise.

[0004]

However, the prior art has the following problems. First, if the power supply voltage supplied to the charge pump is increased for the purpose of expanding the frequency variable range of the PLL circuit and achieving high-speed lock-up, the current consumption is increased and the battery is quickly consumed, and the charge pump itself is connected to peripheral circuits. It becomes a noise generation source, causing malfunction and deterioration of the C / N value.

If the power supply voltage supplied to the phase comparator is reduced for the purpose of reducing power consumption, a delay occurs when the phase difference signal is generated, which delays the reaction, and the voltage of the phase difference signal itself is low. Therefore, a delay occurs in driving the charge pump, and as a result, it takes time to lock up the PLL.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems by providing a charge pump having a wide frequency variable range, low power consumption and low noise, and a phase comparator having low power consumption and quick response and having a large charge pump driving capability. Accordingly, it is an object of the present invention to provide a PLL circuit which locks up at high speed and consumes low power.

[0007]

According to one embodiment of the present invention, there is provided a voltage controlled oscillator, a frequency divider for dividing the output of the voltage controlled oscillator, and
A reference frequency generator, a phase comparator that compares the phase of the output of the reference frequency generator with the phase of the output of the frequency divider, and converts a phase difference signal output from the phase comparator into a control voltage of the voltage controlled oscillator. A phase locked loop circuit having a charge pump and a phase difference voltage conversion circuit comprising a low-pass filter, wherein the phase difference obtained from the output of the phase comparator is compared with a reference value to determine the magnitude of the phase difference. Means for increasing the power supply voltage to be supplied to the phase comparator and the charge pump based on the power supply voltage (Vcc) before voltage conversion based on the determination result when the phase difference is large and decreasing the power supply voltage when the phase difference is small. Is provided.

When the low-pass filter of the PLL circuit is constituted by an active filter, the power supply voltage of the active low-pass filter is not limited to the power supply voltage (Vcc ) As a reference, a PLL circuit is provided which is supplied from means for increasing the voltage when the phase difference is large and decreasing the voltage when the phase difference is small.

The means for determining the magnitude of the phase difference includes an exclusive OR circuit that receives the phase difference signal output from the phase comparator, and a smoothing circuit that smoothes the output signal of the exclusive OR circuit. A reference voltage generation circuit that sets a reference value of the phase difference, a voltage comparator that compares the output voltage of the reference voltage generation circuit with the output voltage of the smoothing circuit to determine the magnitude,
And a voltage switch that captures, holds, and outputs the output signal of the voltage comparator using the output signal of the exclusive OR circuit.

[0010] The power supply voltage is converted to a power supply voltage (V
cc), the means for increasing the phase difference when the phase difference is large and decreasing the voltage when the phase difference is small are a booster circuit and a step-down circuit which output a DC voltage, and a signal output from a means for determining the magnitude of the phase difference. And a selection circuit for selecting the step-down circuit when the phase difference is small and the step-down circuit when the phase difference is small.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a PLL circuit according to a first embodiment of the present invention.
8, a frequency divider 102, a reference frequency generator 101, a phase comparator 103, a charge pump 104, a low-pass filter 107, a phase difference width detection circuit 105, and a voltage conversion circuit 106. I have. in this case,
The phase comparator 103 has two input terminals and two output terminals, one input terminal is connected to the output terminal of the reference frequency generator 101, and the other input terminal of the voltage controlled oscillator 108. The output terminal of the frequency divider 102 for dividing the output is connected. Further, two input terminals of the charge pump 104 and two input terminals of the phase difference width detection circuit 105 are connected to two output terminals of the phase comparator 103, respectively. Further, the charge pump 104 has two input terminals and one output terminal. The output terminal is connected to the input terminal of the low-pass filter 107. The output terminal of the low-pass filter 107 is
08, and the output terminal of the voltage controlled oscillator 108 is connected to the input terminal of the frequency divider 102. The output terminal of the phase difference width detection circuit 105 is connected to the input terminal of the voltage conversion circuit 106. The output terminal of the voltage conversion circuit 106 is connected to the power supply terminals of the phase comparator 103 and the charge pump 104. Further, a voltage controlled oscillator 108, a frequency divider 102, a reference frequency generator 101, a phase difference width detection circuit 105, a voltage conversion circuit 1
06 is supplied with the power supply voltage Vcc.

Next, the operation of the PLL circuit according to the first embodiment will be described with reference to FIG. The frequency of the reference frequency fr output from the reference frequency generator 101 and the output signal of the voltage controlled oscillator 108 are divided by the phase comparator 103 and the frequency divider 10
When the frequency division frequency fn output from 2 is input, the phase comparator 103 outputs an up signal UP (hereinafter, referred to as UP) and a down signal DOWN (hereinafter, referred to as DOWN), which are phase difference signals of these two signals. ) Is output to the charge pump 104 and the phase difference width detection circuit 105. The phase difference signals UP and DOWN are converted into a signal voltage corresponding to the phase difference by the charge pump 104 and the low-pass filter 107 and input to the voltage control oscillator 108. Then, the voltage controlled oscillator 108 outputs a signal having a frequency proportional to the input signal voltage to the frequency divider 102, and the frequency divider 102 divides the frequency of the input signal and outputs the resultant signal to the phase comparator 103. In this way, the loop frequency is repeated, and the divided frequency fn output from the frequency divider 102 becomes closer to the reference frequency fr.

Here, the divided frequency fn is equal to the reference frequency fr.
When the voltage is lower, the phase comparator 103 outputs a phase difference signal that passes through the charge pump 104 and the low-pass filter 107 and is supplied with a higher control voltage by the voltage-controlled oscillator 108, whereby the voltage control is performed. The frequency of the signal output from the oscillator 108 to the frequency divider 102 increases, and the frequency of the frequency fn output from the frequency divider 102 increases.
Becomes closer to the reference frequency fr.

Conversely, when the divided frequency fn is higher than the reference frequency fr, the phase comparator 103 passes through the charge pump 104 and the low-pass filter 107, and a voltage at which a low control voltage is input to the voltage controlled oscillator 108. The phase difference signal is output, and the frequency division frequency fn output from the frequency divider 102 operates so as to be closer to the reference frequency fr.

In the PLL circuit operating as described above, the phase difference width detection circuit 105 constantly monitors the phase difference signals UP and DOWN output from the phase comparator 103, compares the phase difference with the reference value, and compares the phase difference signal with the reference value. Judge the magnitude of the difference,
A signal indicating an output voltage is output to voltage conversion circuit 106. The voltage conversion circuit 106 uses the signal from the phase difference width detection circuit 105 to
04 is changed. That is, the phase difference width detection circuit 105 functions as a unit that determines the magnitude of the phase difference, and the voltage conversion circuit 106 functions as a unit that changes the power supply voltage.

When the phase difference is equal to or larger than the reference value, the phase difference width detection circuit 105 outputs a signal for increasing the voltage to the voltage conversion circuit 106. As a result, the power supply voltage supplied from the voltage conversion circuit 106 to the phase comparator 103 and the charge pump 104 increases, and the frequency division frequency fn output from the frequency divider 102 can be locked up to the reference frequency fr more quickly. become.

On the other hand, when the reference frequency fr is substantially the same as the divided frequency fn, the phase difference is smaller than the reference value, so that the phase difference width detection circuit 105 outputs a signal for decreasing the voltage to the voltage conversion circuit 106. . Thereby, the voltage conversion circuit 10
From 6, the power supply voltage supplied to the phase comparator 103 and the charge pump 104 becomes lower, and the power consumption can be reduced.

That is, according to the present invention, when the phase difference is large, the power supply voltage supplied to the phase comparator and the charge pump is boosted to improve the operation speed of the phase comparator and the charge pump driving capability and the frequency of the voltage controlled oscillator. When the phase difference after lock-up is small, the power supply voltage supplied to the phase comparator and the charge pump is reduced to reduce the power consumption of the phase comparator and the charge pump, and reduce the noise of the charge pump. Reduction,
This provides a PLL circuit with high-speed lock-up and low power consumption.

FIG. 2 shows a second embodiment of the PLL circuit of the present invention. In FIG. 2, the same reference numerals as those in FIG. 1 denote the same parts. This PLL circuit differs from that shown in FIG. 1 in that the low-pass filter is constituted by an active filter,
That is, the DC voltage of the voltage conversion circuit 106 is supplied as the power supply voltage of the active low-pass filter 109.

Next, the operation of the PLL circuit shown in FIG. 2 which is different from that shown in FIG. 1 will be described. The operation of the PLL circuit shown in FIG. 2 is different from that shown in FIG. 1 in that the boosted power supply voltage when the phase difference is equal to or more than the reference value, and the lowered power supply voltage when the phase difference is less than the reference value, This is to be supplied to the phase comparator 103, the charge pump 104, and the active low-pass filter 109. This is because, when the low-pass filter is constituted by an active filter, the control voltage of the voltage controlled oscillator 108 is changed to the active low-pass filter.
This is because when the power supply voltage of the charge pump 104 is changed, the power supply voltage of the active low-pass filter 109 must be changed at the same time because the power supply voltage of the filter 109 does not exceed the power supply voltage of the filter 109. Thus, even when the low-pass filter is formed of an active filter, high-speed lock-up is realized when the phase difference is large, and low power consumption is achieved when the phase difference after lock-up is small, as in the first embodiment. And noise reduction.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a PLL circuit according to the present invention will be described below. The configuration of the present embodiment is as shown in FIG. 2 described above. The reference frequency generator, the frequency divider, the phase comparator, the charge pump, the active low-pass filter, and the voltage controlled oscillator have a circuit configuration conventionally used in a PLL circuit. Next, the power supply voltage is changed,
A phase comparator, a charge pump, an active low-pass filter, and a phase difference width detection circuit and a voltage conversion circuit for controlling these power supply voltages will be described.

FIG. 3 shows a phase comparator. Hereinafter, the phase comparator will be described. The phase comparator 103 includes NAND circuits 231 to 239. And NAND
The input of the circuit 231 has a reference frequency input terminal 218 and an NA.
The output of the ND circuit 238, the output of the NAND circuit 231 and the output of the NAND circuit 233 at the input of the NAND circuit 232, the output of the NAND circuit 232 and the output of the NAND circuit 237 at the input of the NAND circuit 233, Each is connected. The input of the NAND circuit 236 includes the frequency-divided frequency input terminal 219 and the output of the NAND circuit 239, and the input of the NAND circuit 235 includes the NAND circuit 2
34 and the output of NAND circuit 236 are NAND
The input of the circuit 234 and the output of the NAND circuit 235 and the NA
The outputs of the ND circuits 237 are connected to each other.

Further, the input of the NAND circuit 237 is N
The output of the AND circuit 231, the output of the NAND circuit 232, the output of the NAND circuit 235, and the output of the NAND circuit 236 are input to the input of the NAND circuit 238.
1 and the output of NAND circuit 232 and NAND circuit 2
37 and the input of the NAND circuit 239 is NAN.
Output of D circuit 236, output of NAND circuit 235 and NA
The outputs of the ND circuits 237 are connected to each other.
The output of the NAND circuit 238 is supplied to the up signal terminal 201, and the NAND circuit 239 is supplied to the down signal terminal 202.
Output is connected. In addition, the NAND circuit 2 is connected from the voltage conversion circuit 106 through the phase comparator power supply terminal 211.
A power supply voltage is supplied to 31 to 239.

FIG. 4 shows a charge pump. Hereinafter, the charge pump will be described. Charge pump 104
Are the inverter 221 and the N-channel transistor 222
And a P-channel transistor 223. The up signal terminal 201 is connected to the inverter 221.
, The output of the inverter 221 is at the gate of the N-channel transistor 222, the down signal terminal 202 is at the gate of the P-channel transistor 223, the charge pump power supply terminal 212 is at the source of the P-channel transistor 223, Drain is N
The source of the channel transistor 222 and the drain of the N-channel transistor 222 are connected to the ground, respectively, so that an output is taken out between the drain of the P-channel transistor 223 and the source of the N-channel transistor 222. The voltage conversion circuit 10
6, a power supply voltage is supplied to the source of the P-channel transistor 223 and the inverter 221 through the charge pump power supply terminal 212.

FIG. 4 shows an active low-pass filter. Hereinafter, the active low-pass filter will be described. The active low-pass filter 109 includes the inverter 225 and the resistor 2
26, 227 and a capacitor 228. Then, the output of the charge pump 104 is
To the input of the inverter 225, the output of the inverter 225 to the low-pass filter output terminal 217 and the capacitor 228, the capacitor 228 to the resistor 227, and the resistor 22
7 are connected to the inputs of the inverter 225, respectively. Further, a power supply voltage is supplied from the voltage conversion circuit 106 to the inverter 225 through the power supply terminal 213 for the active low-pass filter.

FIG. 5 shows a phase difference width detecting circuit. Hereinafter, the phase difference width detection circuit will be described. Phase difference width detection circuit 1
Reference numeral 05 denotes an exclusive OR circuit 203 (hereinafter, referred to as an EX-OR circuit), a smoothing circuit 204, and a reference voltage generating circuit 20.
6, a voltage comparator 205, a voltage switch 207 and an inverter 208. Then, the up signal terminal 201 and the down signal terminal 2 of the phase comparator 103
02 is connected to the input side of the EX-OR circuit 203,
The output side of the OR circuit 203 is connected to the input side of the smoothing circuit 204; Further, the output side of the smoothing circuit 204 and the output side of the reference voltage generation circuit 206 are connected to the voltage comparator 2.
05, and the output side of the voltage comparator 205 and the output side of the EX-OR circuit 203 are connected to the voltage switch 2
07, and the output side of the voltage switch 207 is connected to the voltage conversion circuit 106. The power supply voltage Vcc is supplied to the EX-OR circuit 203, the smoothing circuit 204, the voltage comparator 205, the reference voltage generation circuit 206, and the voltage switch 207 through the power supply terminal 200 for the phase difference width detection circuit.

FIG. 5 shows a voltage conversion circuit. Hereinafter, the voltage conversion circuit will be described. The voltage conversion circuit 106 includes an inverter 208, a boost circuit 209, and a step-down circuit 210. Then, the phase difference width detection circuit 105
Is output to the booster circuit 209 via the inverter 208, and the other is directly branched to the step-down circuit 210 via the inverter 208.
Connected to Further, the output side of the booster circuit 209 and the output side of the step-down circuit 210 are connected to the phase comparator power supply terminal 2.
11, a charge pump power supply terminal 212 and an active low-pass filter power supply terminal 213. The power supply voltage Vcc is supplied to the inverter 208, the booster circuit 209, and the step-down circuit 210 through the power supply terminal 214 for the voltage conversion circuit.

Next, the operation of the PLL circuit in this embodiment will be described. In this embodiment, the reference frequency generator 101, the voltage controlled oscillator 108, the frequency divider 102, the phase comparator 103,
Charge pump 104 and active low-pass filter 1
The operation of the phase-locked loop consisting of 07 is as described in the embodiment of the present invention.

Next, the operation of the phase difference width detection circuit 105 and the voltage conversion circuit 106 will be described with reference to FIGS. FIG.
Is the reference frequency fr of the reference frequency generator 101 and the frequency divider 1
FIG. 7 is a waveform diagram when the phase difference of the divided frequency fn of No. 02 is equal to or larger than the reference value, and FIG. 7 is a waveform diagram when the phase difference is smaller than the reference value. The waveforms of the output of the circuit 203, the input and output of the voltage comparator 205, and the outputs of the voltage switch 207 and the voltage conversion circuit 106 are shown. Here, the phase difference signal UP and DOWN output from the phase comparator 103 are both normally HIGH and are LOW when active, and the phase of the divided frequency fn is delayed from the phase of the reference frequency fr. When UP, the UP changes according to the phase difference, and DOWN is held HIGH. When the phase of the divided frequency fn is ahead of the phase of the reference frequency fr, DOWN changes in accordance with the phase difference, and UP is held at HIGH. Note that the phase difference is 0
At this time, both UP and DOWN are held HIGH.

Next, the operation when the phase difference is large will be described with reference to FIG. When the reference frequency fr shown in FIG. 6A and the divided frequency fn shown in FIG. 6B are input to the phase comparator 103, the phase difference signal UP shown in FIG.
DOWN shown in (d) is output, and the phase difference width detection circuit 1
05 is input to the EX-OR circuit 203. Here, since the phase of the divided frequency fn is ahead of the phase of the reference frequency fr, UP changes according to the phase difference, and DOWN becomes H
It is held at IGH. Therefore, the EX-OR circuit 20
As shown in FIG. 6 (e), the output signal from
When it becomes W, it becomes HIGH. Therefore, FIG.
The output signal of the EX-OR circuit 203 shown in FIG.
After smoothing at 04, as shown at 204a in FIG. 6 (f), it is input to the voltage comparator 205 and
The output voltage of the reference voltage generation circuit 206 indicated by reference numeral 06 a is used as the other input of the voltage comparator 205. By the way, the voltage comparator 205 outputs the output voltage 2 of the reference voltage generation circuit 206.
When the output voltage 204a of the smoothing circuit 204 is higher or the same as the output voltage 06a, HIGH is output, and when the output voltage 204a is lower, LOW is output. Therefore, an output signal as shown in FIG. The voltage switch 207 is connected to the output signal of the voltage comparator 205 shown in FIG.
The output signal of the EX-OR circuit 203 shown in (e) is input and the output signal of the voltage comparator 205 is output to the EX-OR circuit 20.
The signal shown in FIG. 6H is output to the voltage conversion circuit 106 while being held at the down edge of the output signal of No. 3.

On the other hand, both the booster circuit 209 and the step-down circuit 210 in the voltage conversion circuit 106 perform voltage conversion with a LOW signal and output a DC voltage, and stop output with a HIGH signal. Here, since the inverter 208 inverts the output signal of the phase difference width detection circuit 105 and outputs the inverted signal to the booster circuit 209, when the output signal of the phase difference width detection circuit 105 is HIGH, the booster circuit 209 outputs a DC voltage. However, when LOW, the step-down circuit 210 outputs a DC voltage. Therefore, when the signal shown in FIG. 6H is input to the voltage conversion circuit 106, the power supply voltage shown in FIG. 6I is supplied to the phase comparator 103, the charge pump 104, and the active low-pass filter 109. Is done.

Next, the operation when the phase difference is small will be described with reference to FIG. When the reference frequency fr shown in FIG. 7A and the divided frequency fn shown in FIG. 7B are input to the phase comparator 103, the phase difference signal UP shown in FIG.
DOWN shown in (d) is output, and the phase difference width detection circuit 1
05 is input to the EX-OR circuit 203. Here, since the phase of the divided frequency fn is ahead of the phase of the reference frequency fr, UP changes according to the phase difference, and DOWN becomes H
It is held at IGH. Therefore, the EX-OR circuit 20
As shown in FIG. 7 (e), the output signal from
When it becomes W, it becomes HIGH. Therefore, FIG.
The output signal of the EX-OR circuit 203 shown in FIG.
After smoothing at 04, as shown at 204a in FIG. 7 (f), it is input to the voltage comparator 205 and
The output voltage of the reference voltage generation circuit 206 indicated by reference numeral 06 a is used as the other input of the voltage comparator 205. By the way, the voltage comparator 205 outputs the output voltage 2 of the reference voltage generation circuit 206.
When the output voltage 204a of the smoothing circuit 204 is higher or the same as that of the output voltage 06a, HIGH is output, and when the output voltage 204a is lower, LOW is output, so that the output signal shown in FIG.
07. The voltage switch 207 is as shown in FIG.
7 (e) and the output signal of the EX-OR circuit 203 shown in FIG. 7 (e), and the output signal of the voltage comparator 205 is held at the down edge of the output signal of the EX-OR circuit 203. Then, output is performed as shown in FIG.

As described earlier with reference to FIG. 6, when the signal shown in FIG.
The power supply voltage shown in FIG. 7I is supplied to the phase comparator 103, the charge pump 104, and the active low-pass filter 109.

Here, comparing FIG. 6 and FIG. 7, FIG. 6 shows that power is supplied by the booster circuit 209, whereas FIG. . Note that when the phase of the divided frequency fn is ahead of the phase of the reference frequency fr, the DOWN changes according to the phase difference, and the operation is the same as that described with reference to FIGS. 6 and 7 except that UP is held at HIGH. Perform the operation. When the phase difference is 0, both UP and DOWN are HIGH.
, The output signal of the EX-OR circuit 203 becomes LOW and falls below the reference value, so that the same operation as in FIG. 7 is performed. Therefore, according to the present embodiment, when the phase difference between the reference frequency fr of the reference frequency generator and the divided frequency fn of the frequency divider 102 is large, a voltage higher than the power supply voltage (Vcc) 215a is used. Voltage (Vcc) 21
A voltage lower than 5a can be used as a power supply voltage of the phase comparator 103, the charge pump 104, and the active low-pass filter 109.

By the way, since the lock-up time of the PLL circuit is generally designed to be about 10 msec, according to the present invention, most of the time can be achieved with a low voltage. In this embodiment, the power supply circuit voltage is 3 V, and the voltage of the booster circuit is 6
V, the voltage by the step-down circuit is 1.5 V, and the output voltage of the reference voltage generation circuit is 1.5 V. Therefore, when the power supply voltage is the same of 3V, the power consumption of the phase comparator and the charge pump can be reduced to about 1/4 of that of the fixed 3V.

[0036]

As described above, the PL according to the present invention is
The L circuit connects the power supply voltage of the phase comparator and the charge pump,
When the phase difference is equal to or larger than the reference value, the voltage is increased, and when the phase difference is smaller than the reference value, the voltage is decreased. As a result, the lock-up speed is increased when the phase difference is large, which requires high-speed lock-up or expansion of the frequency variable range. When the phase difference after lock-up is small, the noise of the charge pump can be reduced and the power consumption can be reduced. Thus, the effect that the conversion can be achieved can be obtained.

When the low-pass filter is composed of an active filter, the power supply voltage of the phase comparator, the charge pump, and the active low-pass filter is boosted when the phase difference is equal to or more than the reference value, and is smaller than the reference value. Sometimes has the function of stepping down. As a result, low-pass
Even for a PLL circuit in which the filter is formed of an active filter, a high-speed lock-up or an expansion of the frequency variable range is required. When the phase difference is large, the lock-up speed is high, and when the phase difference after lock-up is small, This has the effect of reducing noise of the charge pump and reducing power consumption.

That is, the PLL circuit according to the present invention has an excellent effect of increasing the speed of lock-up, expanding the frequency variable range, preventing malfunctions due to noise and deteriorating the C / N value, and realizing low power consumption. It has. As a result, a PLL that satisfies the required performance and responds to the prolonged battery usage time required for portable devices
A circuit can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a phase comparator in the embodiment.

FIG. 4 shows a charge pump and a low-pass filter according to the embodiment.
It is a circuit diagram of a filter.

FIG. 5 is a circuit diagram of a phase difference width detection circuit and a voltage conversion circuit in the embodiment.

6A and 6B are waveform diagrams when a phase difference between a reference frequency fr and a divided frequency fn is large, and FIG.
(B) is the divided frequency fn, (c) is the phase difference signal UP,
(D) is the phase difference signal DOWN, (e) is the output of the EX-OR circuit 203, (f) is the input of the voltage comparator 205,
(G) is the output of the voltage comparator 205, (h) is the output of the voltage switch 207, and (i) is the output of the voltage conversion circuit 106.

7A and 7B are waveform diagrams when the phase difference between the reference frequency fr and the divided frequency fn is small, and FIG.
(B) is the divided frequency fn, (c) is the phase difference signal UP,
(D) is the phase difference signal DOWN, (e) is the output of the EX-OR circuit 203, (f) is the input of the voltage comparator 205,
(G) is the output of the voltage comparator 205, (h) is the output of the voltage switch 207, and (i) is the output of the voltage conversion circuit 106.

[Explanation of symbols]

101: reference frequency generator, 102: frequency divider, 103:
Phase comparator 104 charge pump 105 phase difference detection circuit 106 voltage conversion circuit 107 low-pass filter 108 voltage-controlled oscillator 109 active low-pass filter 200 phase difference detection circuit Power supply terminal, 201: up signal terminal, 202: down signal terminal, 203: exclusive OR (EX-OR) circuit, 204
... Smoothing circuit, 204a ... Output voltage of smoothing circuit, 20
5: voltage comparator, 206: reference voltage generation circuit, 206a
Reference voltage, 207 Voltage switcher (flip-flop), 208, 221, 225 Inverter, 209
Step-up circuit, 210 ... Step-down circuit, 211 ... Power terminal for phase comparator, 212 ... Power terminal for charge pump, 213 ...
Power supply terminal for active low-pass filter, 214 power supply terminal for voltage conversion circuit, 215a power supply voltage (Vcc), 21
7: Low-pass filter output terminal, 218: Reference frequency input terminal, 219: Divided frequency input terminal, 222: N-channel transistor, 223: P-channel transistor, 226, 227: resistor, 228: capacitor, 23
1-239 ... NAND circuit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03L ^7/ 06-7/22

Claims (4)

(57) [Claims] 1. A voltage-controlled oscillator, a frequency divider for dividing the output of the voltage-controlled oscillator, a reference frequency generator, and comparing the phase of the output of the reference frequency generator with the phase of the output of the frequency divider. A phase locked loop circuit comprising: a phase comparator; and a phase difference voltage conversion circuit including a charge pump and a low-pass filter for converting a phase difference signal output from the phase comparator into a control voltage of the voltage controlled oscillator. Means for comparing the phase difference obtained from the output of the comparator with a reference value to determine the magnitude of the phase difference; based on the determination result, the power supply voltage supplied to the phase comparator and the charge pump before the voltage conversion Power-supply voltage
When the phase difference is large based on (Vcc), the voltage is boosted and the phase difference is increased.
A phase-locked loop circuit comprising: means for stepping down when small . Wherein said low-pass filter is an active filter, the low pass filter voltage the supply voltage
The phase difference is large based on the power supply voltage (Vcc) before conversion.
2. The phase-locked loop circuit according to claim 1, wherein a power supply voltage is supplied from a step-up means when the phase difference is small when the phase difference is small . 3. An exclusive OR circuit that receives the phase difference signal output from the phase comparator as an input, and smoothes an output signal of the exclusive OR circuit. A smoothing circuit, a reference voltage generating circuit for setting a reference value of the phase difference, a voltage comparator for comparing the output voltage of the reference voltage generating circuit with the output voltage of the smoothing circuit to determine the magnitude, 3. The phase-locked loop circuit according to claim 1, further comprising: a voltage switch that captures, holds, and outputs the output signal of the comparator using the output signal of the exclusive OR circuit. 4. A power supply voltage before a voltage conversion is performed on the power supply voltage.
When the phase difference is large based on (Vcc), the voltage is boosted and the phase difference is increased.
Means when the small to buck outputs a DC voltage, the booster circuit and the step-down circuit and, when the phase difference is large by signals output from the means for determining the magnitude of the phase difference position selecting the boost circuit 4. The phase-locked loop circuit according to claim 1, further comprising: a selection circuit that selects the step-down circuit when the phase difference is small.