JP3003120B2 - Storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device comprising a semiconductor integrated circuit for reading and writing data in word units.

[0002]

2. Description of the Related Art In a semiconductor memory widely used in various fields, a large number of memory cells are arranged in a matrix, and an address of one word of a memory cell is designated to read data in word units. And a device that performs a write operation. The designation of an address when reading and writing data in such a semiconductor memory is performed by supplying a predetermined address signal to word lines and bit lines arranged in a matrix corresponding to each memory cell. Therefore, if the same address signal is supplied, the same memory cell is always specified.

[0003]

In a conventional semiconductor memory, once data is stored in each memory cell, an address signal to be supplied and data read from a memory cell corresponding to the address are always unique one-to-one. Corresponding to Therefore, for example, if data stored in a certain memory cell is later found to be incorrect, the data must be read out once to an external register and new correct data must be stored again at a predetermined address. There is. In such a case, a method of adding an error correction code to the data and correcting the data in an error correction circuit is conceivable. However, this method requires a considerable amount of operation for error correction, and also requires a data redundancy. Has the disadvantage of requiring an extra storage capacity.

The present invention has been made based on the above circumstances, and reads out data corresponding to a certain address signal by replacing the data at another address in bit units, or writing data in another address in bit units. It is an object of the present invention to provide a storage device capable of performing such operations.

[0005]

SUMMARY OF THE INVENTION In order to achieve the above-mentioned object, the present invention provides a memory system in which a large number of memory cells are arranged in a matrix and an address signal is supplied to word lines and bit lines. In a memory device that reads and writes data in word units, a loop-shaped connection line provided between the array of memory cells in the bit direction and perpendicular to the word direction, and a connection between the connection line and the word line Switching means provided at each intersection position for switching signals between the word line and the connection line, and control means for controlling switching of all the switching means are provided. Here, the bit direction refers to a direction along the bit lines arranged in the matrix, and the word direction refers to a direction along a word line perpendicular to the bit lines.

[0006]

According to the present invention, when data once stored is read out, the data of the n-th bit in the first word address is replaced with the n-th bit of the second word address. Consider the case where data is to be replaced with the data on the bit line. First, the switching means at the intersection of the word line of the first word address and the loop-shaped connection line provided immediately before the arrangement of the memory cells in the bit direction, and the word line of the second word address The switching means at the intersection with the immediately preceding loop-shaped connection line is switched. As a result, the n-th bit data of the second word address is read as the n-th bit data of the first word address.

Next, switching means at the intersection of the word line of the first word address and the loop-shaped connection line provided immediately after the arrangement of the memory cells in the bit direction, and the second word address The switching means at the intersection of the word line and the immediately following loop-shaped connection line is switched. As a result, the data after the (n + 1) th bit of the first word address is read as it is as the data of the first word address. Therefore, even when an address signal designating the first word is supplied, only the n-th bit data of the first word address is read out instead of the n-th bit data of the second word address. .

The switching control of the switching means is performed by control means provided inside the storage device. In addition, a plurality of bit data can be exchanged and read out by the same operation. Further, the same operation is performed not only when reading data but also when writing data.

[0009]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a storage device according to one embodiment of the present invention, and shows a part of a large number of memory cells 8 arranged in a matrix. FIG. 2 is a circuit diagram showing a specific configuration of the switch (switching means) 16 provided in each section of FIG.

In FIG. 1, the bit direction and the word direction are
It is defined as shown by the arrow in the figure. 10 _j, 10_h, 10_i
Are word lines, which are the j-th word and the h-th word, respectively.
This is an address line for designating a word and an i-th word.
The bit line 12₁, 12_Two, 12_Three, ..., 12
_nSpecifies the array of memory cells 8 in the bit direction.
You. Furthermore, the arrangement and arrangement of memory cells in the bit direction
A loop connection line (hereinafter also referred to as a loop connection line)
You. ) 14₁, 14_Two, 14_Three, ..., 14_nBut
Line (parallel to the bit line)
A switch 16 is provided at the position where the connection line crosses the word line.
There is. The switching of these many switches 16 is the same.
Control signal decoding provided on a memory chip
Is controlled by the circuit 18 as described later.

As shown in FIG. 2, the switch 16 comprises four MOS transistors 30, 32, 34 and 36.
These form a pair of p-channel transistors and n-channel transistors to form two sets of CMOSs. A common control signal CNT is supplied to the gate of each transistor from the control signal decode circuit 18 described above.
Normally, this control signal CNT is 0 (Lo level) and p
Since the channel transistors 30 and 34 are on and the n-channel transistors 32 and 36 are off, the word line 10 goes from D to B and the loop connection line 14 goes to A.
To C. On the other hand, when the control signal CNT becomes 1 (Hi level), the operating states of the transistors are inverted, the p-channel transistors 30 and 34 are turned off, and the n-channel transistors 32 and 3 are turned off.
6 is turned on, D of the word line 10 is C of the loop connection line 14 and A of the loop connection line 14 is the word line 10.
B is connected. Thus, the control signal CN
The connection state between the word line 10 and the loop connection line 14 can be switched by T. Table 1 shows the relationship between the level of the control signal CNT and the connection state of the word line 10 and the loop connection line 14.

[0012]

[Table 1]

Returning to FIG. 1, when reading the data of the j-th word, only the data of the memory cell 8A of the second bit is replaced with the memory cell 8B of the second bit of the h-th word.
It is assumed that the data is read out by replacing the data. At this time, a control address signal for performing such replacement is supplied to the control signal decode circuit 18 from the outside, so that the control signal decode circuit 18
Decodes this control address signal and sends a predetermined control signal CNT to the switch 16 which needs to be switched.
Supply.

In this case, among the switches 16, the switches 16A, 16B, 16C, and 16D shown in FIG. 1 are subjected to the switching, and the switches 16A and 16B receive 1 as the control signal CNT, and the switches 16C and 16D receive the control signal CNT. 1 is supplied as CNT. As described in this time switch shown in FIG. 2, the switch 16A is loop connection line 1 disassociate the word line 10 _j from the memory cell 8A
4 connects _2, switch 16B connects the loop connection lines 14 ₂ to the memory cell 8B via the word line 10 _h. The switch 16C connects the word line _10h to the memory cell 8C.
And disassociate from the connected to the loop connection line 14 ₃ and around the loop connecting line 14 ₃ downwards reaches the switch 16D and the switch 16D is connected to the loop connection lines 14 ₃ in the memory cell 8D via the word line 10 _j I do. In this state, when an address signal designating reading of data stored in the j-th word is applied to the word line 10 _j , only the second bit of the j-th word is the memory cell of the second bit of the h-th word. The data stored in 8B is read.

The operation of replacing the memory cells is as follows.
For example, in the above example, it was discovered that the data stored in the memory cell 8A was erroneous,
This is particularly effective when the original correct data can be read as the j-th word by replacing the data stored in the j-th word. In this case, as long as the control address signal is given to the control signal decoding circuit 18 in advance, the necessary bits are replaced and read by adding the address signal designating the j-th word as it is. An operation for rewriting the entire data and a correction operation using an error correction code and an error correction circuit are not required.

Further, since the storage device of this embodiment can perform data manipulation in bit units, it can be used for image processing by intentionally switching memory cells in addition to correcting data errors. It can also be used for bitmap operations in memories and the like.

In this embodiment, only the case where data is read has been described. However, when writing data in word units, the same operation is performed to replace a specific bit with bit data of another word. Can write. This bit data exchange is 1
The number of bits is not limited, and a plurality of bits can be replaced at the same time.

[0018]

As described above, according to the present invention, a loop-shaped connection line is provided between memory cell arrays in the bit direction perpendicular to the word direction, and the loop-shaped connection line is connected to the word line. By providing the switching means at the position of the intersection with the line, when reading or writing data in word units, only data of a specific bit is replaced with the same bit data of another word by an external signal. Therefore, when there is wrong bit data in one word, it can be easily replaced with the correct data in another word, or apparent data shift in memory can be easily performed. A storage device can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a part of a large number of memory cells arranged in a matrix according to one embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific configuration of a switch provided in each unit of FIG.

[Explanation of symbols]

 2 Image sensor 8 Memory cell 10 Word line 12 Bit line 14 Loop connection line 16 Switch 18 Control signal decode circuit 30, 34 P-channel MOS transistor 32, 26 N-channel MOS transistor

Claims (1)

(57) [Claims] 1. A storage device in which a large number of memory cells are arranged in a matrix and read and write data in word units to said memory cells by supplying address signals to word lines and bit lines. A loop-shaped connection line provided between the array of memory cells in the direction perpendicular to the word direction, and provided at each intersection of the connection line and the word line, between the word line and the connection line. Switching means for switching signals; control means for controlling switching of all the switching means;
Storage means comprising: