JP3474474B2 - Semiconductor memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a technique of storing an address of a defective memory cell (error cell) and using a spare memory cell instead of the defective memory cell.

[0002]

2. Description of the Related Art In a semiconductor memory such as a DRAM, the address of a cell determined to be defective at the time of inspection is written in a defective address memory which is a non-volatile memory, and the defective address memory is read from this defective address memory immediately after the computer is powered on. Is read out and stored in the register, and the address decoder is modified based on the output of this register.

FIG. 9 shows a circuit example for performing such processing, that is, a circuit example for separating a defective cell from an address space. 1 is a memory area composed of memory cells 10,
11 to 14 are drivers for selecting a word line corresponding to an address, and F1 to F4 are flip-flops for selecting the drivers 11 to 14, respectively, and a defective address is read from a register (not shown) An inhibition signal is output from the corresponding flip-flop F1 (F2 to F3) to the driver 11 (12 to 14). As a result, even if the address is read from the CPU, the corresponding cell is not selected, and a cell in a spare memory area (not shown) provided separately is selected instead. In this example, the "row" cell group including the defective address is not selected in the memory area.

[0004]

The circuit described above has each "row".
Since a control line for separating these memory cells from the memory area is provided for each memory cell group, there is a problem that the chip area required for the control line increases, and a CPU is provided in the spare memory area. Since a part of the managed address space is allocated, a wide address space is required, and the number of address lines increases accordingly.

The present invention has been made under these circumstances, and an object thereof is to suppress an increase in chip area in a semiconductor memory device in which a defective memory cell of a main memory is replaced with a spare memory. To do.

[0006]

According to a first aspect of the present invention, there is provided a semiconductor memory device for selecting a memory cell of a spare memory when an address appearing on a system address bus corresponds to a defective memory cell of the main memory. A defective address memory in which an address (defective address) corresponding to a cell is written in advance is compared with an address appearing on the system address bus and a defective address stored in the defective address memory, and when both match, a match signal is output. A memory address bus for giving an address to the main memory and the spare memory, and a spare memory address output unit for outputting a spare memory address which is an address for selecting a memory cell of the spare memory. , When the match signal is not output from the comparison unit, the memory address is The bus to the system address bus side,
Further, when a coincidence signal is output, switching means for switching and connecting the memory address bus to the spare memory address output section side, and when a coincidence signal is not output from the comparison section, it is connected to the main memory decoder. Validating the input of the address and invalidating the input to the decoder of the spare memory, and invalidating the input of the address to the decoder of the main memory when the coincidence signal is output from the comparison unit, and Decoder control means for enabling input to the decoder of the spare memory.

The decoder control means has a control signal line common to each driver of the main memory decoder and each driver of the spare memory decoder in at least one of the word line and the bit line. And the signal input to the driver of the main memory and the signal input to the driver of the auxiliary memory are in an inverse relationship, and each driver of the decoder of the main memory is controlled by the control signal appearing on the control signal line. It is possible to configure such that the drivers of the spare memory are collectively brought into the inoperative state (inoperative state) and the inoperative state (inoperative state) is collectively provided (the invention of claim 2).

[0008]

[0009]

[0010]

[0011]

1 is a circuit diagram showing an embodiment of a semiconductor memory device of the present invention, and FIG. 2 shows a data processing device such as an MCU (micro controller unit) to which this memory device is applied. FIG. In the figure, 2 is a data bus, 21 is a CPU (central processing unit), and 3 is an address bus. In this example, the CPU of the configuration of FIG.
When a portion other than 21 is called a memory device, the memory device has a main memory 4 which is a non-volatile memory such as a flash memory for storing data, and an address of a defective memory cell included in the main memory 4. A defective address memory 22 which is a nonvolatile memory in which (hereinafter referred to as a defective address) is written in advance, and a spare memory (redundant memory) 5 to which spare memory cells used in place of the defective memory cells in the main memory 4 are allocated. I have it.

Further, in FIG. 1, reference numerals 40 and 50 denote memory cells each formed of a transistor. In this example, the main memory 4 and the spare memory 5 are provided by being allocated to different memory areas in a common memory chip, and the bit line BL is shared by the memory cells 40 and 50. The main memory 4 and the spare memory 5 are not limited to being provided in the common memory array, but may be provided in separate memory arrays. WL is a word line.

Reference numerals 41 to 44 are word lines WL of the main memory 4.
, A driver forming a part of the decoder, 51 and 52 selecting a memory cell group 50 corresponding to each word line WL of the spare memory 5,
It is a driver that constitutes a part of the decoder. These drivers 41 to 44, 51, 52 have an input end ina connected to the address bus 31 and an input end inb connected to the control signal line A2. The control signal line A2 sends a control signal for operating or inactivating the drivers 41 to 44, 51, 52. The drivers 41 to 44,
51 and 52 are in an operating state when a signal of logic "1" is input to the input terminal ina, and are in a non-operation state when a signal of logic "0" is input. That is, in this example, the input of the address signal becomes valid when the enable signal "1" is input.

In the above description, for convenience of explanation, for example, the lower 2 bits appearing on the system address bus 3 are the word lines WL.
In the address bus, the signal lines corresponding to the word line WL are composed of the signal lines A0 and A1 and are attached to the input sides of the drivers 41 to 44, 51 and 52. Codes such as A0 and A1 are assigned to signal lines A0 and A, respectively.
1 represents the signal level output. In the figure, an overline is added as an inverted signal of the signal level, but in the specification, due to the limitation of the word processor used, A
The inverted signal of 0 is described as "-A0". Therefore, for example, when "1" appears on the control signal line A2, the drivers 41 to 41
“-A2”, that is, “0” is input to 44, 51, and 52.

Further, this memory device is provided with a register 61, and the defective address written in the defective address memory 22 is copied to this register 61 when the power of the data processing device is turned on. In this example, this defective address is an address that specifies the "row" containing the error cell of the main memory 4. 62 is a comparator which is a comparison unit.
When the address output to the address bus 3 and the address held in the register 61 match, the comparator 62 outputs a signal "1", for example, a spare memory address output unit 63 and a switch described later. Parts S1 and S
2 is output. In this example, the defective address of the main memory 4 (specifically, the lower two addresses that specify the “row” of the defective address)
Since the bit) is set to two of "00" and "10", the register 61 is composed of two registers 61a and 61b which respectively hold these defective addresses, and a comparator corresponding to this. Reference numeral 62 is composed of two comparators 62a and 62b.

The spare memory address output unit 63 shown at 63 is composed of address output units 63a and 63b for outputting the addresses of the spare memory 5, respectively. Each address output unit 63 is provided from the comparator 62. When the signal "1" is input, the 2-bit data corresponding to the address of the spare memory 5 is transferred to the address bus 32.
Are output to the signal lines A0 and A1. Further, these address output units 63a and 63b output a signal "1" to the control signal line A2 in addition to the address of the spare memory 5. Although the term “address bus” is used with reference numerals 3, 31, 32, 3 is called a system address bus, 31 is a memory address bus, and 32 is a spare memory address bus in order to avoid confusion of terms.

The switch unit S1 is a memory address bus 31.
System address 3 or spare memory address bus 3
A switching means for connecting to one of the two
The former is selected on the C side and the latter is selected on the contact NO side. The switch section S2 connects the control signal line A2 to the ground (contact NC side) or to the floating terminal (contact NO side). The switch section S2 and the control signal line form a decoder control means.

Next, the operation of the above embodiment will be described. The address of the main memory 4 is output from the CPU 21,
If the address is normal, register 61a (61
Since the address (defective address) held in b) does not match the address appearing on the system address bus 3, both outputs of the comparators 62a and 62b are "0", and the switch sections S1 and S2 are Are switched to the NC side (state in FIG. 1). Therefore, since the control signal line A2 is connected to the ground, the signal "-A2", that is, "1" is input as an enable signal to the input terminals inb of the drivers 41 to 44, and the drivers 41 to 44 operate. It becomes a state. At this time, the input ends of the drivers 51 and 52 in
A signal "A2", that is, "0", is input to b as a prohibition signal, the drivers 51 and 52 are deactivated, and the spare memory 5 is not accessed.

On the other hand, since the system address bus 3 is connected to the memory address bus 31, the driver corresponding to the address appearing on the system address bus 3 is driven.
In this example, "00" and "10" are set as defective addresses for the sake of description. Therefore, for example, the driver 43 is driven with respect to the normal address "01", and the word line W which is the output line thereof.
The memory cell 40 connected to L is selected, and as a result, the data intersecting the selected bit line BL is read.

On the other hand, when the address of the main memory 4 output from the CPU 21 is the address (defective address) corresponding to the defective memory cell 40, for example, "00".
If so, the address held in the register 61a and the address appearing on the system address bus 3 match, so that "1" is output from the comparator 62a,
Both the switch units S1 and S2 are switched to the N0 side.
Therefore, the switch signal S2 side of the control signal line A2 is in a floating state, and the control signal line A2 changes from the spare address output unit 63a.
The signal "1" output to the driver 51, 52 is input as an enable signal to the input terminals inb of the drivers 51, 52, and the drivers 51, 52 are brought into an operating state. At this time, the driver 41
The signal "-A2", that is, "0", is input to the input ends inb of the drivers ~ 44 as the prohibition signal, and
Becomes inoperative, and the main memory 4 is not accessed.

On the other hand, the signal "1" from the comparator 62a.
By this, the address of the spare memory 5 (spare address) from the spare address output unit 63a to the spare memory address bus 32
For example, "01" is output. Since the spare memory address bus 32 is connected to the memory address bus 31, the driver 51 is driven and the memory cell 50 connected to the word line WL which is the output line thereof is selected. As a result, the data intersecting the selected bit line BL is read.

According to this embodiment, the drivers 41 to 44 of the main memory 4 and the drivers 51 and 5 of the spare memory 5 are used.
A common control signal line A2 for enabling one of the two and the other for invalidating the other is provided, and the comparator 62 monitors whether or not the address appearing on the system address bus 3 is a defective address. , This comparator 63
Since the signal level of the control signal line A2 is switched on the basis of the output of, the number of the control signal line A2 is sufficient, and the wiring area can be narrowed.

Further, the spare memory 5 is accessed while the memory address bus 31 is disconnected from the system address bus 3, and normally, the drivers 51 and 52 of the spare memory 5 are disabled by the control signal A2. Therefore, the address of the spare memory 5 generated on the memory address bus 31 is independent of the address space managed by the CPU 21. Therefore, the address of the spare memory 5 can be freely determined without worrying about the address managed by the CPU 21, and is particularly effective when there is no room to add the spare memory to the address space prepared for the memory. It is a technique. Since it is only necessary to prepare the minimum address space required by the system, the number of address signal lines is reduced, and the wiring area is also reduced from this point, reducing the chip area and reducing die cost. Moreover, since unnecessary charge-up of the address signal line is not performed, power consumption can be reduced and reliability can be improved.

A preferred example of a method of writing the defective address written in the defective address memory 22 into the register 61 will be described below. Figure 3 shows MC
8 is a time chart showing the rise of the power supply voltage (vdd) in the MCU, the rise of the clock signal, and the reset status when the power supply of U is turned on at time t1. Generally M
In the CU, the power supply voltage (vdd) rises to a predetermined value and is in a reset state in which writing to the register is prohibited until time t2 when the clock signal stabilizes.
At time t2, the reset is released and the register is written.

When writing a defective address to the register 61, resetting is not performed, and even if it is unstable, the defective address is read out to the register 61 by a clock signal and sequentially overwritten by the next clock. In this way, even if the data in the register 61 is not correct at first, when the reset is released, the correct data, that is, the defective address is written in the register 61. Therefore, when the MCU starts processing,
Even if the defective address of the main memory 4 is accessed, it is transferred to the spare memory 5, so that the data processing is not hindered, and the write processing to the register 61 does not have to be performed after the MCU is on standby. Processing can be performed.

In the above-described embodiment, when the main memory 4 has a defective memory cell, the word line WL including the defective memory cell is invalidated, and the word line W of the spare memory 5 is transferred to the memory cell group included in the "row". Although the memory cell of the spare memory 5 is replaced with the spare memory 5, the bit line BL including the defective memory cell of the main memory 4 is invalidated and transferred to the bit line W of the spare memory 5, and the spare memory cell group included in the “column” is spared. It may be configured to replace the memory cell of the memory 5, and in this case, the defective address is stored in a register as a higher-order address for identifying the bit line, and the driver of the column decoder of the main memory 4 and the spare memory 5 is used. On the other hand, the same configuration as that of the above-described embodiment may be adopted.

In the embodiment shown in FIG. 1, the CPU 2
If the address managed by 1 has a vacancy, that is, if there is an unused address, the vacant address may be assigned to the address of the spare memory 5. In this case, the control switch S2 and the control signal line A2 may be omitted. Because the addresses of the main memory 4 and the spare memory 5 are different from each other, and even when the switch S1 is switched to the system address bus 3 side, it is the same as the device such as the interface connected to the CPU 21. This is because the address never appears in the memory address 31.

FIG. 4 is a diagram showing still another embodiment of the present invention. This example is different from the device of FIG. 1 in that the spare address output unit 63 is not used and the outputs of the respective comparators 62a and 62b forming the comparison unit are used as the selection signals of the respective rows of the spare memory 5. It can be used when the number of memory cells 50 of the memory 5 is small. That is, the output signal lines of the comparators 62a and 62b are connected to the gates of the memory cells 50 in each row of the spare memory 5, respectively. In this case, the memory address bus 31 and the switch unit S1 for switching the address bus are not necessary, and the drivers 41 to 44 forming the decoder of the main memory 4 are directly connected to the system address bus 3.

Further, in order to prevent the main memory 4 from being selected when a defective address occurs on the system address bus 3, a control signal line A2 having one end connected to the control input end inb of the drivers 41 to 44 is provided. There is. The switch section S3 provided at the other end of the control signal line A2 is on the ground side when the outputs of the comparators 61a and 61b are both "0", and is on the power source V when either is "1".
It is configured to switch to the dd side.

Therefore, when the address corresponding to the normal memory cell 40 is generated on the system address bus 3, the switch section S3 is switched to the ground side, so that the drivers 41 to 44 are in the enable state. The memory cell of the corresponding row of the main memory 4 is selected. At this time, the outputs of the comparators 61a and 61b are both "0", and the spare memory 5 is not accessed. On the other hand, when a defective address is generated on the system address bus 3, the switch section S3 is switched to the Vdd side and the comparator is turned on.
Since the output of the data 61a (61b) becomes "1", the access to the main memory 4 is prohibited and the spare memory 5 is accessed.

Next, another embodiment of the present invention will be described. FIG. 5 is an explanatory view for explaining the outline of this embodiment, and FIG. 6 is a circuit diagram showing the same embodiment. . M1 is a first memory array and M2 is a second memory array, both of which are, for example, flash memories. The word line WL (horizontal line "row") of the memory array M1 and the word line WL of the memory array M2 are respectively connected to a first row decoder RD1 and a second row decoder RD2.
Selected by. In the memory array M1, the memory cells 7 belonging to the vertical line from the side of the row decoder RD1.
0 in the first column, the second column, ... In the memory array M2,
When the memory cells 70 belonging to the vertical line from the row decoder RD2 side are called the first column, the second column ... The bit lines BL corresponding to the same column of both memory arrays M2, M2 are column decoders. It is selected (decoded) by the CD at the same time. Note that the transistors forming the memory cell 70 are conveniently shown as squares in FIG. 5 and circles in FIG. 6, and the number thereof is also convenient due to the restriction of the area in the drawing.

In the memory array M1 (M2), the memory cells 70 included in one predetermined row, for example, the memory cells in the last row are used as the spare memory 71 (81), and the other memory cells are used as the main memory 72 (82). Used as. Then, of the addresses appearing on the address bus (system address bus) 3, the bit line BL is, for example, by the upper bit,
The word line WL is selected from the main memories 72 and 82 by the lower bit.

Regarding selection of the word line WL of the spare memory 71 (81), the main memory 7 of the first memory array M1 is selected.
When the second word line WL is selected, the word line WL of the spare memory 81 of the second memory array M2 is selected,
Word line WL of the main memory 82 of the second memory array M2
When is selected, the word line WL of the spare memory 71 of the first memory array M1 is selected. In order to perform such an operation, for example, in the row decoder RD1 (RD2), an OR circuit for the output of each word line WL is incorporated,
The output of the OR circuit may be used as the signal on the word line WL of the spare memory 81 (71).

Reference numerals 73 and 83 denote the first memory array M, respectively.
This is a sense amplifier that reads out the data of the first and second memory arrays M2 and outputs it to the data bus 2. For example, when the memory cell 70 of the nth row and the mth column of the main memory 72 of the memory array M1 is selected. The data of the memory cell 70 is read by the sense amplifier 73. Further, at this time, the memory cell 70 in the m-th column of the spare memory 81 of the second memory array M2 is selected and its data is read by the sense amplifier. Here, in this embodiment, the main memory 72
When the defective memory cell 70 is included in (82), the defective memory cell 70 is replaced with the spare memory 81 of the second memory array M2 (spare memory 71 of the first memory array M1). I have to.

This state is shown in FIG. For example, main memory 7
If the memory cells A in the first column and the second row of 2 are defective,
The data to be written in this memory cell A is written in advance in the memory cell A in one column of the spare memory 81. By processing in this way, when the defective memory cell A of the main memory cell 72 is selected, the memory cell A of the spare memory 81 which is an alternative to the defective memory cell A is selected and read by the sense amplifier 83. Therefore, the read data of the sense amplifier 83 may be output to the data bus 2. In FIG. 5, the capital letters written in the main memories 72 and 82 are defective memory cells, and the spare memories 71 and 8 to which these defective memory cells are transferred.
The corresponding alphabet is attached to one memory cell. However, if there are two or more defective memory cells in one column of the main memory 72 (82), they are excluded as defective products at the inspection stage. Even if there are defective memory cells, the number is one.

By the way, the selected main memory 72 (8
If the memory array 70 of 2) is normal, one sense amplifier 73 (8
3) to the data bus 2 to output the defective memory array 70.
When it is selected, it is necessary to output from the other sense amplifier 83 (73) to the data bus 2. Therefore, in order to switch the sense amplifier 73 (83), the register 91 and the register 91 The comparator 92 is used, and the sense amplifier 7 is provided in accordance with the output of the comparator 92.
A switch unit 10 provided between the data bus 3 and 83 and the data bus 2.
Switching between 0 and 200 is performed.

Next, a circuit for switching the register 91, the comparator 92 and the switch units 100 and 200 will be described with reference to FIG. Register 91
Register 9 to which the defective address of the main memory 72 is written
1-1 and 91-2, and registers 91-3 and 91-4 into which the defective address of the main memory 82 is written. The comparator 92 includes comparators 92-1 and 92-2 which output the comparison results a1 and a2 when the defective address of the main memory 72 appears on the address bus 3, and the defective address of the main memory 82. A comparator 9 for outputting the comparison results b1 and b2 respectively when they appear on the bus 3.
2-3 and 92-4. And the switch unit 10
0 (200) is the above-mentioned comparison result a1, a2, b1, b
2 and a selection signal output when the row decoder RD1 (RD2) selects any word line WL, the on / off control is performed by the logic of FIG. 7, and the OR circuit 104 (204 ), The switch is closed when "1" is input, and the switch is opened when "0" is input. In the figure, 101, 102, 201 and 202 are OR circuits, and 103 and 203 are exclusive OR circuits.
Further, the selection signal from RD1 (RD2) of the row decoder, which is the input signal of the exclusive OR circuit 103, has the same code as the row decoder of the output source for convenience.

For example, if a normal memory cell is selected from the main memory 72, a1 and a2 are "0", and R
Since D1 is "1", the output of the exclusive OR circuit 103 is "1", and the switch unit 100 is closed. On the other hand, in the switch unit 200, b1 and b2 are "0", and R
Since D2 is "0", it is open, and therefore the data read by the sense amplifier 73 is output to the data bus 2.

On the other hand, if a defective memory cell of the main memory 7 is selected, a1 (a2) becomes "1",
Since RD1 is "1", the output of the exclusive OR circuit 103 becomes "0", and the switch unit 100 opens (b1, b).
2 is "0"). On the other hand, the switch unit 200 is closed because a1 (a2) is "1", and therefore the data read by the sense amplifier 83 (this is the spare memory 8
1 data) is output to the data bus 2.

According to such an embodiment, the data can be sent to the data bus 2 earlier than in the previous embodiments.

8A and 8B show how the address signal and the data are determined in the embodiment shown in FIGS. When the address signal is determined at time t1, the data is read from the main memory 72 (82) and the auxiliary memory 81 (71) to the sense amplifier 73 (83) at the same time, and the switching units 100 and 200 are switched. As a result, the data is fixed at time t2.

On the other hand, (c) and (d) of FIG. 8 show how the address signal and data are determined in the embodiment shown in FIGS. In this case, after the address signal is determined, it takes time T for processing such as switching of the switch units S1 and S2, and therefore, the memory cell to be read is determined at the rising time t2 of the clock 1, and The embodiments shown in FIGS. 5 to 7 are more advantageous in terms of processing speed.

In the embodiment shown in FIGS. 5 and 6, the main memory 72 is used.
The same number of memory cells as the number of columns of (82) are used as the spare memory 8
1 (72), but the main memory 72 (8
The same number of memory cells as the number of rows in 2) is prepared as a spare memory, and when the memory cells of the main memory are selected, the memory cells corresponding to the rows of the memory cells selected in the main memory from the spare memory. May be selected.

[0044]

As described above, according to the first and second aspects of the invention, when the semiconductor memory device is configured to transfer to the spare memory when the memory cell of the main memory is defective,
An increase in chip area can be suppressed .

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a main part of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an overall configuration of the above embodiment.

FIG. 3 is a waveform diagram showing how the voltage of each part rises when the power of the computer is turned on.

FIG. 4 is a circuit diagram showing a main part of another embodiment of the present invention.

FIG. 5 is an explanatory diagram showing the outline of still another embodiment of the present invention.

FIG. 6 is a circuit diagram showing a main part of still another embodiment described above.

FIG. 7 is a circuit diagram showing a circuit for switching a switch unit in still another embodiment.

FIG. 8 is a time chart showing how data is determined in the embodiment shown in FIGS. 1 and 6.

FIG. 9 is a circuit diagram showing a part of a conventional semiconductor memory device.

[Explanation of symbols]

2 data buses 22 Bad address memory 3 address bus (system address bus) 31 memory address bus 32 spare memory address bus 4 main memory 40 memory cells 41-44 driver 5 spare memory 50 memory cells 51 driver 61 registers 62 comparator 63 Bad address output section S1, S2 switch section BL bit line WL word line M1 first memory array M2 second memory array 71, 81 spare memory 72, 82 Main memory 73,83 Sense amplifier 91 register 92 Comparator 100, 200 switch RD1, RD2 row decoder CD row decoder

─────────────────────────────────────────────────── --Continued from the front page (56) References JP-A-55-45169 (JP, A) JP-A-61-77946 (JP, A) JP-A-1-307099 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) G06F 12/16 G11C 29/00

Claims (2)

(57) [Claims] 1. In a semiconductor memory device for selecting a memory cell of a spare memory when an address appearing on a system address bus corresponds to a defective memory cell of a main memory, an address (defective address) corresponding to a defective memory cell of a main memory. A pre-written defective address memory, a comparison unit that compares an address appearing on the system address bus with a defective address stored in the defective address memory, and outputs a match signal when the two match. A memory address bus for giving an address to the memory and the spare memory, a spare memory address output unit for outputting a spare memory address which is an address for selecting a memory cell of the spare memory, and a match signal output from the comparison unit When not done,
Switching means for switching and connecting the memory address bus to the system address bus side and the memory address bus to the spare memory address output section side when the match signal is output, and the match signal is not output from the comparison section. Sometimes
When the input of the address to the decoder of the main memory is valid and the input to the decoder of the spare memory is invalid, and when the coincidence signal is output from the comparison unit, the decoder of the main memory is input. And a decoder control means for invalidating the input of the address of the memory and validating the input to the decoder of the spare memory. 2. The decoder control means shares a control signal common to each driver of the main memory decoder and each driver of the spare memory decoder on at least one of the word line and the bit line. The signal input to the driver of the main memory and the signal input to the driver of the auxiliary memory have an inverted relationship, and each driver of the decoder of the main memory is controlled by the control signal appearing on the control signal line. 2. The semiconductor memory device according to claim 1, wherein the memory cells are collectively operated (inactive state) and the drivers of the spare memory are collectively inactive (operating state).